CN113315514A

CN113315514A - Dual-mode spread spectrum clock generator

Info

Publication number: CN113315514A
Application number: CN202110583173.0A
Authority: CN
Inventors: 张兴虎; 罗可欣
Original assignee: Tongfang Industrial Co Ltd
Current assignee: Tongfang Industrial Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2021-08-27
Anticipated expiration: 2041-05-27
Also published as: CN113315514B

Abstract

A dual-mode spread spectrum clock generator is disclosed, which can be used or not used with a delta-sigma modulator. In both modes, quantization noise is suppressed and the jitter of the spread spectrum clock generator is improved. The two modes can be applied to different occasions. If a delta-sigma modulator is used, where the quantization noise is pushed to high frequencies, this mode is suitable for applications where low frequency jitter is relatively important, such as general phase-locked loops for field programmable gate arrays. If a delta-sigma modulator is not used, the quantization noise is now flat across the entire frequency band, which is a suitable mode for applications where low frequency jitter is filtered out by the clock recovery unit, such as phase-locked loops used in transmitters in serial-to-parallel conversion circuits. Therefore, the invention has higher practical value and economic value.

Description

Dual-mode spread spectrum clock generator

Technical Field

The invention relates to the field of clock generators, in particular to a dual-mode spread spectrum clock generator.

Background

In today's high speed data transmission systems, a serial link architecture has become the mainstream. As the data rate of the interface is increased, the internal clock frequency reaches the megahertz range, which makes the Electromagnetic Interference (EMI) become serious. Several techniques are currently available to reduce electromagnetic interference, including masking, pulse shaping, slew rate control, and spread spectrum clocking. Among them, Spread-spectrum Clocking (SSC) is the best performance and lowest cost technology for high-speed systems. The frequency of the clock varies in a triangular waveform with time, and is usually around 30 kHz. A spread spectrum clock generator is a generator that generates a spread spectrum clock.

However, the spread spectrum clock generator in the prior art adopts a single fixed design structure for suppressing quantization noise, so that the spread spectrum clock generator can only be applied to specific application occasions and is lack of adaptability.

Disclosure of Invention

It is an object of the present invention to provide a dual-mode spread spectrum clock generator that solves the aforementioned problems in the prior art.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a dual-mode spread spectrum clock generator comprises a phase-locked loop and a signal generator, wherein the signal generator comprises a phase accumulator, a delta-sigma modulator and a contour generator, the input end of the delta-sigma modulator is directly connected with the output end of the contour generator, and the output end of the delta-sigma modulator is directly connected with the input end of the phase accumulator; the output of the profile generator can be connected directly to the input of the phase accumulator, so that the delta-sigma modulator is not used.

Further, the phase-locked loop includes a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a fractional clock divider. The phase frequency detector has a reference clock input for receiving a reference clock signal, and a loop clock input and output. The charge pump has an input connected to the output of the phase frequency detector and an output. The loop filter has an input connected to the output of the charge pump and an output. The voltage controlled oscillator has an input connected to the output of the loop filter and an output providing an output clock signal. The fractional clock divider has a signal input connected to the output of the voltage controlled oscillator, a control input, and an output connected to the cycle clock input of the phase frequency detector.

Further, the fractional clock divider includes a phase interpolator, a phase rotator, and a multi-modulus divider. The phase interpolator, the phase rotator and the multi-modulus divider are cascaded in sequence.

Further, the resolution of the phase interpolator is 1/16, and the resolution of the phase rotator is 1/8.

The invention has the beneficial effects that:

the invention realizes the dual-mode working state of the spread spectrum clock generator. Bimodulus means that the sigma delta modulator is used or not used. In both modes, quantization noise is suppressed and the jitter of the spread spectrum clock generator is improved. The difference is that the application of the two modes can be different. If a delta-sigma modulator is used, where the quantization noise is pushed to high frequencies, this mode is suitable for applications where low frequency jitter is relatively important, such as general phase-locked loops for field programmable gate arrays. If a delta-sigma modulator is not used, the quantization noise is now flat across the entire frequency band, which is a suitable mode for applications where low frequency jitter is filtered out by the clock recovery unit, such as phase-locked loops used in transmitters in serial-to-parallel conversion circuits. Therefore, the invention has higher practical value and economic value.

Drawings

FIG. 1 is a schematic diagram of a dual-mode spread spectrum clock generator of the present invention;

in the figure, a 1-Fractional Phase-locked loop Fractional-N PLL, a 101-Phase frequency detector PFD, a 102-charge pump CP, a 103-loop filter LF, a 104-voltage controlled oscillator VCO, a 105-Fractional clock Divider Fractional Divider fraction, a 106-Phase interpolator PI, a 107-Phase rotator PR, a 108-multi-modulus Divider MMD, a 2-signal Generator, a 201-Phase Accumulator, a 202-delta sigma modulator SDM, a 203-Profile Generator.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, the dual-mode spread spectrum clock generator of the present invention includes a Fractional phase-locked loop Fractional-N PLL1 and a signal generator 2. Wherein the Fractional phase locked loop Fractional-N PLL1 comprises a phase frequency detector PFD101, a charge pump CP102, a loop filter LF103, a voltage controlled oscillator VCO104 and a Fractional clock Divider Fractional Divider 105. The phase frequency detector PFD101 has a reference clock input for receiving a reference clock signal labeled "Fref", and a loop clock input and output. The charge pump CP102 has an input connected to the output of the phase frequency detector PFD101 and an output. The loop filter LF103 has an input connected to the output of the charge pump CP102 and an output. The voltage controlled oscillator VCO104 has an input connected to the output of the loop filter LF103 and an output providing an output clock signal labeled "Fvco". The Fractional clock Divider Fractional Divider105 has a signal input connected to the output of the voltage controlled oscillator VCO104, a control input, and an output connected to the cycle clock input of the phase frequency detector PFD 101. Fractional clock Divider Fractional Divider105 includes phase interpolator PI106, phase rotator PR107, and multi-modulus Divider MMD 108. In this embodiment, a Fractional clock Divider Fractional Divider105 with a resolution of 1/128 is formed by cascading a phase interpolator PI106 with a resolution of 1/16, a phase rotator PR107 with a resolution of 1/8, and a multi-modulus Divider MMD 108.

The signal Generator2 comprises a Phase Accumulator201, a delta-sigma modulator SDM202, a Profile Generator 203. The Profile Generator203 has an input for receiving a spread spectrum clock Control signal labeled "SSC Control", and an output. The sigma delta modulator SDM202 has an input connectable to the output of the Profile Generator203 and an output. The Phase Accumulator201 has an input connectable to the output of the delta sigma modulator SDM 202. In the state in which the sigma delta modulator SDM202 is not used, the output of the Profile Generator203 can be connected directly to the input of the Phase Accumulator 201. The Phase Accumulator201 also has an output connected to the control input of the Fractional clock Divider Fractional Divider105, and the signals output by the output in this embodiment include a 4-bit PI CW signal, a 3-bit PR CW signal, and an MMD CW signal.

By adopting the technical scheme disclosed by the invention, the following beneficial effects are obtained:

the invention realizes the dual-mode working state of the spread spectrum clock generator. Dual mode refers to the use or non-use of the sigma delta modulator SDM 202. In both modes, the quantization noise is suppressed by-42 dBc and the jitter of the spread spectrum clock generator is improved. The difference is that the application of the two modes can be different. If the sigma delta modulator SDM202 is used, i.e. the input of the sigma delta modulator SDM202 is directly connected to the output of the Profile Generator201, while the output of the sigma delta modulator SDM202 is directly connected to the input of the Phase Accumulator203, the quantization noise will be pushed to high frequencies, which is a mode suitable for applications where low frequency jitter is relatively important, such as a general Phase locked loop of a field programmable gate array. If the sigma delta modulator SDM202 is not used, i.e. the output of the Profile Generator203 is directly connected to the input of the Phase Accumulator201, the quantization noise is now flat over the entire frequency band, which is a suitable mode for applications where low frequency jitter is filtered out by a clock recovery unit, such as a Phase locked loop used in a transmitter in a serial-to-parallel conversion circuit. Therefore, the invention has higher practical value and economic value.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements should also be considered within the scope of the present invention.

Claims

1. A dual-mode spread spectrum clock generator is characterized by comprising a phase-locked loop and a signal generator, wherein the signal generator comprises a phase accumulator, a delta-sigma modulator and a contour generator, the input end of the delta-sigma modulator is directly connected with the output end of the contour generator, and the output end of the delta-sigma modulator is directly connected with the input end of the phase accumulator; the output of the profile generator can be connected directly to the input of the phase accumulator, so that the delta-sigma modulator is not used.

2. The dual-mode spread spectrum clock generator of claim 1, wherein the phase-locked loop comprises a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a fractional clock divider; the phase frequency detector has a reference clock input for receiving a reference clock signal, and a loop clock input and output; said charge pump having an input connected to the output of said phase frequency detector and an output; the loop filter has an input connected to the output of the charge pump and an output; the voltage controlled oscillator having an input connected to the output of the loop filter and an output providing an output clock signal; the fractional clock divider has a signal input connected to the output of the voltage controlled oscillator, a control input, and an output connected to the cycle clock input of the phase frequency detector.

3. The dual-mode spread spectrum clock generator of claim 2, wherein the fractional clock divider comprises a phase interpolator, a phase rotator, and a multi-modulus divider; the phase interpolator, the phase rotator and the multi-modulus divider are cascaded in sequence.

4. The dual-mode spread spectrum clock generator of claim 3, wherein the resolution of the phase interpolator is 1/16 and the resolution of the phase rotator is 1/8.