CN113315492B - Low-overhead precision calibration circuit and method for high-precision delay chain - Google Patents
Low-overhead precision calibration circuit and method for high-precision delay chain Download PDFInfo
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- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
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Abstract
The invention discloses a low-overhead precision calibration circuit and a method for a high-precision delay chain, wherein the circuit comprises: the delay chain comprises more than one delay unit, and the input pulse signal Chainln sequentially passes through the delay units in the delay chain; selecting the output of one delay unit as a final output signal ChainOut; a signal capture circuit for sampling the Chainout signal and accumulating the sampled results; and the control logic unit is used for controlling the sampling of the output signal Chainout signal in the signal capture circuit and controlling the output result of the adder in the signal capture circuit. The method is implemented based on the circuit described above. The invention has the advantages of simple structure, convenient implementation, high precision and the like.
Description
Technical Field
The invention mainly relates to the technical field of integrated circuits, in particular to a low-overhead precision calibration circuit and method for a high-precision delay chain.
Background
High-precision Pulse Width Modulation (HRPWM) is widely applied to the fields of measurement, communication, Digital power supply, motor control and the like, and is an integral part of a modern Digital Signal Controller (DSC).
The pulse precision generated by high-precision pulse width modulation reaches 100ps magnitude, and is usually completed by adopting a delay chain. Namely: a plurality of delay unit circuits capable of generating a certain delay delta for signals are connected in series to form a delay chain, and the path of an input signal on the delay chain is controlled through a control parameter omega so as to accurately control the pulse width. Because δ changes with factors such as operating voltage and temperature of the circuit, the relationship (step length λ) between the system clock period Tsys and δ needs to be continuously calibrated in the circuit operating process, so that the control parameter ω can be accurately calculated. If the delay amount of the rising or falling edge of the pulse to the rising or falling edge of the system clock is epsilon, then:
λ＝Tsys/δ (1)
for example, chinese patent application CN202010168931.8 proposes a method and a circuit for generating ultra-high precision pulses, which can be calibrated temporarily for each pulse based on the relationship (step length λ) between the clock period Tsys and the delay delta of the delay unit in a hardware circuit calibration system. However, this solution not only complicates the hardware calibration circuit, but also increases the power consumption of the system due to unnecessary repeated calibration when the operating environment changes slowly.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a low-overhead precision calibration circuit and method aiming at a high-precision delay chain, which are simple in structure, convenient to implement and high in precision.
In order to solve the technical problems, the invention adopts the following technical scheme:
a low overhead precision calibration circuit for a high precision delay chain, comprising:
the delay chain comprises more than one delay unit, and the input pulse signal Chainln sequentially passes through the delay units in the delay chain; selecting the output of one delay unit as a final output signal ChainOut;
a signal capture circuit for sampling the Chainout signal and accumulating the sampled results;
and the control logic unit is used for controlling the sampling of the output signal Chainout signal in the signal capture circuit and controlling the output result of the adder in the signal capture circuit.
As a further improvement of the calibration circuit of the present invention: a certain delay delta is generated every time the Input signal passes through one delay unit; the output of one delay cell is then selected as the final output signal, ChainOut, based on the information stored in the selection parameter register R2.
As a further improvement of the calibration circuit of the present invention: the number n of the delay units, the delay delta of the delay units and the system clock period Tsys satisfy the following relations:
n×δ≥Tsys。
as a further improvement of the calibration circuit of the present invention: the control logic unit generates latching signals LCKCAP0 and LCKCAP1 according to a system clock SysCLK and a Chainln pulse signal to control sampling of the ChainOut signal in the signal capture circuit.
The control logic unit generates an accumulation enable signal ADDEN according to the values of the threshold register R3 and the counter CNT to control the output result of the adder in the signal capture circuit.
As a further improvement of the calibration circuit of the present invention: the counter CNT operates in the SysCLK domain, starts counting from 0 after the calibration enable signal CALEN is asserted, and stops counting when the threshold set by the threshold register R3 is reached.
As a further improvement of the calibration circuit of the present invention: the signal capturing circuit comprises sampling registers CAP0 and CAP1, adders ADD0 and ADD1 and accumulation registers R0 and R1, and all the elements work in a system clock SysCLK domain.
As a further improvement of the calibration circuit of the present invention: the sampling registers CAP0 and CAP1 respectively sample the high level and the low level of the Chainout signal under the control of the latch signals LCKCAP0 and LCKCAP 1; the adder ADD0 and the register R0 complete the accumulation of the value of the sampling register CAP0 under the control of the accumulation enable signal ADDEN, and the adder ADD1 and the register R1 complete the accumulation of the value of the sampling register CAP1 under the control of the accumulation enable signal ADDEN.
The invention further provides a calibration method based on the circuit, which comprises the following steps:
step S1: initializing; setting the value of the calibration State identification State to be 0, clearing the registers R0-R5, setting the initial value of a threshold register R3, setting the cycle number 2k +1 for high level or low level statistics, and setting the range of a selection parameter register R2; create the accumulation result array AddVec0[0:2 k), AddVec1[0:2k ] used for respectively storing the values of the accumulation registers R0 and R1 after each cycle is finished; setting the value of the calibration State identification State to 1;
step S2: initializing high level statistics; setting the value of a selection parameter register R2 as lambda 0-k, setting the value of a cycle index idx as 0, and setting a control register R4 and enabling a CALEN signal; setting the value of a calibration State identifier State to be 2;
step S3: completing the high level statistics for one time; entering a calibration procedure, and if the calibration State identification State value is 2, detecting whether the counter CNT reaches a threshold value; if not, then exiting the calibration procedure, executing other procedures: if so, the value of the accumulation register R0 is saved in the accumulation result array AddVec0[0:2k ] the position indicated by the cycle index idx, setting the value of the calibration State identifier State to 3, exiting the calibration procedure, and executing other procedures;
step S4: high level statistics completion confirmation; if the calibration State identification State value is 3, adding 1 to the cycle index idx value;
step S5: initializing low level statistics; if the value of the calibration State identifier State is 4, setting the value of the calibration State identifier State to be 5 after the calibration is finished;
step S6: completing the low level statistics for one time; if the calibration State identification State value is 5, detecting whether the counter CNT reaches a threshold value; if not, exiting the calibration program and executing other programs; if so, the value of the accumulation register R1 is saved in the accumulation result array AddVec1[0:2k ] the value of the calibration State identification State is set to 6 at the position indicated by the cycle index idx;
step S7: low level statistics complete validation;
step S8: the current step size lambda is calculated.
As a further improvement of the calibration method of the present invention: the step S8 includes the following steps:
step S801: for the accumulation result array AddVec0[0:2k +1 item in 2k ], searching a first item smaller than the characteristic value psi from the 0 th item, and setting the item as AddVec0[ alpha ]; for the accumulation result array AddVec1[0:2k +1 item in 2k ], starting from item 0, searching a first item which is larger than the characteristic value psi, and setting the item as AddVec1[ beta ];
step S802: calculating the offset beta-alpha of the current step length lambda relative to the initial step length lambda 0, and further obtaining the value of the current step length lambda; namely:
AddVec0[ alpha ] < psi, where alpha is a positive integer and 0 ≦ alpha ≦ 2k
AddVec1[ beta ] > psi, where beta is a positive integer and 0 ≦ beta ≦ 2k
λ＝λ0+β-α
The characteristic value ψ is set in advance in accordance with the physical characteristics of the delay chain and the value of the threshold register R3, so that it is expressed in the above equation that when the latch signals LCKCAP0, LGKCAP1 are sampled by the system clock SysCLK, the input pulse Chainln propagates to the input terminals of the sampling registers CAP0, CAP1, and is captured by the registers CAP0, CAP 1.
Compared with the prior art, the invention has the advantages that:
the low-overhead precision calibration circuit and method aiming at the high-precision delay chain have the advantages of simple structure, convenience in implementation and high precision, the low-overhead delay calibration method is realized by adopting a mode of combining software and hardware, the hardware circuit is simple, the software overhead can be ignored, and the low-overhead precision calibration circuit and method are more suitable for a high-precision pulse width modulation system with slowly-changing working environment.
Drawings
Fig. 1 is a schematic diagram of the structure of the calibration circuit of the present invention.
FIG. 2 is a flow chart of the calibration method of the present invention.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples.
The low-overhead precision calibration method is a method for calculating the relation (step length lambda) between the clock period Tsys of the system and the delay delta of the delay unit based on a hardware circuit and a software process. The step information λ may be stored in a software data structure or in a dedicated register for reading by a user program to calculate the value of the control parameter ω required to accurately control the pulse width with high precision.
As shown in fig. 1, a low overhead precision calibration circuit for high precision delay chain of the present invention comprises:
the delay chain comprises more than one delay unit, and the input pulse signal Chainln sequentially passes through the delay units in the delay chain; selecting the output of one delay unit as a final output signal ChainOut;
a signal capture circuit for sampling the Chainout signal and accumulating the sampled results;
and the control logic unit is used for controlling the sampling of the output signal Chainout signal in the signal capture circuit and controlling the output result of the adder in the signal capture circuit.
In a specific application example, a certain delay δ is generated every time a signal Input is Input through one delay unit; the output of one delay cell is then selected as the final output signal, ChainOut, based on the information stored in the selection parameter register R2.
In a specific application example, the number n of the delay units, the delay delta of the delay units and the system clock period Tsys satisfy the following relationship
n×δ≥Tsys (3)
In a specific application example, the control logic unit generates latching signals LCKCAP0 and LCKCAP1 according to a system clock SysCLK and a Chainln pulse signal to control sampling of the ChainOut signal in the signal capturing circuit.
In a specific application example, the control logic unit generates the accumulation enable signal ADDEN according to the values of the threshold register R3 and the counter CNT to control the output result of the adder in the signal capture circuit.
In a specific application example, the counter CNT operates in the SysCLK domain, starts counting from 0 after the calibration enable signal CALEN is asserted, and stops counting when the threshold set by the threshold register R3 is reached.
In a specific example of an application, the calibration enable signal CALENN is a bit in the control register R4 (R4 is not explicitly shown in FIG. 1 for simplicity).
In a specific application example, the signal capturing circuit comprises sampling registers CAP0 and CAP1, adders ADD0 and ADD1, and accumulation registers R0 and R1, and all the elements work in a system clock SysCLK domain. In a preferred embodiment, the sampling registers CAP0 and CAP1 sample the high level and the low level of the ChainOut signal respectively under the control of the latch signals LCKCAP0 and LCKCAP 1. The adder ADD0 and the register R0 complete the accumulation of the value of the sampling register CAP0 under the control of the accumulation enable signal ADDEN, and the adder ADD1 and the register R1 complete the accumulation of the value of the sampling register CAP1 under the control of the accumulation enable signal ADDEN.
The values in the accumulation registers R0 and R1 are positive integers.
As shown in fig. 2, the present invention further provides a low overhead precision calibration method for a high precision delay chain, which includes:
step S1: and (5) initializing.
In a specific application example, the tasks completed in the initialization stage are as follows:
1) setting the value of the calibration State flag State to 0;
2) clear registers R0-R5, set the initial value of the threshold register R3 (e.g., set R3 to 65535);
3) the number of cycles 2k +1 for performing high level or low level statistics is set, and the range of the selection parameter register R2 is set:
4) create the accumulation result array AddVec0[0:2 k), AddVec1[0:2k ] used for respectively storing the values of the accumulation registers R0 and R1 after each cycle is finished;
5) setting the value of the calibration State identification State to 1; 6) and exiting the calibration procedure and executing other procedures. The relationship among the cycle number 2k +1, the selection parameter register R2, and the initial step value λ 0 is:
λ 0-k ≦ R2 ≦ λ 0+ k, k < λ 0, k being a positive integer (4)
Or:
2 lambda 0-k R2 is 2 lambda 0+ k, k is < lambda 0, k is a positive integer (5)
The initial value λ 0 of the step size can be obtained by using a default value of the system or a static calibration method in a conventional method. The present patent does not relate to the calculation of the initial value of the step size λ 0.
Step S2: and initializing high-level statistics.
When the calibration program is entered again, if the value of the calibration status flag State is 1, the following procedures are executed:
step S201: the selection parameter register R2 is set to a value of λ 0-k. In step 2, the relationship of the parameter register R2 and the initial step value λ 0 is selected to satisfy the equation (4).
Step S202: the cycle index idx is set to 0. The value range of the cycle index idx is more than or equal to 0 and less than or equal to 2 k.
Step S203: setting a control register R4, enabling a CALEN signal;
step S204: setting the value of a calibration State identifier State to be 2;
step S205: and exiting the calibration procedure and executing other procedures.
Step S3: one high level statistic is completed.
When the calibration procedure is entered again, if the calibration status flag State value is 2, it is detected whether the counter CNT reaches the threshold value. If not, exiting the calibration program and executing other programs; if so, the value of the accumulation register R0 is saved in the accumulation result array AddVec0[0:2k ] indicated by the cycle index idx, the value of the calibration status flag State is set to 3, the calibration procedure is exited, and other procedures are executed.
AddVec0[idx]＝R0 (6)
Step S4: high statistics complete validation.
When entering the calibration procedure again, if the calibration status flag value is 3, first add1 to the cycle index idx value, and execute the following procedure:
step S401: if idx is larger than or equal to 2k, setting the value of a calibration State identifier State to be 4, exiting the calibration program and executing other programs;
step S402: and if idx is less than 2k, adding 1 to the value of the selection parameter register R2, clearing the counter CNT, clearing the accumulation register R0, clearing the CALEN enable signal in the control register R4 to be 1, setting the value of the calibration State identifier State to be 2, exiting the calibration program and executing other programs.
Step S5: and initializing low level statistics.
When the calibration program is entered again, if the calibration State flag State value is 4, the following procedures are executed:
step S501: the selection parameter register R2 is set to a value of 2 λ 0-k. In step 5, the relationship of the parameter register R2 and the initial step value λ 0 satisfying equation (5) is selected.
Step S502: the cycle index idx is set to 0. The value range of the cycle index idx is more than or equal to 0 and less than or equal to 2 k.
Step S503: setting a control register R4, enabling a CALEN signal;
step S504: setting the value of a calibration State identifier State to be 5;
step S505: and exiting the calibration procedure and executing other procedures.
Step S6: one low level statistic is completed.
When entering the calibration procedure again, if the calibration status flag State value is 5, it is detected whether the counter CNT reaches the threshold value. If not, exiting the calibration program and executing other programs; if so, the value of the accumulation register R1 is saved in the accumulation result array AddVec1[0:2k ] indicated by the cycle index idx, the value of the calibration status flag State is set to 6, the calibration procedure is exited, and other procedures are executed.
AddVec1[idx]＝R1 (7)
Step S7: the low level statistics complete the acknowledgement.
When entering the calibration procedure again, if the calibration status flag value is 6, first add1 to the cycle index idx value, and then execute the following procedures:
step S701: if idx is larger than or equal to 2k, setting the value of the calibration State identifier State to be 7, exiting the calibration program and executing other programs;
step S702: and if idx is less than 2k, adding 1 to the value of the selection parameter register R2, clearing the counter CNT, clearing the accumulation register R1, clearing the CALEN enable signal in the control register R4 to be 1, setting the value of the calibration State identifier State to be 5, exiting the calibration program and executing other programs.
Step S8: the current step size lambda is calculated.
The step S8 includes the following steps:
step S801: for the accumulation result array AddVec0[0:2k +1 items in 2k ], searching a first item which is smaller than the characteristic value psi (set as 32768) from the 0 th item, and setting the item as AddVec0[ alpha ]; for the accumulation result array AddVec1[0:2k +1 entry in 2k ], the first entry larger than the eigenvalue ψ (e.g., set to 32768) is found from entry 0, and this entry is assumed to be AddVec1[ β ].
Step S802: and calculating the offset beta-alpha of the current step length lambda relative to the initial step length lambda 0, and further obtaining the value of the current step length lambda. Namely:
AddVec0[ alpha ] < psi, where alpha is a positive integer and 0 ≦ alpha ≦ 2k (8)
AddVec1[ beta ] > psi, where beta is a positive integer and 0. ltoreq. beta.ltoreq.2k (9)
λ＝λ0+β-α (10)
The characteristic value ψ is set in advance in accordance with the physical characteristics of the delay chain and the value of the threshold register R3, so that expressions (8) and (9) indicate that when the latch signals LCKCAP0 and LCKCAP1 are sampled by the system clock SysCLK, the input pulse Chainln can stably propagate to the input terminals of the sampling registers CAP0 and CAP1 and thus be captured by the registers CAP0 and CAP 1.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (5)
1. A low overhead precision calibration circuit for a high precision delay chain, comprising:
the delay chain comprises more than one delay unit, and the input pulse signal ChainIn sequentially passes through the delay units in the delay chain; selecting the output of one delay unit as a final output signal ChainOut;
a signal capture circuit for sampling the Chainout signal and accumulating the sampled results;
the control logic unit is used for controlling the sampling of the output signal Chainout signal in the signal capture circuit and controlling the output result of the adder in the signal capture circuit;
the control logic unit generates latching signals LCKCAP0 and LCKCAP1 according to a system clock SysCLK and a ChainIn pulse signal so as to control the sampling of a ChainOut signal in the signal capturing circuit; the control logic unit generates an accumulation enable signal ADDEN according to the values of the threshold register R3 and the counter CNT so as to control the output result of an adder in the signal capture circuit;
the signal capturing circuit comprises sampling registers CAP0 and CAP1, adders ADD0 and ADD1 and accumulation registers R0 and R1, and all the elements work in a system clock SysCLK domain;
the sampling registers CAP0 and CAP1 respectively sample the high level and the low level of the Chainout signal under the control of the latch signals LCKCAP0 and LCKCAP 1; the adder ADD0 and the register R0 complete the accumulation of the value of the sampling register CAP0 under the control of the accumulation enable signal ADDEN, and the adder ADD1 and the register R1 complete the accumulation of the value of the sampling register CAP1 under the control of the accumulation enable signal ADDEN.
2. The low-overhead precision calibration circuit for a high-precision delay chain according to claim 1, wherein a certain delay δ is generated every time an Input signal Input passes through one of said delay cells; the output of one delay cell is then selected as the final output signal, ChainOut, based on the information stored in the selection parameter register R2.
3. The low-overhead precision calibration circuit for high-precision delay chains according to claim 2, wherein the number n of delay units, the delay delta of the delay units, and the system clock period Tsys satisfy the following relationship:
n×δ≥Tsys。
4. the low-overhead precision calibration circuit for high-precision delay chains as claimed in claim 1, wherein said counter CNT is operated in the SysCLK domain, starts counting from 0 after the calibration enable signal CALEN is asserted, and stops counting when the threshold set by the threshold register R3 is reached.
5. A calibration method based on the circuit of any one of claims 1-4, comprising:
step S1: initializing; setting the value of the calibration State identification State to be 0, clearing the registers R0-R4, setting the initial value of a threshold register R3, setting the cycle number 2k +1 for high level or low level statistics, and setting the range of a selection parameter register R2; creating accumulation result arrays AddVec0[0:2k ], AddVec1[0:2k ] for respectively storing the values of the accumulation registers R0 and R1 after the end of each cycle; setting the value of the calibration State identification State to 1;
step S2: initializing high level statistics; setting the value of a selection parameter register R2 as lambda 0-k, setting the value of a cycle index idx as 0, and setting a control register R4 and enabling a CALEN signal; setting the value of a calibration State identifier State to be 2; λ 0 is the initial value of step length, k is a positive integer;
step S3: completing the high level statistics for one time; entering a calibration procedure, and if the calibration State identification State value is 2, detecting whether the counter CNT reaches a threshold value; if not, exiting the calibration program and executing other programs; if so, saving the value of the accumulation register R0 in the accumulation result array AddVec0[0:2k ] at the position indicated by the cycle index idx, setting the value of the calibration State identifier State to 3, exiting the calibration procedure, and executing other procedures;
step S4: high level statistics completion confirmation; if the calibration State identification State value is 3, adding 1 to the cycle index idx value; when entering the calibration procedure again, if the calibration status flag value is 3, first add1 to the cycle index idx value, and execute the following procedure:
step S401: if idx is larger than or equal to 2k, setting the value of a calibration State identifier State to be 4, exiting the calibration program and executing other programs;
step S402: if idx is less than 2k, adding 1 to the value of the selection parameter register R2, clearing the counter CNT, clearing the accumulation register R0, clearing the CALEN enable signal in the control register R4 to be 1, setting the value of the calibration State identifier State to be 2, exiting the calibration program and executing other programs;
step S5: initializing low level statistics; if the value of the calibration State identifier State is 4, setting the value of the calibration State identifier State to be 5 after the calibration is finished;
step S6: completing the low level statistics for one time; if the calibration State identification State value is 5, detecting whether the counter CNT reaches a threshold value; if not, exiting the calibration program and executing other programs; if so, the value of the accumulation register R1 is saved in the accumulation result array AddVec1[0:2k ] at the position indicated by the cycle index idx, and the value of the calibration State identification State is set to 6;
step S7: low level statistics complete validation; when entering the calibration procedure again, if the calibration status flag value is 6, first add1 to the cycle index idx value, and then execute the following procedures:
step S701: if idx is larger than or equal to 2k, setting the value of the calibration State identifier State to be 7, exiting the calibration program and executing other programs;
step S702: if idx is less than 2k, adding 1 to the value of the selection parameter register R2, clearing the counter CNT, clearing the accumulation register R1, clearing the CALEN enable signal in the control register R4 to be 1, setting the value of the calibration State identifier State to be 5, exiting the calibration program and executing other programs;
step S8: calculating a current step length lambda; the method comprises the following steps:
step S801: for 2k +1 items in the accumulation result array AddVec0[0:2k ], searching a first item smaller than the characteristic value psi from the 0 th item, and setting the item as AddVec0[ alpha ]; for 2k +1 items in the accumulation result array AddVec1[0:2k ], searching a first item larger than the characteristic value psi from the 0 th item, and setting the item as AddVec1[ beta ];
step S802: calculating the offset beta-alpha of the current step length lambda relative to the initial step length lambda 0, and further obtaining the value of the current step length lambda; namely:
AddVec0[ alpha ] < psi, where alpha is a positive integer and 0 ≦ alpha ≦ 2k
AddVec1[ beta ] > psi, where beta is a positive integer and 0 ≦ beta ≦ 2k
λ＝λ0+β–α
The characteristic value ψ is set in advance in accordance with the physical characteristics of the delay chain and the value of the threshold register R3, so that it is expressed in the above equation that when the latch signals LCKCAP0, LCKCAP1 are sampled by the system clock SysCLK, the input pulse ChainIn propagates to the input terminals of the sampling registers CAP0, CAP1, and is captured by the registers CAP0, CAP 1.
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