CN113315483B - Configurable three-dimensional equalizer based on silicon-on capacitor and parameter design method thereof - Google Patents
Configurable three-dimensional equalizer based on silicon-on capacitor and parameter design method thereof Download PDFInfo
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Abstract
The invention discloses a configurable three-dimensional equalizer based on a silicon-on capacitor, which comprises: the circuit comprises a switch control module SC1, a switch module S1, an injection resistor array R1, a silicon-on capacitor array C1, a switch control module SC2, a switch module S2, an injection resistor array R2 and a silicon-on capacitor array C2, wherein the switch module S1 and the switch module S2 are provided with a control end and a bidirectional port, and the switch control module SC1, the switch control module SC2, the injection resistor array R1, the injection resistor array R2, the silicon-on capacitor array C1 and the silicon-on capacitor array C2 are provided with bidirectional ports; the injection resistor array R1, the through silicon capacitor array C1, the injection resistor array R2 and the through silicon capacitor array C2 are arranged in a silicon substrate. The invention can improve the integration level and reliability of the three-dimensional integrated RC passive equalizer, and has easy configuration and high practicability.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a configurable three-dimensional equalizer based on a silicon-on capacitor and a parameter design method thereof.
Background
In high-speed data transmission techniques, equalization techniques are often used to compensate for the signal to enable a channel of limited bandwidth to transmit a higher signal rate.
In the prior art, for example, patent CN108964627a proposes an RC passive equalization structure for shielding differential through-silicon vias, the structure employs an on-chip resistor and an on-chip capacitor, and the structure may increase the overall longitudinal size and the lateral area of the passive equalization structure, resulting in a lower overall integration level of the passive equalization structure.
In addition, in order to achieve the best working effect of the equalizer in the prior art, parameter information of components such as on-chip resistors and on-chip capacitors and the like generally needs to be derived in the practical application process of the equalizer, the derivation process of the parameter information is complex, a large number of accurate and tedious calculations are needed, process parameters used in the derivation process are also determined by a production line, the production line is generally in commercial secrecy and other factors, and the used process parameter information cannot be published, so that technical personnel cannot accurately and quickly obtain the parameter information, the equalizer is inconvenient to use, and further, differences between the working effect and the design can be caused due to differences of process batches of the production line.
In addition, the prior art has the problem that the balanced structure needs to carry out multilayer wiring on the silicon substrate, so that the complexity and the cost of the process are increased, and the production efficiency and the yield are reduced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a configurable three-dimensional equalizer based on a silicon-on capacitor and a parameter design method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
a through silicon capacitor-based configurable three-dimensional equalizer comprising: the circuit comprises a switch control module SC1, a switch module S1, an injection resistor array R1, a silicon-on capacitor array C1, a switch control module SC2, a switch module S2, an injection resistor array R2 and a silicon-on capacitor array C2, wherein the switch module S1 and the switch module S2 are provided with a control end and a bidirectional port, and the switch control module SC1, the switch control module SC2, the injection resistor array R1, the injection resistor array R2, the silicon-on capacitor array C1 and the silicon-on capacitor array C2 are provided with bidirectional ports; the injection resistor array R1, the through silicon capacitor array C1, the injection resistor array R2 and the through silicon capacitor array C2 are arranged on a silicon substrate; a control end of the switch module S1 is connected to the switch control module SC1, a first bidirectional port of the switch module S1 is connected to a signal input end, and a second bidirectional port of the switch module S1 is connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the silicon-on capacitor array C1, respectively; the second bidirectional port of the injection resistor array R1 and the second bidirectional port of the through silicon capacitor array C1 are respectively connected with a signal output end; a control end of the switch module S2 is connected to the switch control module SC2, a first bidirectional port of the switch module S2 is connected to the signal output end, and a second bidirectional port of the switch module S2 is connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the silicon-on capacitor array C2, respectively; and the second bidirectional port of the injection resistor array R2 and the second bidirectional port of the through silicon capacitor array C2 are respectively connected with the ground wire.
In an embodiment of the present invention, the switch control module SC1 is disposed with a first multiplexer chip, the first multiplexer chip corresponds to an output end, the switch module S1 is disposed with a first switch chip, the first switch chip corresponds to a plurality of first injection resistance switch tubes and a first silicon-on capacitance switch tube; the control end of the switch module S1 is connected to the switch control module SC1, and includes: an output end corresponding to a first multiplexer chip of the switch control module SC1 is connected to a gate of a first injection resistance switching tube and a gate of a first silicon-on capacitance switching tube of the switch module S1 through a control end of the switch module S1; the first bidirectional port of switch module S1 is connected with signal input end, includes: the signal input end is connected with the source electrodes of a first injection resistance switching tube and a first silicon-on capacitance switching tube of the switch module S1 through a first bidirectional port of the switch module S1; the second bidirectional port of the switch module S1 is respectively connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the through silicon capacitor array C1, and includes: a first injection resistance switching tube of the switching module S1 is connected with a first bidirectional port of the injection resistance array R1 through a second bidirectional port; the first through silicon capacitor switch tube of the switch module S1 is connected with the first bidirectional port of the through silicon capacitor array C1 through the second bidirectional port.
In an embodiment of the present invention, the switch control module SC2 is disposed with a second multiplexer chip, the second multiplexer chip corresponds to an output end, the switch module S2 is disposed with a second switch chip, and the second switch chip corresponds to a plurality of second injection resistance switch tubes and second pass silicon capacitor switch tubes; the control end of the switch module S2 is connected to the switch control module SC2, and includes: an output end corresponding to a second multiplexer chip of the switch control module SC2 is respectively connected with a second injection resistance switch tube of the switch module S2 and a grid electrode of a second through silicon capacitor switch tube through a control end of the switch module S2; the first bidirectional port of the switch module S2 is connected to the signal output terminal, and includes: the source electrodes of a second injection resistance switching tube and a second silicon-on capacitor switching tube in the switching module S2 are connected with the signal output end through a first bidirectional port; the second bidirectional port of the switch module S2 is respectively connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the silicon-through capacitor array C2, and includes: a second injection resistance switch tube in the switch module S2 is connected to a first bidirectional port of the injection resistance array R2 through a second bidirectional port of the switch module S2; the second through silicon capacitor switch tube in the switch module S2 is connected to the first bidirectional port of the through silicon capacitor array C2 through the second bidirectional port of the switch module S2.
The invention has the beneficial effects that:
the equalizer provided by the invention can be based on the silicon-on capacitor, has stronger capacitive coupling effect, can improve the integration level of the equalizer and save the cost by using the injection resistor on the silicon substrate, and has simple process and easy application and popularization.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a structural schematic diagram of a configurable three-dimensional equalizer based on a pass-silicon capacitor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a three-dimensional equalizer circuit configurable based on a pass-silicon capacitor according to an embodiment of the present invention;
fig. 3 is a schematic top view of a configurable three-dimensional equalizer circuit based on a pass-silicon capacitor according to an embodiment of the present invention;
fig. 4 is a schematic cross-sectional view along direction AA' of a three-dimensional equalizer circuit configurable based on a pass-silicon capacitor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a configurable three-dimensional equalizer based on a through silicon capacitor according to an embodiment of the present invention, including: the circuit comprises a switch control module SC1, a switch module S1, an injection resistor array R1, a silicon-on capacitor array C1, a switch control module SC2, a switch module S2, an injection resistor array R2 and a silicon-on capacitor array C2.
The switch module S1 and the switch module S2 are disposed with a control end and a bidirectional port, and the switch control module SC1, the switch control module SC2, the injection resistor array R1, the injection resistor array R2, the silicon-on capacitor array C1, and the silicon-on capacitor array C2 are disposed with bidirectional ports.
The bidirectional port includes an input port and an output port. The switch control module SC1 and the switch control module SC2 can be implemented based on a chip or a circuit having preset logic, and the control of the switch module S1 and the switch module S2 can be implemented through corresponding codes.
The invention constructs the equalizer based on the TSC (Through-Silicon Capacitor), which can make the equalizer have stronger capacitance coupling effect, improve the integration level of the equalizer and save the cost.
Optionally, the injection resistor array R1, the through silicon capacitor array C1, the injection resistor array R2, and the through silicon capacitor array C2 are disposed on a silicon substrate.
The silicon substrate refers to a system-level packaging material through which a plurality of circuit chips and different types of devices can be three-dimensionally integrated together to form a complex and complete system.
Compared with the prior art that a plurality of capacitors and resistors are arranged side by side and/or stacked through on-chip capacitors and resistors and are interconnected and combined through more leads to form the equalizer, the invention integrates the injection resistor array and the through silicon capacitor array in the silicon substrate, realizes three-dimensional system-level packaging, can effectively reduce the number of lead interconnections and the area of wiring, reduces crosstalk between an active device and a passive device, improves reliability, reduces the area and the volume of the equalizer, improves the integration level of the equalizer, reduces the manufacturing cost, has higher thermal conductivity, can play a role of a ground layer, and can avoid demetalization.
Optionally, the switch control module controls the switch module through a core particle technology.
The injection resistor array and the silicon-on capacitor array are deployed on the silicon substrate as passive devices, the switch control module and the switch module are realized as active devices in a core particle ChipLet mode, and the crosstalk between the active devices and the passive devices can be reduced while the passive devices have high precision.
The equalizer is also called as an RC (Resistor-capacitor) passive equalizer.
Optionally, the unit resistance values of the resistors in the injection resistor array are the same.
Optionally, the unit capacitance values of the through silicon capacitors in the through silicon capacitor array are the same.
The invention can selectively gate and inject one or more resistors in the resistor array and one or more silicon-on capacitors in the silicon-on capacitor array through the control of the switch control module, thereby changing the numerical values of the resistor array and the capacitor array, rapidly and accurately determining the zero pole frequency, the direct current gain and the high frequency gain of the equalizer, further determining the compensation coefficient, simplifying the calculation process of obtaining the compensation coefficient, improving the accuracy of the compensation coefficient, and solving the problem that the parameter data acquisition in the prior art needs to depend on a production line through a configurable mode.
Optionally, the injection resistor array and the silicon-on capacitor array are disposed with a preset encoding mode, so as to set corresponding parameters of the equalizer.
The preset encoding mode is preset by a person skilled in the art according to service needs, and the present invention is not limited, for example, 8421 codes or temperature codes.
Optionally, a control end of the switch module S1 is connected to the switch control module SC1, a first bidirectional port of the switch module S1 is connected to the signal input end, and a second bidirectional port of the switch module S1 is connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the silicon-on capacitor array C1, respectively.
An input port of the first bidirectional port of the switch module S1 is connected to a signal input terminal, and output ports of the second bidirectional port of the switch module S1 are respectively connected to an input port of the first bidirectional port of the injection resistor array R1 and an input port of the first bidirectional port of the silicon-through capacitor array C1.
Optionally, the switch control module SC1 is disposed with a first multiplexer chip, the first multiplexer chip corresponds to an output end, the switch module S1 is disposed with a first switch chip, and the first switch chip corresponds to a plurality of first injection resistance switch tubes and a first silicon-on capacitance switch tube.
Optionally, the control end of the switch module S1 is connected to the switch control module SC1, and includes: an output end corresponding to the first multiplexer chip of the switch control module SC1 is connected to the gates of the first injection resistance switching tube and the first silicon-on capacitance switching tube of the switch module S1 through the control end of the switch module S1.
Optionally, the first bidirectional port of the switch module S1 is connected to a signal input end, and includes: the signal input end is connected with the source electrodes of the first injection resistance switching tube and the first silicon-on capacitance switching tube of the switch module S1 through the first bidirectional port of the switch module S1.
Optionally, the second bidirectional port of the switch module S1 is respectively connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the through silicon capacitor array C1, and the method includes: a first injection resistance switching tube of the switching module S1 is connected with a first bidirectional port of the injection resistance array R1 through a second bidirectional port; the first through silicon capacitor switch tube of the switch module S1 is connected with the first bidirectional port of the through silicon capacitor array C1 through the second bidirectional port.
Referring to fig. 2, fig. 2 is a schematic diagram of a three-dimensional equalizer circuit configurable based on a pass-silicon capacitor. The first multi-channel selection chip is illustrated by taking four channels as an example, as S 1-1 、S 1-2 、S 1-3 、S 1-4 And the number of the channels of the multi-channel selection chip is set according to the number of the resistors injected into the resistor array and the number of the capacitors in the capacitor array. The first switch chip may be a Metal Oxide Semiconductor (MOS) switch chip, and the first switch chip corresponds to a plurality of first injection resistance switch tubes, such as two MR switch tubes shown in the figure 1-1 And MR 1-2 The first switch chip corresponds to a plurality of first silicon-on capacitive switch tubes, such as two silicon-on capacitive switch tubes MC 1-1 And MC 1-2 The number of the first injection resistance switching tubes is set according to the number of the resistors in the injection resistance array, and the number of the first silicon-on capacitor switching tubes is set according to the number of the capacitors in the capacitor array, it should be noted that, in the present invention, the numbers of the resistors and the capacitors are set by those skilled in the art according to the index requirements, and the present invention is not limited thereto, and the injection resistance array R1 in fig. 2 only uses two resistors, and the silicon-on capacitor array C1 only uses two silicon-on capacitors as an example and is described by way of example.
The signal input may be denoted as V in The resistance switching tube MR 1-1 And MR 1-2 Through the output port of the second bidirectional port of the switch module S1, the injection resistor R on the silicon substrate is connected 1-1 And R 1-2 Connected silicon-through capacitance switch tube MC 1-1 And MC 1-2 Through the output ports of the second bidirectional ports of the switch module S1, respectively connected with the capacitor C 1-1 And C 1-2 And (4) connecting.
Optionally, the second bidirectional port of the injection resistor array R1 and the second bidirectional port of the through silicon capacitor array C1 are respectively connected to a signal output terminal.
Specifically, an output port in the second bidirectional port of the injection resistor array R1 and an output port in the second bidirectional port of the through silicon capacitor array C1 are respectively connected to a signal output terminal. The signal input may be denoted as V in The signal output terminal can be represented as V EQ 。
Optionally, a control end of the switch module S2 is connected to the switch control module SC2, a first bidirectional port of the switch module S2 is connected to the signal output end, and a second bidirectional port of the switch module S2 is connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the silicon-on capacitor array C2, respectively.
An output port of the first bidirectional port of the switch module S2 is connected to the signal output port, and an output port of the second bidirectional port of the switch module S2 is connected to an input port of the first bidirectional port of the injection resistor array R2 and an input port of the first bidirectional port of the through silicon capacitor array C2, respectively.
Optionally, the switch control module SC2 is disposed with a second multiplexer chip, the second multiplexer chip corresponds to the output end, the switch module S2 is disposed with a second switch chip, and the second switch chip corresponds to a plurality of second injection resistance switch tubes and second pass silicon capacitance switch tubes.
Optionally, the control end of the switch module S2 is connected to the switch control module SC2, and includes: an output end corresponding to the second multiplexer chip of the switch control module SC2 is connected to the gates of the second injection resistance switch tube and the second pass silicon capacitance switch tube of the switch module S2 through the control end of the switch module S2.
Optionally, the first bidirectional port of the switch module S2 is connected to the signal output end, and includes: and the source electrodes of the second injection resistance switching tube and the second silicon-through capacitance switching tube in the switching module S2 are connected with the signal output end through the first bidirectional port.
Optionally, the second bidirectional port of the switch module S2 is respectively connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the through silicon capacitor array C2, and the method includes: a second injection resistance switch tube in the switch module S2 is connected to a first bidirectional port of the injection resistance array R2 through a second bidirectional port of the switch module S2; the second through silicon capacitor switch tube in the switch module S2 is connected to the first bidirectional port of the through silicon capacitor array C2 through the second bidirectional port of the switch module S2.
Referring to FIG. 2, the second multi-channel chip is illustrated by taking four channels as an example, as S 2-1 、S 2-2 、S 2-3 、S 2-4 And the number of the channels of the multi-channel selection chip is set according to the number of the resistors injected into the resistor array and the number of the capacitors in the capacitor array. The second switch chip may be an MOS switch chip, and the second switch chip corresponds to a plurality of second injection resistance switch tubes, such as two injection resistance switch tubes MR shown in the figure 2-1 And MR 2-2 The second switch chip corresponds to a plurality of second through silicon capacitive switch tubes, such as two through silicon capacitive switch tubes MC shown in the figure 2-1 And MC 2-2 The number of the second injection resistance switching tubes is set according to the number of the resistors in the injection resistance array, the number of the second silicon-through capacitor switching tubes is set according to the number of the capacitors in the capacitor array, it should be noted that, in the present invention, the numbers of the resistors and the capacitors are set by a person skilled in the art according to business needs, the present invention is not limited, and the injection resistance array R2 in fig. 2 is only provided with two injection resistances R 2-1 And R 2-2 The through silicon capacitor array C2 only uses two through silicon capacitors C 2-1 And C 2-2 Are described by way of example and illustration.
Optionally, the second bidirectional port of the injection resistor array R2 and the second bidirectional port of the through silicon capacitor array C2 are respectively connected to a ground line.
The Ground line may be denoted as GND (Ground).
Optionally, the equalizer further includes: the rewiring layer comprises a front rewiring layer and a back rewiring layer, wherein the rewiring layer is used for carrying out bidirectional port connection; the through silicon via penetrates through the silicon substrate, and the front rewiring layer and the back rewiring layer are respectively positioned on the front surface and the back surface of the silicon substrate; the front rewiring layer is connected with the back rewiring layer through the silicon through hole; the front rewiring layer is connected with the ground wire to form a shielding ring. Fig. 3 is a schematic top view of a three-dimensional equalizer circuit configurable based on a Through Silicon capacitor according to an embodiment of the present invention, where a circle of a dotted line represents a Through Silicon Via TSV (Through Silicon Via), and a rectangle of the dotted line represents a Redistribution Layer RDL (Redistribution Layer).
The rewiring layer can realize circuit connection between the control end and the two-way ports and between the two-way ports, a three-dimensional integrated shielding ring structure can be formed between the front rewiring layer and the back rewiring layer in the rewiring layer and the silicon through hole, and the shielding ring can effectively inhibit electromagnetic interference from a power supply and other circuits, so that the equalizer has high shielding and high reliability performance.
Optionally, the first bidirectional port of the switch module S1 is connected to a signal input end, and the second bidirectional port of the switch module S1 is respectively connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the silicon-on capacitor array C1, including:
a first bidirectional port in the switch module S1 is connected with the signal input end through a front rewiring layer; and the second bidirectional port in the switch module S1 is connected with the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the silicon-through capacitor array C1 through a front rewiring layer.
The second bidirectional port of the injection resistor array R1 is connected to a signal output terminal, and includes: the second bidirectional port of the injection resistor array R1 is connected with the back rewiring layer through a through silicon via; and the second bidirectional port of the injection resistor array R1 is connected with the signal output end through a through silicon via.
The second bidirectional port of the through silicon capacitor array C1 is connected to a signal output terminal, and includes: the second bidirectional port of the through silicon capacitor array C1 is connected with the back rewiring layer through a through silicon via; and the second bidirectional port of the through silicon capacitor array C1 is connected with the signal output end through a through silicon via.
Optionally, a control end of the switch module S2 is connected to the switch control module SC2, a first bidirectional port of the switch module S2 is connected to the signal output end, and a second bidirectional port of the switch module S2 is connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the output end of the silicon-on capacitor array C2, respectively, where the method includes: a first bidirectional port in the switch module S2 is connected with the signal input end through a front rewiring layer; a second bidirectional port in the switch module S2 is connected to a first bidirectional port of the injection resistor array R2 and a first bidirectional port of the silicon-on capacitor array C2 through a front rewiring layer; the second bidirectional port of the injection resistor array R2 is connected to ground, and includes: the second bidirectional port of the injection resistor array R2 is connected with the back rewiring layer through a through silicon via; the second bidirectional port of the injection resistor array R2 is connected with the ground wire through a through silicon via; the second bidirectional port of the through silicon capacitor array C2 is connected to a ground line, and includes: the second bidirectional port of the through silicon capacitor array C1 is connected with the back rewiring layer through a through silicon via; and the second bidirectional port of the through silicon capacitor array C1 is connected with the ground wire through a through silicon via.
The shielding ring can reduce the impedance from the top of the silicon substrate to the ground plane at the bottom, further improve the anti-interference performance of the equalizer, and particularly greatly improve the anti-interference performance of the equalizer when the number of the through silicon vias of the grounding wire is increased.
Referring to fig. 4, a schematic cross-sectional view along direction AA' of a configurable three-dimensional equalizer circuit based on a pass-silicon capacitor according to an embodiment of the present invention is provided.
The equalizer provided by the invention can be based on the silicon-on capacitor, has stronger capacitive coupling effect, can improve the three-dimensional integration level of the equalizer and saves the cost; secondly, the invention can flexibly configure the compensation coefficient of the equalizer by flexibly adjusting the numerical values of the injection resistor array and the capacitor array, so that the equalizer works in an optimal state, related parameter data in a circuit can be quickly acquired, the dependence of the equalizer on a production line in the prior art can be solved, the calculation can be simplified, the calculation accuracy can be improved, and the quality and the reliability of signal transmission can be improved; in addition, the invention can effectively inhibit the electromagnetic interference from a power supply and other circuits through a shielding ring structure formed by a rewiring layer and a silicon through hole based on a silicon substrate, so that the equalizer further has the performances of high integration level, high shielding and high reliability.
Example two
In order to flexibly configure the compensation coefficient of the equalizer, the invention provides a three-dimensional equalizer parameter design method based on silicon-through capacitance configuration, which is applied to the equalizer and comprises the following parameters: transfer function, pole zero, dc gain, high frequency gain, and compensation coefficients. The method comprises the following steps:
wherein, R is 1 Represents the total resistance of the injection resistor array R1, R 2 Represents the resistance of the injection resistor array R2, C 1 Representing the total capacitance of a through-silicon capacitor array C1, C 2 Represents the total capacitance of the capacitor array C2, and S represents the independent variable of the S domain.
wherein, the ω is z Represents the zero point, said ω p Representing the poles.
Step 3, determining the direct current gain and the high frequency gain, and expressing as:
wherein, gain DC Representing the DC Gain, gain HF Indicating the high frequency gain.
Step 4, determining a compensation coefficient, which is expressed as:
the invention can selectively gate one or more resistors in the injection resistor array and one or more silicon-through capacitors in the silicon-through capacitor array through the control of the switch control module, thereby changing the numerical values of the injection resistor arrays R1 and R2 and the capacitor arrays C1 and C2, further determining the zero pole frequency, the direct current gain and the high frequency gain of the equalizer, and further determining the compensation coefficient. And the signal input by the signal input end can obtain the optimal equalization effect according to the compensation coefficient.
The equalizer provided by the invention can be based on the through silicon capacitor, has stronger capacitive coupling effect, can improve the three-dimensional integration level of the equalizer and save the cost; secondly, the invention can flexibly configure the compensation coefficient of the equalizer by flexibly adjusting the numerical values of the injection resistor array and the capacitor array, so that the equalizer works in an optimal state, related parameter data in a circuit can be quickly acquired, the dependence of the equalizer on a production line in the prior art can be solved, the calculation can be simplified, the calculation accuracy can be improved, and the quality and the reliability of signal transmission can be improved; in addition, the invention can effectively inhibit the electromagnetic interference from a power supply and other circuits through a shielding ring structure formed by a rewiring layer and a silicon through hole based on a silicon substrate, so that the equalizer further has the performances of high integration level, high shielding and high reliability.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. "beneath," "under" and "beneath" a first feature includes the first feature being directly beneath and obliquely beneath the second feature, or simply indicating that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, numerous simple deductions or substitutions may be made without departing from the spirit of the invention, which shall be deemed to belong to the scope of the invention.
Claims (7)
1. A silicon-on capacitor-based configurable three-dimensional equalizer, comprising: the circuit comprises a switch control module SC1, a switch module S1, an injection resistor array R1, a silicon-on capacitor array C1, a switch control module SC2, a switch module S2, an injection resistor array R2 and a silicon-on capacitor array C2, wherein the switch module S1 and the switch module S2 are provided with a control end and a bidirectional port, and the switch control module SC1, the switch control module SC2, the injection resistor array R1, the injection resistor array R2, the silicon-on capacitor array C1 and the silicon-on capacitor array C2 are provided with bidirectional ports;
the injection resistor array R1, the through silicon capacitor array C1, the injection resistor array R2 and the through silicon capacitor array C2 are arranged in a silicon substrate;
a control end of the switch module S1 is connected to the switch control module SC1, a first bidirectional port of the switch module S1 is connected to a signal input end, and a second bidirectional port of the switch module S1 is connected to a first bidirectional port of the injection resistor array R1 and a first bidirectional port of the silicon-on capacitor array C1, respectively;
the second bidirectional port of the injection resistor array R1 and the second bidirectional port of the silicon-through capacitor array C1 are respectively connected with a signal output end;
a control end of the switch module S2 is connected to the switch control module SC2, a first bidirectional port of the switch module S2 is connected to the signal output end, and a second bidirectional port of the switch module S2 is connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the silicon-on capacitor array C2, respectively;
the second bidirectional port of the injection resistor array R2 and the second bidirectional port of the silicon-through capacitor array C2 are respectively connected with the ground wire.
2. The equalizer of claim 1, wherein the switch control module SC1 is disposed with a first multiplexer chip, the first multiplexer chip corresponds to an output end, the switch module S1 is disposed with a first switch chip, the first switch chip corresponds to a plurality of first injection resistance switch tubes and a first silicon-on capacitance switch tube;
the control end of the switch module S1 is connected to the switch control module SC1, and includes:
an output end corresponding to a first multiplexer chip of the switch control module SC1 is connected to a gate of a first injection resistance switching tube and a gate of a first silicon-on capacitance switching tube of the switch module S1 through a control end of the switch module S1;
the first bidirectional port of switch module S1 is connected with signal input end, includes:
the signal input end is connected with the source electrodes of a first injection resistance switching tube and a first silicon-on capacitance switching tube of the switch module S1 through a first bidirectional port of the switch module S1;
the second bidirectional port of the switch module S1 is respectively connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the silicon-through capacitor array C1, and includes:
a first injection resistance switching tube of the switching module S1 is connected with a first bidirectional port of the injection resistance array R1 through a second bidirectional port;
the first through silicon capacitor switch tube of the switch module S1 is connected with the first bidirectional port of the through silicon capacitor array C1 through the second bidirectional port.
3. The equalizer of claim 1, wherein the switch control module SC2 is disposed with a second multiplexer chip, the second multiplexer chip corresponds to the output terminal, the switch module S2 is disposed with a second switch chip, the second switch chip corresponds to a plurality of second injection resistance switch tubes and second silicon-on capacitance switch tubes;
the control end of the switch module S2 is connected to the switch control module SC2, and includes:
an output end corresponding to a second multiplexer chip of the switch control module SC2 is respectively connected with a second injection resistance switch tube of the switch module S2 and a grid electrode of a second through silicon capacitor switch tube through a control end of the switch module S2;
the first bidirectional port of the switch module S2 is connected to the signal output terminal, and includes:
the source electrodes of a second injection resistance switching tube and a second through-silicon capacitor switching tube in the switching module S2 are connected with the signal output end through a first bidirectional port;
the second bidirectional port of the switch module S2 is respectively connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the through silicon capacitor array C2, and includes:
a second injection resistance switch tube in the switch module S2 is connected to a first bidirectional port of the injection resistance array R2 through a second bidirectional port of the switch module S2;
the second through silicon capacitor switch tube in the switch module S2 is connected to the first bidirectional port of the through silicon capacitor array C2 through the second bidirectional port of the switch module S2.
4. The equalizer of claim 1, further comprising: the rewiring layer comprises a front rewiring layer and a back rewiring layer, wherein the rewiring layer is used for carrying out bidirectional port connection; the through silicon via penetrates through the silicon substrate, and the front rewiring layer and the back rewiring layer are respectively positioned on the front surface and the back surface of the silicon substrate;
the front rewiring layer is connected with the back rewiring layer through the silicon through hole;
the front rewiring layer is connected with the ground wire to form a shielding ring.
5. The equalizer of claim 4, wherein the first bidirectional port of the switch module S1 is connected to a signal input terminal, and the second bidirectional port of the switch module S1 is respectively connected to the first bidirectional port of the injection resistor array R1 and the first bidirectional port of the pass-silicon capacitor array C1, and the method comprises:
a first bidirectional port in the switch module S1 is connected with the signal input end through a front rewiring layer;
a second bidirectional port in the switch module S1 is connected to a first bidirectional port of the injection resistor array R1 and a first bidirectional port of the silicon-on capacitor array C1 through a front rewiring layer;
the second bidirectional port of the injection resistor array R1 is connected to a signal output terminal, and includes:
the second bidirectional port of the injection resistor array R1 is connected with the back rewiring layer through a through silicon via;
the second bidirectional port of the injection resistor array R1 is connected with the signal output end through a through silicon via;
the second bidirectional port of the through silicon capacitor array C1 is connected to a signal output terminal, and includes:
the second bidirectional port of the through silicon capacitor array C1 is connected with the back rewiring layer through a through silicon via;
and the second bidirectional port of the through silicon capacitor array C1 is connected with the signal output end through a through silicon via.
6. The equalizer of claim 4, wherein a control terminal of the switch module S2 is connected to the switch control module SC2, a first bidirectional port of the switch module S2 is connected to the signal output terminal, and a second bidirectional port of the switch module S2 is respectively connected to the first bidirectional port of the injection resistor array R2 and the first bidirectional port of the output terminal of the pass-through capacitor array C2, and the equalizer comprises:
a first bidirectional port in the switch module S2 is connected with the signal input end through a front rewiring layer;
a second bidirectional port in the switch module S2 is connected to a first bidirectional port of the injection resistor array R2 and a first bidirectional port of the silicon-on capacitor array C2 through a front rewiring layer;
the second bidirectional port of the injection resistor array R2 is connected to ground, and includes:
the second bidirectional port of the injection resistor array R2 is connected with the back rewiring layer through a silicon through hole;
the second bidirectional port of the injection resistor array R2 is connected with the ground wire through a through silicon via;
the second bidirectional port of the through silicon capacitor array C2 is connected to a ground line, and includes:
the second bidirectional port of the through silicon capacitor array C1 is connected with the back rewiring layer through a through silicon via;
and the second bidirectional port of the through silicon capacitor array C1 is connected with the ground wire through a through silicon via.
7. A three-dimensional equalizer parameter design method based on silicon-on capacitance configuration, which is applied to the equalizer of any one of claims 1 to 6, and is characterized in that the method comprises the following steps:
determining a transfer function according to the injection resistor array R1, the through silicon capacitor array C1, the injection resistor array R2 and the through silicon capacitor array C2 in the equalizer, wherein the transfer function is expressed as:
wherein, R is 1 Represents the total resistance of the injection resistor array R1, R 2 Represents the resistance of the injection resistor array R2, C 1 Representing the total capacitance of a through-silicon capacitor array C1, C 2 Representing the total capacitance of the through silicon capacitor array C2, wherein S represents the independent variable of the signal S domain;
determine the pole zero, expressed as:
wherein, the ω is z Represents the zero point, said ω p Representing a pole;
determining the dc gain and the high frequency gain, expressed as:
wherein, gain DC Representing the DC Gain, gain HF Represents the high frequency gain;
determining a compensation factor, expressed as:
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