CN113315422B - Commutation error compensation system and commutation error compensation method of brushless DC motor - Google Patents

Abstract

The disclosure provides a commutation error compensation system and a commutation error compensation method for a brushless direct current motor. The system comprises: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor; a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of the stator winding, a second input end of the target voltage acquisition circuit is electrically connected with a midpoint of the bus, and an input end of the direct current voltage acquisition circuit is electrically connected with an output end of the target voltage acquisition circuit; the input end of the commutation error type acquisition circuit is electrically connected with the output end of the direct-current voltage acquisition circuit; the commutation error type acquisition circuit is used for determining a type signal of the commutation error, and the type signal comprises a high level signal or a low level signal; and a general input/output interface of the digital processor is electrically connected with the output end of the commutation error type acquisition circuit to generate commutation error compensation quantity. The system realizes commutation error compensation by using a general input/output interface of a digital processor.

Description

Commutation error compensation system and commutation error compensation method of brushless DC motor

technical field

The present invention relates to the technical field of electric motors, in particular to a commutation error compensation system and a commutation error compensation method of a brushless DC motor.

Background technique

The brushless DC motor commutation method can use three-way Hall signals or encoders, and form six-way commutation signals through the combination of high and low levels. However, the installation of the position sensor not only increases the manufacturing process, it is easy to introduce commutation errors, but also reduces the cost of commutation. The reliability of the system, so there is a commutation method without position sensors. This position sensorless commutation technology has been widely used in the detection of the commutation position. During the specific implementation, the commutation error will be caused due to the phase shift of the filter and the delay of software and hardware.

In the prior art, based on the symmetry of the motor's signal such as the phase voltage and phase current of the motor, when the commutation error exists, the signal becomes asymmetrical. This asymmetry is described by mathematical variables and introduced into control as a feedback quantity The output control amount is used as the commutation error compensation amount, so as to realize the closed-loop compensation of the commutation error.

However, when realizing the closed-loop compensation of the above-mentioned commutation error, it is necessary to use an analog-to-digital converter (Analog-to-Digital Converter) to sample the voltage and current signals to construct the return value. Gyroscope, MSCMG), the active magnetic bearing control and the double closed-loop control of the motor run in a digital processor, occupying all ADC channels in the digital processor, so there is no redundant ADC channel for collecting the feedback amount of the commutation error control.

SUMMARY OF THE INVENTION

The present disclosure provides a commutation error compensation system and a commutation error compensation method of a brushless DC motor, which can realize the commutation error compensation by using a universal input and output interface of a digital processor.

In a first aspect, an embodiment of the present invention provides a commutation error compensation system for a brushless DC motor, including: a target voltage acquisition circuit, a DC voltage acquisition circuit, a commutation error type acquisition circuit, and a digital processor;

The first input terminal of the target voltage acquisition circuit is electrically connected to the virtual neutral point of the stator winding of the brushless DC motor, and the second input terminal of the target voltage acquisition circuit is connected to the busbar of the brushless DC motor. point electrical connection; the target voltage acquisition circuit is configured to determine a target voltage signal according to the voltage signal between the virtual neutral point and the bus midpoint;

The input terminal of the DC voltage acquisition circuit is electrically connected to the output terminal of the target voltage acquisition circuit; the DC voltage acquisition circuit is used for determining the first voltage corresponding to the positive voltage signal in the target voltage signal according to the target voltage signal. the DC voltage value and the second DC voltage value corresponding to the negative voltage signal;

The first input terminal of the commutation error type acquisition circuit is electrically connected to the first output terminal of the DC voltage acquisition circuit, and the second input terminal of the commutation error type acquisition circuit is electrically connected to the first output terminal of the DC voltage acquisition circuit. The two output terminals are electrically connected; the commutation error type acquisition circuit is configured to determine the type signal of the commutation error according to the absolute value of the second DC voltage value and the first DC voltage value; the type signal includes A high-level signal or a low-level signal, the type signal is used to indicate that the type of the commutation error is phase lead or phase lag;

The universal input and output interface of the digital processor is electrically connected to the output end of the commutation error type acquisition circuit; the digital processor is used for determining the commutation error according to the type signal, the initial compensation amount of the commutation error and the convergence factor. Phase error compensation amount.

Optionally, the digital processor includes: a flag bit information acquisition unit and a compensation unit;

The input end of the flag bit information acquisition unit is electrically connected to the universal input and output interface, and the flag bit information acquisition circuit is used to determine the corresponding flag bit information according to the type signal;

The input end of the compensation unit is electrically connected to the output end of the flag bit information acquisition unit, and the compensation unit is used for determining the commutation error compensation amount according to the following formula:

为第n次补偿时的换相误差补偿量，

为换相误差初始补偿量，k_i为第i次补偿时获取到的类型信号对应的标志位信息，λ为收敛因子，N为预设阈值。where n is the number of compensations,

is the commutation error compensation amount in the nth compensation,

is the initial compensation amount of the commutation error, ki is the flag bit information corresponding to the type signal obtained during the _ith compensation, λ is the convergence factor, and N is the preset threshold.

Optionally, the commutation error type acquisition circuit includes: a first inverter and a comparator;

The input terminal of the first inverter is electrically connected to the second input terminal of the commutation error type acquisition circuit, and the first inverter is used for acquiring the absolute value of the second DC voltage value;

The first input terminal of the comparator is electrically connected to the output terminal of the first inverter, and the second input terminal of the comparator is electrically connected to the first input terminal of the commutation error type acquisition circuit; the The comparator is configured to output a low level signal if the absolute value of the second DC voltage value is greater than the first DC voltage value; if the absolute value of the second DC voltage value is smaller than the first DC voltage value, output high level signal;

The compensation unit is further configured to determine the flag bit information corresponding to the type signal according to the following formula:

k=(S _c -0.5)×2;

Wherein, S _c is a low-level signal or a high-level signal, and k is the flag bit information corresponding to the type of signal.

Optionally, the DC voltage acquisition circuit includes: a positive voltage DC voltage acquisition circuit and a negative voltage DC voltage acquisition circuit;

The positive voltage DC voltage acquisition circuit includes a first half-wave rectifier and a first capacitor, the input end of the first half-wave rectifier is respectively connected with the first end of the first capacitor and the input end of the DC voltage acquisition circuit electrically connected, the output end of the first half-wave rectifier is respectively electrically connected to the second end of the first capacitor and the first output end of the DC voltage acquisition circuit; the first half-wave rectifier is used to obtain the a positive voltage signal in the target voltage signal, and the first capacitor is used to obtain a first DC voltage value corresponding to the positive voltage signal;

The negative voltage DC voltage acquisition circuit includes a second half-wave rectifier and a second capacitor, the input end of the second half-wave rectifier is respectively connected with the first end of the second capacitor and the input end of the DC voltage acquisition circuit electrically connected, the output end of the second half-wave rectifier is respectively electrically connected to the second end of the second capacitor and the second output end of the DC voltage obtaining circuit; the second half-wave rectifier is used to obtain the a negative voltage signal in the target voltage signal, and the second capacitor is used to obtain a second DC voltage value corresponding to the negative voltage signal.

Optionally, the target voltage obtaining circuit includes: a subtractor, a second inverter and a gate;

The first input terminal of the subtractor is electrically connected to the first input terminal of the target voltage acquisition circuit, and the second input terminal of the subtractor is electrically connected to the second input terminal of the target voltage acquisition circuit; the a subtractor is used to obtain the voltage signal between the virtual neutral point and the bus midpoint;

The input end of the second inverter is electrically connected to the output end of the subtractor, and the second inverter is used to obtain the inverted voltage signal of the voltage signal;

The first input end of the gate is electrically connected to the output end of the second inverter, the second input end of the gate is electrically connected to the output end of the subtractor, and the gate The controller is used for generating the target voltage signal according to the voltage signal, the inverted voltage signal and the gate signal.

In a second aspect, an embodiment of the present invention provides a commutation error compensation method for a brushless DC motor, which is suitable for a commutation error compensation system for a brushless DC motor. The commutation error compensation system includes: a target voltage acquisition circuit, DC voltage acquisition circuit, commutation error type acquisition circuit and digital processor;

The first input terminal of the target voltage acquisition circuit is electrically connected to the virtual neutral point of the stator winding of the brushless DC motor, and the second input terminal of the target voltage acquisition circuit is connected to the busbar of the brushless DC motor. point electrical connection; the input terminal of the DC voltage acquisition circuit is electrically connected to the output terminal of the target voltage acquisition circuit; the first input terminal of the commutation error type acquisition circuit is electrically connected to the first output of the DC voltage acquisition circuit The second input terminal of the commutation error type acquisition circuit is electrically connected to the second output terminal of the DC voltage acquisition circuit; the universal input and output interface of the digital processor is electrically connected to the type signal acquisition circuit. The output terminal is electrically connected;

The commutation error compensation method includes:

Determine the target voltage signal according to the voltage signal between the virtual neutral point in the brushless DC motor and the bus midpoint;

According to the target voltage signal, determine the first DC voltage value corresponding to the positive voltage signal and the second DC voltage value corresponding to the negative voltage signal in the target voltage signal;

A type signal of the commutation error is determined according to the absolute value of the second DC voltage value and the first DC voltage value, where the type signal includes a high-level signal or a low-level signal, and the type signal is used to represent The type of commutation error is phase lead or phase lag;

The commutation error compensation amount is determined according to the type signal, the commutation error initial compensation amount and the convergence factor.

Optionally, the determining the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor includes:

Determine the flag bit information corresponding to the type signal according to the type signal;

The commutation error compensation amount is determined according to the following formula:

为第n次补偿时的换相误差补偿量，

为换相误差初始补偿量，k_i为第i次补偿时获取到的类型信号对应的标志位信息，λ为收敛因子，N为预设阈值。where n is the number of compensations,

is the commutation error compensation amount in the nth compensation,

is the initial compensation amount of the commutation error, ki is the flag bit information corresponding to the type signal obtained during the _ith compensation, λ is the convergence factor, and N is the preset threshold.

Optionally, before the determining the phase error compensation amount, the method further includes:

The preset threshold is determined according to the following formula:

Among them, δ is the commutation error compensation increment when the error compensation converges to the steady state.

Optionally, the determining the type signal of the commutation error according to the absolute value of the second DC voltage value and the first DC voltage value includes:

If the absolute value of the second DC voltage value is greater than the first DC voltage value, a low level signal is output; if the absolute value of the second DC voltage value is less than the first DC voltage value, a high level signal is output Signal;

The determining the flag bit information corresponding to the type signal includes:

Determine the flag bit information corresponding to the type of signal according to the following formula:

k=(S _c -0.5)×2;

Wherein, S _c is a low-level signal or a high-level signal, and k is the flag bit information corresponding to the type of signal.

Optionally, the determining the target voltage signal according to the voltage signal between the virtual neutral point and the bus midpoint in the brushless DC motor includes:

obtaining an inverse voltage signal of the voltage signal;

The target voltage signal is acquired according to the voltage signal, the inversion signal and the gate signal, and the target voltage signal monotonically increases or decreases monotonically within a commutation period.

In the technical solution provided by the embodiment of the present invention, the first input terminal of the target voltage acquisition circuit is electrically connected to the virtual neutral point of the stator winding of the brushless DC motor, and the second input terminal of the target voltage acquisition circuit is connected to the brushless DC motor. The midpoint of the busbar is electrically connected, and the target voltage acquisition circuit can determine the target voltage signal according to the voltage signal between the virtual neutral point and the midpoint of the busbar; the input terminal of the DC voltage acquisition circuit is electrically connected to the output terminal of the target voltage acquisition circuit , the DC voltage acquisition circuit can determine, according to the target voltage signal, the first DC voltage value corresponding to the positive voltage signal and the second DC voltage value corresponding to the negative voltage signal in the target voltage signal; The first output terminal of the DC voltage acquisition circuit is electrically connected, the second input terminal of the commutation error type acquisition circuit is electrically connected with the second output terminal of the DC voltage acquisition circuit, and the commutation error type acquisition circuit can be based on the second DC voltage value. The absolute value and the first DC voltage value determine the type signal of the commutation error, wherein the type signal includes a high-level signal or a low-level signal, that is to say, the type signal is a digital signal, and the type used to represent the commutation error is Phase lead or phase lag; the digital processor is electrically connected to the output end of the commutation error type acquisition circuit through the universal input and output interface of the digital processor, and the digital processor can receive the digital signal, according to the type signal, the initial compensation amount of the commutation error and the convergence factor Determines the amount of commutation error compensation. Therefore, the technical solutions provided by the embodiments of the present invention can realize commutation error compensation through the universal input and output interface of the digital processor.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. In other words, on the premise of no creative labor, other drawings can also be obtained from these drawings.

FIG. 1 is a schematic structural diagram of a commutation error compensation system for a brushless DC motor according to an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a brushless DC motor according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a motor commutation point detection principle provided by an embodiment of the present invention;

FIG. 4 is a schematic waveform diagram of the voltage signal U _{MN ′} when there is no commutation error provided by an embodiment of the present invention;

FIG. 5 is a schematic waveform diagram of the voltage signal U _{MN ′} when the commutation error lags provided by an embodiment of the present invention;

FIG. 6 is a schematic waveform diagram of the voltage signal U _{MN ′} when the commutation error is advanced according to an embodiment of the present invention;

7 is a schematic diagram of a target voltage U _mult provided by an embodiment of the present invention;

8 is a schematic flowchart of a commutation error compensation method for a brushless DC motor according to an embodiment of the present invention;

9 is a schematic flowchart of another commutation error compensation method for a brushless DC motor provided by an embodiment of the present invention;

FIG. 10 is a schematic flowchart of yet another commutation error compensation method for a brushless DC motor according to an embodiment of the present invention;

FIG. 11 is a schematic flowchart of yet another commutation error compensation method for a brushless DC motor according to an embodiment of the present invention.

Detailed ways

In order to more clearly understand the above objects, features and advantages of the present invention, the solution of the present invention will be further described below. It should be noted that the embodiments of the present invention and the features in the embodiments may be combined with each other under the condition of no conflict.

Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein; obviously, the embodiments in the description are only a part of the embodiments of the present invention, and Not all examples.

FIG. 1 is a schematic structural diagram of a commutation error compensation system of a brushless DC motor provided by an embodiment of the present invention, and FIG. 2 is a schematic structural diagram of a brushless DC motor provided by an embodiment of the present invention, combined with FIG. 1 and FIG. 2 As shown, the commutation error compensation system 100 of the brushless DC motor includes a target voltage acquisition circuit 110 , a DC voltage acquisition circuit 120 , a commutation error type acquisition circuit 130 and a digital processor 140 .

The first input terminal of the target voltage acquisition circuit 110 is electrically connected to the virtual neutral point N′ of the stator winding of the brushless DC motor 210 , and the second input terminal of the target voltage acquisition circuit 110 is connected to the bus bar of the brushless DC motor 210 . Click M for electrical connection. The target voltage obtaining circuit 110 is configured to determine the target voltage signal U _mult according to the voltage signal U _MN' between the virtual neutral point N' and the bus midpoint M.

The input terminal of the DC voltage acquisition circuit 120 is electrically connected to the output terminal of the target voltage acquisition circuit 110, and the DC voltage acquisition circuit 120 is configured to determine the first DC corresponding to the positive voltage signal U _mult+ in the target voltage signal U _mult according to the target voltage signal U _mult The second DC voltage value U _{mult-_dc corresponding} to the voltage value U _{mult+_dc} and the negative voltage signal U mult-.

The first input terminal of the commutation error type acquisition circuit 130 is electrically connected to the first output terminal of the DC voltage acquisition circuit 120 , and the second input terminal of the commutation error type acquisition circuit 130 is electrically connected to the second output terminal of the DC voltage acquisition circuit 120 . connect. The commutation error type acquisition circuit 130 is configured to determine the commutation error type signal S _c according to the absolute value |U _{mult-_dc} | of the second DC voltage value U _mult -_dc and the first DC voltage value U _{mult+_dc} . The type signal S _c includes a high-level signal 1 or a low-level signal 0, and the type signal S _c is used to indicate that the type of the commutation error is phase lead or phase lag.

和收敛因子λ确定换相误差补偿量

The universal input and output interface G of the digital processor 140 is electrically connected to the output end of the commutation error type acquisition circuit 130, and the digital processor 140 is used for the initial compensation amount of the commutation error according to the type signal S _c and the commutation error type.

and the convergence factor λ to determine the amount of commutation error compensation

Illustratively, as shown in FIG. 2 , the brushless DC motor 210 includes an A-phase stator winding, a B-phase stator winding, and a C-phase stator winding.

The balance equation for the brushless DC motor 210 is as follows:

Among them, L is the phase inductance of the brushless DC motor, R is the phase resistance of the brushless DC motor, e _A is the opposite electromotive force of A, e _B is the opposite electromotive force of B, e _C is the opposite electromotive force of C, and N is the opposite electromotive force of the brushless DC motor. The neutral point of the stator winding, i _A is the A-phase current, i _B is the B-phase current, i _C is the C-phase current, and t is the time.

When BC is turned on, when phase A is suspended, i _A = 0, the phase voltage u _AN of phase A is equal to the opposite electromotive force e _A of A, when AC is turned on, phase B is suspended, at this time i _B = 0, phase B The phase voltage u _BN is equal to the B opposite electromotive force e _B . When AB is turned on and the C phase is suspended, i _C = 0, and the C phase phase voltage u _CN is equal to the C opposite electromotive force e _C .

此时换相点为相电压过零点延迟

FIG. 3 is a schematic diagram of a motor commutation point detection principle provided by an embodiment of the present invention. As shown in FIG. 3 , the phase voltage zero-crossing point is delayed by 30°, which is the commutation point. However, the delay of the filter and the delay of software and hardware in the commutation error compensation system 100 will cause the commutation error

At this time, the commutation point is the phase voltage zero-crossing delay

FIG. 4 is a schematic waveform diagram of the voltage signal U _MN' when there is no commutation error provided by an embodiment of the present invention, FIG. 5 is a schematic waveform diagram of the voltage signal U MN' provided by an embodiment of the present invention when the commutation error is delayed, and FIG. 6 is a schematic diagram of the waveform of the voltage signal U _MN' provided by the embodiment of the present invention A schematic diagram of the waveform of the voltage signal U _MN' when the commutation error is advanced according to the embodiment of the invention. As shown in Figure 4-Figure 6, when any signal in SA, SB, SC jumps, the voltage signal U _MN' is commutated, and when SA, SB, SC does not jump, U _MN' remains unchanged , the target voltage acquisition circuit 110 can invert the voltage signal U _MN′ when SA+SB+SC=1, thereby forming a target voltage signal U _mult that decreases monotonically within the commutation period, as shown in FIGS. 4-6 .

In other embodiments, the target voltage obtaining circuit 110 may also invert the voltage signal U _MN′ when SA+SB+SC=2, so as to form the target voltage signal U _mult monotonically increasing within the commutation period.

The DC voltage acquisition circuit 120 receives the target voltage signal U _mult , and divides the target voltage signal U _mult into a positive voltage signal U _mult+ and a negative voltage signal U _mult− , and decomposes the positive voltage signal U _mult+ according to the Fourier series. The DC part of the voltage signal U _mult+ , that is, the first DC voltage value U _{mult+_dc} is:

Among them, S ₊ is the area of the positive part of the target voltage signal U _mult .

其中，S-为目标电压信号U_mult负值部分的面积。Similarly, the DC part of the negative voltage signal U _mult- , that is, the second DC voltage value U _{mult-_dc} is:

Wherein, S- is the area of the negative part of the target voltage signal U _mult .

The commutation error type obtaining circuit 130 can receive the first DC voltage value U _{mult+_dc} and the second DC voltage value U _{mult-_dc} , and obtain the corresponding absolute value |U mult-_dc according to the second DC voltage value U _{mult -_dc} |, and the type of commutation error is determined according to the absolute value |U _{mult-_dc} | and the first DC voltage value U _{mult+_dc} .

则S₊＝S-，|U_mult-_{_dc}|＝U_{mult+_dc}，如图4所示。若

相位滞后，S₊<S-，U_{mult+_dc}<|U_mult-_{_dc}|，如图5所示，此时换相误差补偿量

应该满足小于0，换相误差类型获取电路130产生的类型信号S_c为低电平信号0。若

相位超前，S₊>S_-，U_{mult+_dc}>|U_{mult-_dc}|，如图6所示，此时换相误差补偿量

应该满足大于0，换相误差类型获取电路130产生的类型信号S_c为高电平信号1。Exemplarily, with reference to Figures 4-6, if there is no commutation error,

Then S ₊ =S-, |U _mult - _{_dc} |=U _{mult+_dc} , as shown in FIG. 4 . like

Phase lag, S ₊ < S-, U _{mult+_dc} <|U _mult - _{_dc} |, as shown in Figure 5, the compensation amount of commutation error at this time

Should be less than 0, the type signal S _c generated by the commutation error type acquisition circuit 130 is a low-level signal 0 . like

Phase lead, S ₊ >S _- , U _{mult+_dc} >|U _{mult-_dc} |, as shown in Figure 6, the compensation amount of commutation error at this time

Should be greater than 0, the type signal S _c generated by the commutation error type acquisition circuit 130 is a high-level signal 1 .

的方向，并根据换相误差初始补偿量

和收敛因子λ能够确定换相误差补偿量

的大小，由此可知数字处理器140可以根据类型信号S_c、换相误差初始补偿量

和收敛因子λ确定换相误差补偿量

的大小和方向，因此，换相点为相电压过零点延迟

从而实现换相误差的补偿。The type signal S _c is a digital signal, the general input and output interface G of the digital processor 140 can receive the type signal S _c , and the type of the commutation error can be obtained according to the type signal S _c , so that the compensation amount of the commutation error can be determined

direction, and the initial compensation amount according to the commutation error

and the convergence factor λ can determine the amount of commutation error compensation

, it can be known that the digital processor 140 can initially compensate the commutation error according to the type signal S _c , the commutation error

and the convergence factor λ to determine the amount of commutation error compensation

size and direction, therefore, the commutation point is the phase voltage zero-crossing delay

So as to realize the compensation of the commutation error.

In the technical solution provided by the embodiment of the present invention, the first input terminal of the target voltage acquisition circuit is electrically connected to the virtual neutral point of the stator winding of the brushless DC motor, and the second input terminal of the target voltage acquisition circuit is connected to the brushless DC motor. The midpoint of the busbar is electrically connected, and the target voltage acquisition circuit can determine the target voltage signal according to the voltage signal between the virtual neutral point and the midpoint of the busbar; the input terminal of the DC voltage acquisition circuit is electrically connected to the output terminal of the target voltage acquisition circuit , the DC voltage acquisition circuit can determine, according to the target voltage signal, the first DC voltage value corresponding to the positive voltage signal and the second DC voltage value corresponding to the negative voltage signal in the target voltage signal; The first output terminal of the DC voltage acquisition circuit is electrically connected, the second input terminal of the commutation error type acquisition circuit is electrically connected with the second output terminal of the DC voltage acquisition circuit, and the commutation error type acquisition circuit can be based on the second DC voltage value. The absolute value and the first DC voltage value determine the type signal of the commutation error, wherein the type signal includes a high-level signal or a low-level signal, that is to say, the type signal is a digital signal, and the type used to represent the commutation error is Phase lead or phase lag; the digital processor is electrically connected to the output end of the commutation error type acquisition circuit through the universal input and output interface of the digital processor, and the digital processor can receive the digital signal, according to the type signal, the initial compensation amount of the commutation error and the convergence factor Determines the amount of commutation error compensation. Therefore, the technical solutions provided by the embodiments of the present invention can realize commutation error compensation through the universal input and output interface of the digital processor.

Optionally, continuing to refer to FIG. 1 , the digital processor 140 includes: a flag bit information acquisition unit 141 and a compensation unit 142 .

The input terminal of the flag information obtaining unit 141 is electrically connected to the general-purpose input and output interface G, and the flag information obtaining circuit 141 is used to determine the corresponding flag information k according to the type signal S _c .

The input end 142 of the compensation unit is electrically connected to the output end of the flag bit information acquisition unit 141, and the compensation unit 142 is used to determine the commutation error compensation amount according to formula (3).

为第n次补偿时的换相误差补偿量，

为换相误差初始补偿量，k_i为第i次补偿时获取到的类型信号对应的标志位信息，λ为收敛因子，N为预设阈值。where n is the number of compensations,

is the commutation error compensation amount in the nth compensation,

is the initial compensation amount of the commutation error, ki is the flag bit information corresponding to the type signal obtained during the _ith compensation, λ is the convergence factor, and N is the preset threshold.

的符号。Specifically, the flag bit information obtaining unit 141 determines the corresponding flag bit information k according to the type signal S _c , if S _c is a low level signal 0, the corresponding flag bit information k is 1, if S _c is a high level signal 1 , the corresponding flag bit information k is -1, it can be seen that the flag bit information k can represent the commutation error compensation amount

symbol.

The working state of the compensation unit 142 is divided into two stages:

在此基础上，每一次补偿增加量

都衰减为上一次补偿增加量的λ倍，补偿增加量逐渐减小，有效减弱了超调和振荡。加之k确定了换相误差补偿量

是滞后补偿量还是超前补偿量，通过上述方式的不断累加，使得换相误差逐渐减小收敛。The first stage is, when n≤N, the first compensation amount after the compensation starts is the initial compensation amount of the commutation error

On this basis, each compensation increase

Both attenuate to λ times of the last compensation increase, and the compensation increase gradually decreases, effectively weakening the overshoot and oscillation. Plus k determines the commutation error compensation amount

Whether it is the lag compensation amount or the advance compensation amount, the commutation error is gradually reduced and converged through the continuous accumulation of the above methods.

不变，如此保证了换相误差补偿收敛至稳态时，仍具有闭环补偿能力，以应对电路漂移、器件老化导致的缓慢误差变化。In the second stage, in order to avoid the final attenuation of the error compensation increase to zero, when the compensation times satisfy n>N, the compensation increase is maintained with the increase of the compensation times

This ensures that when the commutation error compensation converges to a steady state, it still has a closed-loop compensation capability to cope with the slow error changes caused by circuit drift and device aging.

In the embodiment of the present invention, the compensation process of the commutation error is divided into two stages. The first stage is the commutation error compensation convergence stage, and the compensation increment gradually decreases, effectively weakening the overshoot and oscillation. The second stage is the commutation error compensation convergence stage. In the stable phase of the phase error compensation, the commutation error compensation amount is prevented from decaying to zero, so that the commutation error compensation system still has the closed-loop compensation capability, so that it can cope with the slow error changes caused by circuit drift and device aging.

Optionally, continue to refer to FIG. 1 , the commutation error type acquisition circuit 130 includes: a first inverter 131 and a comparator 132 .

The input terminal of the first inverter 131 is electrically connected to the second input terminal of the commutation error type acquisition circuit 130, and the first inverter 131 is used to acquire the absolute value of the second DC voltage value U _{mult-_dc} |U _{mult- _dc} |.

The first input terminal of the comparator 132 is electrically connected to the output terminal of the first inverter 131 , and the second input terminal of the comparator 132 is electrically connected to the first input terminal of the commutation error type acquiring circuit 130 . The comparator 132 is configured to output a low-level signal 0 if the absolute value |U _{mult-_dc} | of the second DC voltage value U _{mult-_dc} is greater than the first DC voltage value U _{mult+_dc} , and if the second DC voltage value U _mult The absolute value of _{-_dc} |U _{mult-_dc} | is smaller than the first DC voltage value U _{mult+_dc} , and a high-level signal 1 is output.

The compensation unit 142 is further configured to determine the flag bit information k corresponding to the type signal S _c according to formula (4):

k=(S _c -0.5)×2 (4)

Wherein, S _c is a low-level signal or a high-level signal, and k is the flag bit information corresponding to the type signal S _c .

即相位滞后时，比较器132输出的S_c为低电平信号0，补偿单元142根据公式(4)确定标志位信息k为-1，换相误差补偿量

从而能够降低换相误差。如图6所示，

即相位超前时，比较器132输出的S_c为高电平信号1，补偿单元142根据公式确定标志位信息k为1，换相误差补偿量

从而能够降低换相误差。Specifically, as shown in Figure 5,

That is, when the phase lags, the S _c output by the comparator 132 is a low-level signal 0, the compensation unit 142 determines that the flag bit information k is -1 according to formula (4), and the compensation amount of the commutation error is

Thus, the commutation error can be reduced. As shown in Figure 6,

That is, when the phase is advanced, the S _c output by the comparator 132 is a high-level signal 1, the compensation unit 142 determines that the flag bit information k is 1 according to the formula, and the compensation amount of the commutation error is 1.

Thus, the commutation error can be reduced.

In the embodiment of the present invention, the first inverter and the comparator can output a corresponding high-level signal or a low-level signal according to whether the commutation error leads or lags, that is, outputs a digital signal. Therefore, the digital processor can pass The universal input and output terminal directly obtains the digital signal, so as to determine whether the commutation error is leading or lagging in phase, without setting an analog-to-digital converter in the commutation error compensation system, saving hardware resources and software resources.

Optionally, continuing to refer to FIG. 1 , the DC voltage obtaining circuit 120 includes: a positive voltage DC voltage obtaining circuit 121 and a negative voltage DC voltage obtaining circuit 122 .

The positive voltage DC voltage acquisition circuit 121 includes a first half-wave rectifier 1211 and a first capacitor C1 , and the input terminal of the first half-wave rectifier 1211 is respectively connected to the first terminal of the first capacitor C1 and the input terminal of the DC voltage acquisition circuit 120 . Electrically connected, the output terminal of the first half-wave rectifier 1211 is electrically connected to the second terminal of the first capacitor C1 and the first output terminal of the DC voltage acquisition circuit 120 respectively. The first half-wave rectifier 1211 is used to obtain the positive voltage signal U _mult+ in the target voltage signal U _mult , and the first capacitor C1 is used to obtain the first DC voltage value U _{mult+_dc} corresponding to the positive voltage signal U _mult+ .

The negative voltage DC voltage acquisition circuit 122 includes a negative voltage half-wave rectifier circuit 1221 and a second capacitor C2. The input terminal of the second half-wave rectifier 1221 is electrically connected to the first terminal of the second capacitor C2 and the input terminal of the DC voltage acquisition circuit 120, respectively. connected, the output end of the second half-wave rectifier 1221 is electrically connected to the second end of the second capacitor C2 and the second output end of the DC voltage obtaining circuit 120 respectively. The second half-wave rectifier 1221 is used to obtain the negative voltage signal U _mult- in the target voltage signal U _mult , and the second capacitor C2 is used to obtain the second DC voltage value U _{mult-_dc} corresponding to the negative voltage signal.

Specifically, as shown in FIG. 1 , the first half-wave rectifier 1211 includes an operational amplifier, a resistor and two diodes, wherein the anode of one diode is connected to the first terminal of the resistor, the input terminal of the operational amplifier and the first half-wave respectively. The input terminal of the rectifier 1211 is electrically connected, the cathode of the diode is electrically connected to the second terminal of the resistor, the cathode of the other diode and the output terminal of the first half-wave rectifier 1211, and the anode of the other diode is electrically connected to the output terminal of the operational amplifier. connect. The target voltage signal U _mult is rectified by the first half-wave rectifier 1211 to generate a positive voltage signal U _mult+ . The first half-wave rectifier 1211 is a precision half-wave rectifier. Thanks to the high gain characteristics of the op amp, even if there is a slight voltage change at the input end of the op amp, the diode will be turned on, forming a feedback loop, avoiding the need for Diode turn-on threshold limit. A first capacitor C1 is added to the feedback loop of the operational amplifier. When the two diodes are turned off, the first capacitor C1 is charged. When the two diodes are turned on, the first capacitor C1 is discharged to the resistor, realizing the filtering of the positive voltage signal U _mult+ smoothing function, so the first DC voltage value U _{mult+_dc} can be obtained.

The second half-wave rectifier 1221 includes an operational amplifier, a resistor and two diodes, wherein the cathode of one diode is electrically connected to the first terminal of the resistor, the input terminal of the operational amplifier and the input terminal of the second half-wave rectifier 1221, respectively. The anode of the diode is electrically connected to the second end of the resistor, the anode of the other diode and the output end of the second half-wave rectifier 1221 respectively, and the cathode of the other diode is electrically connected to the output end of the operational amplifier. The target voltage signal U _mult is rectified by the second half-wave rectifier 1221 to generate a negative voltage signal U _mult- . The second half-wave rectifier 1221 is a precision half-wave rectifier. Thanks to the high gain characteristics of the operational amplifier, even if there is a slight voltage change at the input end of the operational amplifier, the diode will be turned on, forming a feedback loop, avoiding the need for Diode turn-on threshold limit. A second capacitor C2 is added to the feedback loop of the operational amplifier. When the two diodes are turned off, the second capacitor C2 is charged. When the two diodes are turned on, the second capacitor C2 discharges to the resistor, realizing the negative voltage signal U _mult- Filtering and smoothing function, so the second DC voltage value U _{mult-_dc} can be obtained.

In the embodiment of the present invention, the target voltage signal is rectified by the half-wave rectifier, thereby obtaining the positive voltage signal and the negative voltage signal, and the positive voltage signal and the negative voltage signal are smoothed and filtered by the capacitor, so as to obtain the corresponding voltage signal of the positive voltage signal. The first DC voltage value and the second DC voltage value corresponding to the negative voltage signal, in this way, the first DC voltage value and the second DC voltage value can be obtained through the hardware circuit, which can save the commutation error compensation system of the brushless DC motor 100 interrupt resources and computing resources.

Optionally, continue to refer to FIG. 1 , the target voltage obtaining circuit 110 includes: a subtractor 111 , a second inverter 112 and a gate 113 .

The first input terminal of the subtractor 111 is electrically connected to the first input terminal of the target voltage acquisition circuit 110 , and the second input terminal of the subtractor 111 is electrically connected to the second input terminal of the target voltage acquisition circuit 110 . The subtractor 111 is used to obtain the voltage signal U _MN' between the virtual neutral point and the bus midpoint.

The input end of the second inverter 112 is electrically connected to the output end of the subtractor 111, and the second inverter 112 is used to obtain the inverted voltage signal -U MN _' of the voltage signal U _MN' ;

The first input terminal of the gate 113 is electrically connected to the output terminal of the second inverter 112, and the second input terminal of the gate 113 is electrically connected to the output terminal of the subtractor 111 respectively. The signal U _MN' , the inverted voltage signal -U _MN' and the strobe signal S generate the target voltage signal U _mult .

Exemplarily, FIG. 7 is a schematic diagram of a target voltage U _mult provided by an embodiment of the present invention. As shown in FIG. 7 , when the gate signal S is at a high level, the gate 113 gates the second inverter 112. The output terminal, namely the gate -U _MN' , when the gate signal S is at a low level, the gate 113 gates the output terminal of the subtractor 111, that is, the gate U _MN' , thereby generating the target voltage signal U _mult , the target voltage The signal U _mult decreases monotonically during the commutation period. In other embodiments, when the gate signal S is at a high level, U _MN' is gated, and when the gate signal S is at a low level, -UMN _' is gated, thereby generating the target voltage signal U _mult , the target voltage signal U _mult monotonically increases over the commutation period.

In the embodiment of the present invention, the voltage signal between the virtual neutral point and the midpoint of the bus is obtained through the subtractor, the inverted voltage signal of the voltage signal is obtained through the second inverter, and the target voltage signal is obtained through the gate, so , the target voltage signal can be obtained through the hardware circuit, which can save the interruption resources and computing resources of the commutation error compensation system 100 of the brushless DC motor.

The embodiment of the present invention also provides a commutation error compensation method for a brushless DC motor, which is applied to the commutation error compensation system 100 of the brushless DC motor provided by the above embodiment, and includes the commutation error compensation 100 of the brushless DC motor. beneficial effect.

FIG. 8 is a schematic flowchart of a commutation error compensation method for a brushless DC motor according to an embodiment of the present invention. The commutation error compensation method is applicable to the commutation error compensation system 100 of a brushless DC motor as shown in FIG. 1 . . As shown in Figure 8, the specific steps of the commutation error compensation method include:

S101: Determine a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless DC motor.

Specifically, the target voltage acquisition circuit 110 can acquire the voltage signal U _MN' between the virtual neutral point N' and the bus midpoint M, and determine the target voltage signal U _mult according to the voltage signal U _MN' .

S102: Determine, according to the target voltage signal, a first DC voltage value corresponding to a positive voltage signal and a second DC voltage value corresponding to a negative voltage signal in the target voltage signal.

Specifically, the DC voltage acquisition circuit 120 can receive the target voltage signal U _mult output by the target voltage acquisition circuit 110 , and determine the positive voltage signal U _mult+ and the negative voltage signal U in the target voltage signal U _mult according to the received target voltage signal U _{mult mult-} , and respectively determine the first DC voltage value U _{mult+_dc} corresponding to the positive voltage signal U _mult+ and the second DC voltage value U _{mult-_dc corresponding} to the negative voltage signal U mult-.

S103: Determine a type signal of a commutation error according to the absolute value of the second DC voltage value and the first DC voltage value.

The type signal includes a high-level signal or a low-level signal, and the type signal is used to indicate that the type of the commutation error is phase lead or phase lag.

Specifically, the commutation error type acquisition circuit 130 can receive the second DC voltage value U _{mult-_dc} output by the DC voltage acquisition circuit 120, and determine its absolute value |U _{mult-_dc} |. The commutation error type acquisition circuit 130 can also receive the first DC voltage value U _{mult+_dc} output by the DC voltage acquisition circuit 120, and according to the absolute value of the second DC voltage value U _{mult-_dc} |U _{mult-_dc} | and the first DC voltage value U mult+_dc The DC voltage value U _{mult+_dc} determines that the type of commutation error is phase lead or phase lag, and outputs a type signal S _c representing the commutation error, where the type signal S _c is a digital signal, that is, a high-level signal 1 Or low level signal 0.

S104: Determine the commutation error compensation amount according to the type signal, the commutation error initial compensation amount, and the convergence factor.

的方向，还能够根据换相误差初始补偿量

和收敛因子λ能够确定换相误差补偿量

的大小。Specifically, the digital processor 140 can directly obtain the type signal S _c through the general input and output interface G. Since the type signal S _c is a digital signal, an ADC is not required. The digital processor 140 can determine the commutation error compensation amount according to the type signal S _c

direction, and the initial compensation amount can also be based on the commutation error

and the convergence factor λ can determine the amount of commutation error compensation

the size of.

In the technical solution provided by the embodiment of the present invention, the target voltage signal is determined according to the voltage signal between the virtual neutral point and the bus midpoint; according to the target voltage signal, the first DC voltage value corresponding to the positive voltage signal in the target voltage signal is determined The second DC voltage value corresponding to the negative voltage signal; according to the absolute value of the second DC voltage value and the first DC voltage value, the type signal of the commutation error is determined, wherein the type signal includes a high-level signal or a low-level signal , that is to say, the type signal is a digital signal, which is used to indicate that the type of commutation error is phase lead or phase lag; the commutation error compensation amount is determined according to the type signal, the initial compensation amount of the commutation error and the convergence factor. The type signal can be directly obtained through the input and output interface, and the phase error compensation amount can be determined according to the type signal, the initial compensation amount and the convergence factor, so there is no need to set the ADC, and the commutation error compensation can be realized through the general input and output interface of the digital processor.

FIG. 9 is a schematic flowchart of another commutation error compensation method for a brushless DC motor provided by an embodiment of the present invention, and FIG. 9 is a possible implementation manner of executing S104 on the basis of the embodiment shown in FIG. 8 A detailed description, including:

S1041. Determine the flag bit information corresponding to the type signal according to the type signal.

的符号，即换相误差补偿量

的方向。Specifically, as shown in FIG. 1 , the digital processor 140 includes a flag bit information acquisition unit 141 and a compensation unit 142. The flag bit information acquisition unit 141 can determine the flag bit information k corresponding to the type signal S _c according to the type signal S _c , The flag bit information k is 1 or -1, and the flag bit information k is used to indicate the amount of commutation error compensation

The sign of , that is, the amount of commutation error compensation

direction.

S1043: Determine the commutation error compensation amount according to formula (3).

和收敛因子λ代入公式(3)可以确定相误差补偿量

的大小。Specifically, the compensation unit 142 uses the preset phase error initial compensation amount

and the convergence factor λ can be substituted into formula (3) to determine the phase error compensation amount

the size of.

According to formula (3), the process of commutation error compensation is divided into two stages:

在此基础上，每一次补偿增加量

都衰减为上一次补偿增加量的λ倍，补偿增加量逐渐减小，有效减弱了超调和振荡。加之k确定了换相误差补偿量

是滞后补偿量还是超前补偿量，通过上述方式的不断累加，使得换相误差逐渐减小收敛。The first stage is, when n≤N, the first compensation amount after the compensation starts is the initial compensation amount of the commutation error

On this basis, each compensation increase

Both attenuate to λ times of the last compensation increase, and the compensation increase gradually decreases, effectively weakening the overshoot and oscillation. Plus k determines the commutation error compensation amount

Whether it is the lag compensation amount or the advance compensation amount, the commutation error is gradually reduced and converged through the continuous accumulation of the above methods.

不变，如此保证了换相误差补偿收敛至稳态时，仍具有闭环补偿能力，以应对电路漂移、器件老化导致的缓慢误差变化。In the second stage, in order to avoid the final attenuation of the error compensation increase to zero, when the compensation times satisfy n>N, the compensation increase is maintained with the increase of the compensation times

This ensures that when the commutation error compensation converges to a steady state, it still has a closed-loop compensation capability to cope with the slow error changes caused by circuit drift and device aging.

In the embodiment of the present invention, the compensation process of the commutation error is divided into two stages. The first stage is the commutation error compensation convergence stage, and the compensation increment gradually decreases, effectively weakening the overshoot and oscillation. The second stage is the commutation error compensation convergence stage. In the stable phase of the phase error compensation, the commutation error compensation amount is prevented from decaying to zero, so that the commutation error compensation system still has the closed-loop compensation capability, so that it can cope with the slow error changes caused by circuit drift and device aging.

Optionally, continue to refer to FIG. 9, before executing S1043, further include:

S1042, determine the preset threshold according to formula (5):

Among them, δ is the commutation error compensation increment when the error compensation converges to the steady state.

和收敛因子λ代入公式(5)，可确定预设阈值N，当补偿次数达到预设阈值N时，表示换相误差补偿进入稳态。δ越小，换相误差补偿收敛的过程越慢，稳态的周期性振荡越微弱，换相误差补偿的精度越高。Specifically, the compensation unit 142 uses the preset δ, the initial compensation amount of the phase error

and the convergence factor λ are substituted into formula (5), the preset threshold N can be determined, and when the number of compensations reaches the preset threshold N, it means that the commutation error compensation enters a steady state. The smaller the δ, the slower the commutation error compensation convergence process, the weaker the steady-state periodic oscillation, and the higher the commutation error compensation accuracy.

FIG. 10 is a schematic flowchart of another commutation error compensation method for a brushless DC motor according to an embodiment of the present invention. FIG. 10 is a possible implementation of S103 based on the embodiment shown in FIG. 9 . Specific description, including:

S103', if the absolute value of the second DC voltage value is greater than the first DC voltage value, output a low-level signal; if the absolute value of the second DC voltage value is smaller than the first DC voltage value, output high level signal.

Specifically, as shown in FIG. 1 , the commutation error type acquisition circuit 130 includes a second inverter 131 and a comparator 132 , and the second inverter 131 can receive the second DC voltage value U _mult output by the DC voltage acquisition circuit 120 . _{-_dc} and determine its absolute value |U _{mult-_dc} |, the comparator 132 can receive the absolute value |U _mult -_dc| of the second DC voltage value U _mult- _dc and the first DC voltage value U _{mult+_dc} , and When the absolute value |U _{mult-_dc} | of the second DC voltage value U _{mult-_dc} is greater than the first DC voltage value U _{mult+_dc} , a low-level signal 0 is output, and when the absolute value of the second DC voltage value U _{mult-_dc} When the value |U _{mult-_dc} | is smaller than the first DC voltage value U _{mult+_dc} , a high-level signal 1 is output.

A specific description of a possible implementation when S1041 is executed, as shown in Figure 10:

S1041', determine the flag bit information corresponding to the type signal according to formula (4).

即相位滞后时，S_c为低电平信号0，根据公式(4)确定标志位信息k为-1，换相误差补偿量

从而能够降低换相误差。如图6所示，

即相位超前时，S_c为高电平信号1，根据公式(4)确定标志位信息k为1，换相误差补偿量

从而能够降低换相误差。Exemplarily, as shown in Figure 5,

That is, when the phase lags, S _c is a low-level signal 0, and the flag bit information k is determined to be -1 according to formula (4), and the commutation error compensation amount

Thus, the commutation error can be reduced. As shown in Figure 6,

That is, when the phase is advanced, S _c is a high-level signal 1, and the flag bit information k is determined to be 1 according to formula (4), and the commutation error compensation amount

Thus, the commutation error can be reduced.

In the embodiment of the present invention, the sign of the commutation error compensation amount can be obtained according to the type signal, so that the commutation error can be effectively reduced and the commutation accuracy can be improved under the action of the phase error compensation amount.

FIG. 11 is a schematic flowchart of another commutation error compensation method for a brushless DC motor according to an embodiment of the present invention, and FIG. 11 is a possible implementation of S101 based on the embodiment shown in FIG. 8 . A detailed description, including:

S1011, acquiring an inverse voltage signal of the voltage signal.

Specifically, the second inverter 112 receives the voltage signal U _MN' output by the subtractor 111, and obtains the corresponding inverted voltage signal -U _{MN' according to the voltage signal U MN' .}

S1012: Acquire the target voltage signal according to the voltage signal, the inversion signal and the gating signal.

The target voltage signal monotonically increases or decreases monotonically within the commutation period.

Exemplarily, as shown in FIG. 7 , when the gate signal S is at a high level, the gate 113 gates the output end of the second inverter 112 , that is, gate -U _MN' , and the gate signal S is at a low level. Normally, the gate 113 gates the output end of the subtractor 111 , that is, gates U _MN′ , so that the target voltage signal U _mult that monotonically decreases in the commutation period can be obtained.

In other embodiments, U _{MN' may} also be gated when the gate signal S is at a high level, and -UMN' may be gated when the gate signal S is at a low level, so that the monotonically increasing phase within the commutation period can be obtained. The target voltage signal U _mult .

Based on the voltage signal U _MN' , no matter the commutation is accurate, the phase leads or the phase lags, the absolute values of the DC component of the positive voltage electrical signal and the DC component of the negative voltage electrical signal of the voltage signal U _MN' in one cycle are equal. In this embodiment of the present invention, the target voltage signal is acquired according to the voltage signal, and the target voltage signal can break this rule, so that when the phase leads or the phase lags, the absolute difference between the DC component of the positive voltage electrical signal and the DC component of the negative voltage electrical signal in one cycle is The values are not equal, so that the commutation error can be accurately reflected.

It should be noted that, in this document, relational terms such as "first" and "second" etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these There is no such actual relationship or sequence between entities or operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

The above descriptions are only specific embodiments of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A commutation error compensation system for a brushless dc motor, comprising: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;

a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the target voltage obtaining circuit is used for determining a target voltage signal according to a voltage signal between the virtual neutral point and the bus midpoint;

the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; the direct-current voltage acquisition circuit is used for determining a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal;

a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; the commutation error type obtaining circuit is used for determining a type signal of a commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value; the type signal comprises a high level signal or a low level signal and is used for indicating the type of the commutation error as phase lead or phase lag;

a general input/output interface of the digital processor is electrically connected with an output end of the commutation error type acquisition circuit; the digital processor is used for determining commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor;

the digital processor includes: a flag bit information acquisition unit and a compensation unit;

the input end of the zone bit information acquisition unit is electrically connected with the general input/output interface, and the zone bit information acquisition circuit is used for determining corresponding zone bit information according to the type signal;

the input end of the compensation unit is electrically connected with the output end of the zone bit information acquisition unit, and the compensation unit is used for determining the commutation error compensation quantity according to the following formula:

wherein n is the number of compensation times,

for the commutation error compensation amount at the nth compensation,

for initial compensation of commutation errors, k_iAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.

2. The commutation error compensation system of claim 1, wherein the commutation error type obtaining circuit comprises: a first inverter and a comparator;

the input end of the first inverter is electrically connected with the second input end of the commutation error type acquisition circuit, and the first inverter is used for acquiring the absolute value of the second direct-current voltage value;

a first input end of the comparator is electrically connected with an output end of the first phase inverter, and a second input end of the comparator is electrically connected with a first input end of the commutation error type obtaining circuit; the comparator is used for outputting a low level signal if the absolute value of the second direct current voltage value is greater than the first direct current voltage value; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;

the compensation unit is further configured to determine flag bit information corresponding to the type signal according to the following formula:

k＝(S_c-0.5)×2；

wherein S is_cAnd k is a low level signal or a high level signal, and is flag bit information corresponding to the type signal.

3. The commutation error compensation system of claim 1 or 2, wherein the dc voltage acquisition circuit comprises: a positive voltage direct current voltage acquisition circuit and a negative voltage direct current voltage acquisition circuit;

the positive voltage direct current voltage acquisition circuit comprises a first half-wave rectifier and a first capacitor, wherein the input end of the first half-wave rectifier is electrically connected with the first end of the first capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the first half-wave rectifier is electrically connected with the second end of the first capacitor and the first output end of the direct current voltage acquisition circuit respectively; the first half-wave rectifier is used for acquiring a positive voltage signal in the target voltage signal, and the first capacitor is used for acquiring a first direct-current voltage value corresponding to the positive voltage signal;

the negative voltage direct current voltage acquisition circuit comprises a second half-wave rectifier and a second capacitor, wherein the input end of the second half-wave rectifier is electrically connected with the first end of the second capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the second half-wave rectifier is electrically connected with the second end of the second capacitor and the second output end of the direct current voltage acquisition circuit respectively; the second half-wave rectifier is used for acquiring a negative voltage signal in the target voltage signal, and the second capacitor is used for acquiring a second direct-current voltage value corresponding to the negative voltage signal.

4. The commutation error compensation system of claim 1 or 2, wherein the target voltage acquisition circuit comprises: the subtractor, the second inverter and the gate;

a first input end of the subtractor is electrically connected with a first input end of the target voltage acquisition circuit, and a second input end of the subtractor is electrically connected with a second input end of the target voltage acquisition circuit; the subtracter is used for acquiring a voltage signal between the virtual neutral point and the bus midpoint;

the input end of the second inverter is electrically connected with the output end of the subtracter, and the second inverter is used for acquiring an inverted voltage signal of the voltage signal;

the first input end of the gate is electrically connected with the output end of the second inverter, the second input end of the gate is electrically connected with the output end of the subtracter respectively, and the gate is used for generating the target voltage signal according to the voltage signal, the inverted voltage signal and the gate signal.

5. A commutation error compensation method for a brushless DC motor, the commutation error compensation method being applicable to a commutation error compensation system for a brushless DC motor, the commutation error compensation system comprising: the device comprises a target voltage acquisition circuit, a direct-current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;

a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; a general input/output interface of the digital processor is electrically connected with an output end of the commutation error type acquisition circuit;

the commutation error compensation method comprises the following steps:

determining a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless direct current motor;

according to the target voltage signal, determining a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal;

determining a type signal of the commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, and the type signal is used for indicating that the type of the commutation error is phase lead or phase lag;

determining commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor:

the determining the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor specifically includes:

determining flag bit information corresponding to the type signal according to the type signal;

determining the commutation error compensation amount according to the following formula:

wherein n is the number of compensation times,

for the commutation error compensation amount at the nth compensation,

for initial compensation of commutation errors, k_iAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.

6. The method of claim 5, wherein prior to determining the commutation error compensation amount, further comprising:

determining the preset threshold value according to the following formula:

where δ is the commutation error compensation increment at which the error compensation converges to a steady state.

7. The method of claim 5, wherein determining the type signal of commutation error based on the absolute value of the second DC voltage value and the first DC voltage value comprises:

if the absolute value of the second direct current voltage value is larger than the first direct current voltage value, outputting a low level signal; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;

the determining flag bit information corresponding to the type signal includes:

determining flag bit information corresponding to the type signal according to the following formula:

k＝(S_c-0.5)×2；

wherein S is_cAnd k is a low level signal or a high level signal, and k is flag bit information corresponding to the type signal.

8. The method according to any one of claims 5-7, wherein determining a target voltage signal from a voltage signal between a virtual neutral point and a bus midpoint in the brushless DC motor comprises:

acquiring an inverted voltage signal of the voltage signal;

and acquiring the target voltage signal according to the voltage signal, the inverted voltage signal and the gating signal, wherein the target voltage signal is monotonically increased or monotonically decreased in a commutation period.

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