CN113315422B - Commutation error compensation system and commutation error compensation method for brushless direct current motor - Google Patents
Commutation error compensation system and commutation error compensation method for brushless direct current motor Download PDFInfo
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- CN113315422B CN113315422B CN202110578352.5A CN202110578352A CN113315422B CN 113315422 B CN113315422 B CN 113315422B CN 202110578352 A CN202110578352 A CN 202110578352A CN 113315422 B CN113315422 B CN 113315422B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/12—Monitoring commutation; Providing indication of commutation failure
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P6/00—Arrangements for controlling synchronous motors or other dynamo-electric motors using electronic commutation dependent on the rotor position; Electronic commutators therefor
- H02P6/14—Electronic commutators
- H02P6/16—Circuit arrangements for detecting position
- H02P6/18—Circuit arrangements for detecting position without separate position detecting elements
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Abstract
The disclosure provides a commutation error compensation system and a commutation error compensation method for a brushless direct current motor. The system comprises: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor; a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of the stator winding, a second input end of the target voltage acquisition circuit is electrically connected with a midpoint of the bus, and an input end of the direct current voltage acquisition circuit is electrically connected with an output end of the target voltage acquisition circuit; the input end of the commutation error type acquisition circuit is electrically connected with the output end of the direct-current voltage acquisition circuit; the commutation error type acquisition circuit is used for determining a type signal of the commutation error, and the type signal comprises a high level signal or a low level signal; and a general input/output interface of the digital processor is electrically connected with the output end of the commutation error type acquisition circuit to generate commutation error compensation quantity. The system realizes commutation error compensation by using a general input/output interface of a digital processor.
Description
Technical Field
The invention belongs to the technical field of motors, and particularly relates to a commutation error compensation system and a commutation error compensation method of a brushless direct current motor.
Background
The brushless direct current motor commutation method can adopt three paths of Hall signals or encoders, six paths of commutation signals are formed through level high-low combination, but the installation of the position sensor not only increases the manufacturing process, is easy to introduce commutation errors, but also reduces the reliability of the system, and therefore, the commutation method without the position sensor appears. The position-sensorless commutation technique has been widely used for detecting commutation position, and commutation errors can be caused by phase shift of a filter and software and hardware delays during specific implementation.
In the prior art, based on the symmetry of signals of a motor such as phase voltage and phase current of the motor, when a commutation error exists, the signals are asymmetric, the asymmetry is described by mathematical variables and is introduced into a controller as a feedback quantity, and an output control quantity is used as a commutation error compensation quantity, so that closed-loop compensation of the commutation error is realized.
However, when the closed-loop compensation of the commutation error is implemented, an Analog-to-Digital Converter (Analog-to-Digital Converter) is required to sample voltage and current signals to construct a return quantity, and for a highly integrated magnetic levitation Control Moment gyro (MSCMG), the active magnetic levitation bearing Control and the double closed-loop Control of the motor are operated in one Digital processor, and all ADC channels in the Digital processor are occupied, so that no extra ADC channels are used for collecting the feedback quantity of the commutation error Control.
Disclosure of Invention
The present disclosure provides a commutation error compensation system and a commutation error compensation method for a brushless dc motor, which can implement commutation error compensation by using a general input/output interface of a digital processor.
In a first aspect, an embodiment of the present invention provides a commutation error compensation system for a brushless dc motor, including: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;
a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the target voltage obtaining circuit is used for determining a target voltage signal according to a voltage signal between the virtual neutral point and the bus midpoint;
the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; the direct-current voltage acquisition circuit is used for determining a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal;
a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; the commutation error type obtaining circuit is used for determining a type signal of a commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value; the type signal comprises a high level signal or a low level signal and is used for indicating the type of the commutation error as phase lead or phase lag;
a general input/output interface of the digital processor is electrically connected with the output end of the commutation error type acquisition circuit; and the digital processor is used for determining a commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor.
Optionally, the digital processor comprises: a flag bit information acquisition unit and a compensation unit;
the input end of the zone bit information acquisition unit is electrically connected with the general input/output interface, and the zone bit information acquisition circuit is used for determining corresponding zone bit information according to the type signal;
the input end of the compensation unit is electrically connected with the output end of the zone bit information acquisition unit, and the compensation unit is used for determining the commutation error compensation quantity according to the following formula:
wherein n is the number of compensation times,
for the commutation error compensation amount at the nth compensation,
for initial compensation of commutation errors, kiAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.
Optionally, the commutation error type obtaining circuit includes: a first inverter and a comparator;
the input end of the first inverter is electrically connected with the second input end of the commutation error type acquisition circuit, and the first inverter is used for acquiring the absolute value of the second direct-current voltage value;
a first input end of the comparator is electrically connected with an output end of the first phase inverter, and a second input end of the comparator is electrically connected with a first input end of the commutation error type obtaining circuit; the comparator is used for outputting a low level signal if the absolute value of the second direct current voltage value is greater than the first direct current voltage value; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;
the compensation unit is further configured to determine flag bit information corresponding to the type signal according to the following formula:
k＝(Sc-0.5)×2；
wherein S iscAnd k is a low level signal or a high level signal, and k is flag bit information corresponding to the type signal.
Optionally, the dc voltage obtaining circuit includes: a positive voltage direct current voltage acquisition circuit and a negative voltage direct current voltage acquisition circuit;
the positive voltage direct current voltage acquisition circuit comprises a first half-wave rectifier and a first capacitor, wherein the input end of the first half-wave rectifier is electrically connected with the first end of the first capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the first half-wave rectifier is electrically connected with the second end of the first capacitor and the first output end of the direct current voltage acquisition circuit respectively; the first half-wave rectifier is used for acquiring a positive voltage signal in the target voltage signal, and the first capacitor is used for acquiring a first direct-current voltage value corresponding to the positive voltage signal;
the negative voltage direct current voltage acquisition circuit comprises a second half-wave rectifier and a second capacitor, wherein the input end of the second half-wave rectifier is electrically connected with the first end of the second capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the second half-wave rectifier is electrically connected with the second end of the second capacitor and the second output end of the direct current voltage acquisition circuit respectively; the second half-wave rectifier is used for acquiring a negative voltage signal in the target voltage signal, and the second capacitor is used for acquiring a second direct-current voltage value corresponding to the negative voltage signal.
Optionally, the target voltage obtaining circuit includes: the subtractor, the second inverter and the gate;
the first input end of the subtracter is electrically connected with the first input end of the target voltage acquisition circuit, and the second input end of the subtracter is electrically connected with the second input end of the target voltage acquisition circuit; the subtracter is used for acquiring a voltage signal between the virtual neutral point and the bus midpoint;
the input end of the second inverter is electrically connected with the output end of the subtracter, and the second inverter is used for acquiring an inverted voltage signal of the voltage signal;
the first input end of the gate is electrically connected with the output end of the second inverter, the second input end of the gate is electrically connected with the output end of the subtracter respectively, and the gate is used for generating the target voltage signal according to the voltage signal, the inverted voltage signal and the gate signal.
In a second aspect, an embodiment of the present invention provides a commutation error compensation method for a brushless dc motor, which is applied to a commutation error compensation system for a brushless dc motor, where the commutation error compensation system includes: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;
a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; a general input/output interface of the digital processor is electrically connected with the output end of the type signal acquisition circuit;
the commutation error compensation method comprises the following steps:
determining a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless direct current motor;
determining a first direct current voltage value corresponding to a positive voltage signal and a second direct current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal;
determining a type signal of the commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, and the type signal is used for indicating that the type of the commutation error is phase lead or phase lag;
and determining the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor.
Optionally, the determining a commutation error compensation amount according to the type signal, the commutation error initial compensation amount, and the convergence factor includes:
determining flag bit information corresponding to the type signal according to the type signal;
determining the commutation error compensation quantity according to the following formula:
wherein n is the number of compensation times,
for the commutation error compensation amount at the nth compensation,
for initial compensation of commutation errors, kiAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.
Optionally, before determining the phase error compensation amount, the method further includes:
determining the preset threshold value according to the following formula:
where δ is the commutation error compensation increment at which the error compensation converges to a steady state.
Optionally, the determining a type signal of a commutation error according to the absolute value of the second dc voltage value and the first dc voltage value includes:
if the absolute value of the second direct current voltage value is larger than the first direct current voltage value, outputting a low level signal; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;
the determining flag bit information corresponding to the type signal includes:
determining flag bit information corresponding to the type signal according to the following formula:
k＝(Sc-0.5)×2；
wherein S iscAnd k is a low level signal or a high level signal, and k is flag bit information corresponding to the type signal.
Optionally, the determining a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless dc motor includes:
acquiring an inverted voltage signal of the voltage signal;
and acquiring the target voltage signal according to the voltage signal, the inverted signal and the gating signal, wherein the target voltage signal is monotonically increased or monotonically decreased in a phase change period.
In the technical scheme provided by the embodiment of the invention, a first input end of a target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of a brushless direct current motor, a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor, and the target voltage acquisition circuit can determine a target voltage signal according to a voltage signal between the virtual neutral point and the bus midpoint; the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit, and the direct-current voltage acquisition circuit can determine a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in a target voltage signal according to the target voltage signal; the first input end of the commutation error type acquisition circuit is electrically connected with the first output end of the direct-current voltage acquisition circuit, the second input end of the commutation error type acquisition circuit is electrically connected with the second output end of the direct-current voltage acquisition circuit, and the commutation error type acquisition circuit can determine a type signal of a commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, namely the type signal is a digital signal and is used for indicating that the type of the commutation error is phase lead or phase lag; the general input and output interface of the digital processor is electrically connected with the output end of the commutation error type acquisition circuit, and the digital processor can receive the digital signal and determine the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor. Therefore, the technical scheme provided by the embodiment of the invention can realize commutation error compensation through the general input and output interface of the digital processor.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a commutation error compensation system of a brushless dc motor according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a brushless dc motor according to an embodiment of the present invention;
fig. 3 is a schematic diagram of detecting a commutation point of a motor according to an embodiment of the present invention;
FIG. 4 shows a voltage signal U without commutation error according to an embodiment of the present inventionMN’A schematic diagram of the waveform of (a);
FIG. 5 shows a voltage signal U with a lagging commutation error according to an embodiment of the present inventionMN’A schematic diagram of the waveform of (a);
FIG. 6 shows a commutation error advancing time voltage signal U according to an embodiment of the present inventionMN’A schematic diagram of the waveform of (a);
FIG. 7 shows a target voltage U according to an embodiment of the present inventionmultA schematic diagram of (a);
fig. 8 is a schematic flowchart illustrating a commutation error compensation method for a brushless dc motor according to an embodiment of the present invention;
fig. 9 is a schematic flowchart of another commutation error compensation method for a brushless dc motor according to an embodiment of the present invention;
fig. 10 is a schematic flowchart illustrating a commutation error compensation method for a brushless dc motor according to another embodiment of the present invention;
fig. 11 is a schematic flowchart of a commutation error compensation method for a brushless dc motor according to another embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention may be more clearly understood, a solution of the present invention will be further described below. It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those described herein; it is to be understood that the embodiments described in this specification are only some embodiments of the invention, and not all embodiments.
Fig. 1 is a schematic structural diagram of a commutation error compensation system of a brushless dc motor according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of a brushless dc motor according to an embodiment of the present invention, and referring to fig. 1 and fig. 2, a commutation error compensation system 100 of a brushless dc motor includes a target voltage obtaining circuit 110, a dc voltage obtaining circuit 120, a commutation error type obtaining circuit 130, and a digital processor 140.
A first input terminal of the target voltage obtaining circuit 110 is electrically connected to a virtual neutral point N' of the stator winding of the brushless dc motor 210, and a second input terminal of the target voltage obtaining circuit 110 is electrically connected to a bus midpoint M of the brushless dc motor 210. The target voltage obtaining circuit 110 is used for obtaining a voltage signal U between the virtual neutral point N' and the bus midpoint MMN’Determining a target voltage signal Umult。
The input terminal of the dc voltage obtaining circuit 120 is electrically connected to the output terminal of the target voltage obtaining circuit 110, and the dc voltage obtaining circuit 120 is configured to obtain the target voltage signal U according to the target voltage signal UmultDetermining a target voltage signal UmultMedium positive voltage signal Umult+Corresponding first DC voltage value Umult+_dcAnd a negative voltage signal Umult-Corresponding second DC voltage value Umult-_dc。
A first input terminal of the commutation error type obtaining circuit 130 is electrically connected to a first output terminal of the dc voltage obtaining circuit 120, and a second input terminal of the commutation error type obtaining circuit 130 is electrically connected to a second output terminal of the dc voltage obtaining circuit 120. The commutation error type obtaining circuit 130 is used for obtaining a second DC voltage value U according to the first DC voltage valuemult-_dcAbsolute value of (1 | U)mult-_dcL and a first DC voltage value Umult+_dcDetermining the type signal S of the commutation errorc. Type signal ScIncluding a high level signal 1 or a low level signal 0, a type signal ScThe type used to indicate commutation error is either phase lead or phase lag.
The general input/output interface G of the digital processor 140 is electrically connected to the output terminal of the commutation error type obtaining circuit 130, and the digital processor 140 is used for obtaining the type signal S according to the type signalcInitial compensation amount of commutation error
Determining commutation error compensation quantity by convergence factor lambda
Illustratively, as shown in fig. 2, the brushless dc motor 210 includes a-phase stator windings, B-phase stator windings, and C-phase stator windings.
The balance equation for the brushless dc motor 210 is as follows:
wherein L is the phase inductance of the brushless DC motor, R is the phase resistance of the brushless DC motor, eAIs A counter electromotive force, eBIs B counter electromotive force, eCIs C counter electromotive force, N is neutral point of stator winding in brushless DC motor, iAFor phase A current, iBIs phase B current, iCPhase C current, t is time.
When BC is conducted and A is suspended, i isA0, phase voltage uANEqual to A counter electromotive force eAWhen AC is conducted, B phase is suspended, i isB0, B-phase voltage uBNEqual to B counter electromotive force eBWhen AB is conducted and C is suspended, i isC0, C phase voltage uCNEqual to C counter electromotive force eC。
Fig. 3 is a schematic diagram of detecting a phase change point of a motor according to an embodiment of the present invention, and as shown in fig. 3, a zero crossing point of a phase voltage is delayed by 30 °, which is the phase change point. However, the delay of the filter and the delay of the hardware or software in the commutation error compensation system 100 can cause commutation errors
The phase change point is the phase voltage zero crossing point delay
FIG. 4 shows the present inventionThe embodiment provides a voltage signal U without commutation errorMN’Fig. 5 is a voltage signal U when the commutation error lagsMN’Fig. 6 is a schematic waveform diagram of a commutation error lead time voltage signal U according to an embodiment of the present inventionMN’Schematic diagram of the waveform of (1). Referring to FIGS. 4-6, when any one of SA, SB, and SC transitions, the voltage signal UMN’Performing phase change, and when SA, SB and SC do not generate jump, UMN’The target voltage obtaining circuit 110 may keep the voltage signal U unchanged when SA + SB + SC is equal to 1MN’Is inverted to form a target voltage signal U which monotonically decreases during the commutation periodmultAs shown in fig. 4-6.
In another embodiment, the target voltage obtaining circuit 110 may further be configured to output the voltage signal U when SA + SB + SC is 2MN’Is inverted to form a target voltage signal U which monotonically increases during the commutation periodmult。
The DC voltage acquisition circuit 120 receives the target voltage signal UmultAnd a target voltage signal U is providedmultSplit into positive voltage signals Umult+And a negative voltage signal Umult-A positive voltage signal Umult+According to a Fourier series decomposition, a positive voltage signal Umult+I.e. first direct voltage value Umult+_dcComprises the following steps:
wherein S is+Is a target voltage signal UmultArea of the positive portion.
Similarly, the negative voltage signal Umult-I.e. the second dc voltage value Umult-_dcComprises the following steps:
wherein S-is a target voltage signal UmultArea of the negative part.
Phase change error type of obtained electricityThe circuit 130 is capable of receiving a first direct current voltage value Umult+_dcAnd a second DC voltage value Umult-_dcAccording to the second DC voltage value Umult-_dcObtaining the corresponding absolute value | Umult-_dcAnd according to the absolute value | Umult-_dc| and a first direct current voltage value Umult+_dcThe type of commutation error is determined.
Illustratively, as shown in conjunction with fig. 4-6, without commutation error,
then S+＝S-，|Umult-_dc|＝Umult+_dcAs shown in fig. 4. If it is
Phase lag, S+<S-，Umult+_dc<|Umult-_dcIn this case, the commutation error compensation amount is shown in FIG. 5
Should satisfy less than 0, the commutation error type signal S generated by the commutation error type acquisition circuit 130cIs a low signal 0. If it is
Phase advance, S+>S-，Umult+_dc>|Umult-_dcIn this case, as shown in FIG. 6, the amount of commutation error compensation
Should satisfy more than 0, the commutation error type obtaining circuit 130 generates the type signal ScIs a high signal 1.
Type signal ScFor digital signals, the general purpose input output interface G of the digital processor 140 may receive the type signal ScAccording to the type signal ScThe type of commutation error can be obtained, so that the commutation error compensation amount can be determined
And based on the commutation error initial compensation quantity
And the convergence factor lambda can determine the commutation error compensation quantity
From this, it is known that the digital processor 140 can be based on the type signal ScInitial compensation amount of commutation error
Determining commutation error compensation quantity by convergence factor lambda
Thus, the phase change point is a phase voltage zero crossing delay
Thereby realizing the compensation of commutation error.
In the technical scheme provided by the embodiment of the invention, a first input end of a target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of a brushless direct current motor, a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor, and the target voltage acquisition circuit can determine a target voltage signal according to a voltage signal between the virtual neutral point and the bus midpoint; the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit, and the direct-current voltage acquisition circuit can determine a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal; the first input end of the commutation error type acquisition circuit is electrically connected with the first output end of the direct-current voltage acquisition circuit, the second input end of the commutation error type acquisition circuit is electrically connected with the second output end of the direct-current voltage acquisition circuit, and the commutation error type acquisition circuit can determine a type signal of a commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, namely the type signal is a digital signal and is used for indicating that the type of the commutation error is phase lead or phase lag; the general input and output interface of the digital processor is electrically connected with the output end of the commutation error type acquisition circuit, and the digital processor can receive the digital signal and determine the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor. Therefore, the technical scheme provided by the embodiment of the invention can realize commutation error compensation through the general input and output interface of the digital processor.
Optionally, with continued reference to fig. 1, the digital processor 140 includes: a flag bit information acquisition unit 141 and a compensation unit 142.
Wherein, the input end of the flag information obtaining unit 141 is electrically connected to the general input/output interface G, and the flag information obtaining circuit 141 is configured to obtain the type signal ScThe corresponding flag bit information k is determined.
An input end 142 of the compensation unit is electrically connected to an output end of the flag bit information obtaining unit 141, and the compensation unit 142 is used for determining a commutation error compensation amount according to the formula (3)
Wherein n is the number of compensation times,
for the commutation error compensation amount at the nth compensation,
for initial compensation of commutation errors, kiAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal obtained during the ith compensation.
Specifically, the flag bit information acquisition unit 141 acquires the flag bit information based on the type signal ScDetermine correspondencesBit zone information k, if ScIs a low level signal 0, the corresponding flag bit information k is 1, if ScFor a high level signal 1, the corresponding flag bit information k is-1, so that the flag bit information k can indicate the commutation error compensation amount
The symbol of (2).
The operation state of the compensation unit 142 is divided into two stages:
the first stage is that when N is less than or equal to N, the first compensation quantity after compensation is the initial compensation quantity of commutation error
On the basis of the above, each compensation increment
The attenuation is lambda times of the last compensation increment, the compensation increment is gradually reduced, and overshoot and oscillation are effectively weakened. Plus k determines the commutation error compensation
And if the compensation quantity is lag compensation quantity or lead compensation quantity, the commutation error is gradually reduced and converged through continuous accumulation in the mode.
The second stage is to avoid the final attenuation of the error compensation increment to zero, when the compensation times satisfy n>N, the compensation increment is maintained as the compensation times are increased
The method is not changed, so that the closed-loop compensation capability is still provided when the commutation error compensation is converged to a steady state, and slow error change caused by circuit drift and device aging is solved.
In the embodiment of the invention, the compensation process of the commutation error is divided into two stages, wherein the first stage is a commutation error compensation convergence stage, the compensation increment is gradually reduced, overshoot and oscillation are effectively weakened, and the second stage is a commutation error compensation stabilization stage, so that the commutation error compensation amount is prevented from being attenuated to zero, and the commutation error compensation system still has closed-loop compensation capability, thereby being capable of coping with slow error change caused by circuit drift and device aging.
Optionally, with continued reference to fig. 1, the commutation error type obtaining circuit 130 includes: a first inverter 131 and a comparator 132.
An input terminal of the first inverter 131 is electrically connected to a second input terminal of the commutation error type obtaining circuit 130, and the first inverter 131 is used for obtaining a second dc voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc|。
A first input terminal of the comparator 132 is electrically connected to the output terminal of the first inverter 131, and a second input terminal of the comparator 132 is electrically connected to a first input terminal of the commutation error type obtaining circuit 130. The comparator 132 is used for comparing the second DC voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| is greater than the first DC voltage value Umult+_dcOutputting a low level signal 0 if the second DC voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| is less than the first DC voltage value Umult+_dcAnd outputs a high level signal 1.
The compensation unit 142 is further configured to determine the type signal S according to equation (4)cCorresponding flag bit information k:
k＝(Sc-0.5)×2 (4)
wherein S iscIs a low level signal or a high level signal, k is a type signal ScCorresponding flag bit information.
In particular, as shown in figure 5,
i.e., S of the output of the comparator 132 when the phase is laggingcFor the low level signal 0, the compensation unit 142 determines the flag bit information k as-1 according to the formula (4), and the commutation error compensation amount
Thereby enabling phase commutation errors to be reduced. As shown in figure 6 of the drawings,
i.e., phase lead, S output by comparator 132cFor high level signal 1, the compensation unit 142 determines flag bit information k as 1 and commutation error compensation amount according to the formula
Thereby enabling phase commutation errors to be reduced.
In the embodiment of the invention, the first inverter and the comparator can output corresponding high level signals or low level signals, namely digital signals according to the lead or lag of the commutation errors, so that the digital processor can directly acquire the digital signals through the universal input and output end to determine the lead or lag of the commutation errors, an analog-to-digital converter is not required to be arranged in the commutation error compensation system, and hardware resources and software resources are saved.
Optionally, with continued reference to fig. 1, the dc voltage acquisition circuit 120 includes: a positive voltage dc voltage acquisition circuit 121 and a negative voltage dc voltage acquisition circuit 122.
The positive voltage dc voltage obtaining circuit 121 includes a first half-wave rectifier 1211 and a first capacitor C1, an input terminal of the first half-wave rectifier 1211 is electrically connected to a first terminal of the first capacitor C1 and an input terminal of the dc voltage obtaining circuit 120, and an output terminal of the first half-wave rectifier 1211 is electrically connected to a second terminal of the first capacitor C1 and a first output terminal of the dc voltage obtaining circuit 120. The first half-wave rectifier 1211 is for obtaining a target voltage signal UmultPositive voltage signal U inmult+The first capacitor C1 is used for acquiring the positive voltage signal Umult+Corresponding first DC voltage value Umult+_dc。
The negative voltage dc voltage obtaining circuit 122 includes a negative voltage half-wave rectifier 1221 and a second capacitor C2, an input terminal of the second half-wave rectifier 1221 is electrically connected to a first terminal of the second capacitor C2 and an input terminal of the dc voltage obtaining circuit 120, respectively, and an output terminal of the second half-wave rectifier 1221 is electrically connected to a second terminal of the second capacitor C2 and a second output terminal of the dc voltage obtaining circuit 120, respectively. Second half-wave rectifier 1221 for obtaining a target voltage signal UmultNegative voltage signal U inmult-The second capacitor C2 is used for obtaining a second dc voltage value U corresponding to the negative voltage signalmult-_dc。
Specifically, as shown in fig. 1, the first half-wave rectifier 1211 includes an operational amplifier, a resistor, and two diodes, wherein an anode of one diode is electrically connected to a first terminal of the resistor, an input terminal of the operational amplifier, and an input terminal of the first half-wave rectifier 1211, a cathode of the diode is electrically connected to a second terminal of the resistor, a cathode of the other diode, and an output terminal of the first half-wave rectifier 1211, and an anode of the other diode is electrically connected to an output terminal of the operational amplifier. Target voltage signal UmultThrough the rectification of the first half-wave rectifier 1211, a positive voltage signal U is generatedmult+. The first half-wave rectifier 1211 is a precise half-wave rectifier, and benefits from the high gain characteristic of the operational amplifier, so that even if there is a weak voltage variation at the input terminal of the operational amplifier, the diode is turned on to form a feedback loop, thereby avoiding the limitation of the diode turn-on threshold. A first capacitor C1 is added in a feedback loop of the operational amplifier, when the two diodes are cut off, the first capacitor C1 is charged, when the two diodes are conducted, the first capacitor C1 discharges to the resistor, and a positive voltage signal U is realizedmult+So that the first direct current voltage value U can be obtainedmult+_dc。
The second half-wave rectifier 1221 includes an operational amplifier, a resistor, and two diodes, wherein a cathode of one diode is electrically connected to a first end of the resistor, an input end of the operational amplifier, and an input end of the second half-wave rectifier 1221, an anode of the diode is electrically connected to a second end of the resistor, an anode of the other diode, and an output end of the second half-wave rectifier 1221, and a cathode of the other diode is electrically connected to an output end of the operational amplifier. Target voltage signal UmultThrough the rectification of the second half-wave rectifier 1221, a negative voltage signal U is generatedmult-. The second half-wave rectifier 1221 is a precise half-wave rectifier, and benefits from the high gain characteristic of the operational amplifier, so that even if there is a weak voltage variation at the input terminal of the operational amplifier, the diode is turned on to form a feedbackAnd the loop avoids the limitation of the conduction threshold of the diode. A second capacitor C2 is added in a feedback loop of the operational amplifier, when the two diodes are cut off, the second capacitor C2 is charged, and when the two diodes are conducted, the second capacitor C2 discharges to the resistor, so that the negative voltage signal U is realizedmult-So that the second DC voltage value U can be obtainedmult-_dc。
In the embodiment of the invention, the target voltage signal is rectified by the half-wave rectifier to obtain the positive voltage signal and the negative voltage signal, and the positive voltage signal and the negative voltage signal are subjected to smooth filtering by the capacitor to obtain the first direct current voltage value corresponding to the positive voltage signal and the second direct current voltage value corresponding to the negative voltage signal, so that the first direct current voltage value and the second direct current voltage value can be obtained by the hardware circuit, and the interrupt resource and the calculation resource of the commutation error compensation system 100 of the brushless direct current motor can be saved.
Optionally, with continued reference to fig. 1, the target voltage acquisition circuit 110 includes: a subtractor 111, a second inverter 112, and a gate 113.
A first input terminal of the subtractor 111 is electrically connected to a first input terminal of the target voltage obtaining circuit 110, and a second input terminal of the subtractor 111 is electrically connected to a second input terminal of the target voltage obtaining circuit 110. The subtracter 111 is used for acquiring a voltage signal U between the virtual neutral point and the bus midpointMN’。
An input end of the second inverter 112 is electrically connected to an output end of the subtractor 111, and the second inverter 112 is configured to obtain the voltage signal UMN’Is of opposite voltage signal-UMN’；
A first input terminal of the gate 113 is electrically connected to an output terminal of the second inverter 112, a second input terminal of the gate 113 is electrically connected to an output terminal of the subtractor 111, respectively, and the gate 113 is configured to be responsive to the voltage signal UMN’Inverted voltage signal-UMN’Generating a target voltage signal U by a sum strobe signal Smult。
Exemplarily, fig. 7 illustrates a target voltage U according to an embodiment of the present inventionmultAs shown in FIG. 7, a strobe signalWhen S is high, the gate 113 gates the output terminal of the second inverter 112, i.e., gates-UMN’When the gating signal S is low, the gate 113 gates the output terminal of the subtractor 111, i.e., gates UMN’Thereby generating a target voltage signal UmultTarget voltage signal UmultMonotonically decreasing during the commutation period. In other embodiments, the strobe signal S may be high, and the strobe signal U may be highMN’gating-U when gating signal S is lowMN’Thereby generating a target voltage signal UmultTarget voltage signal UmultMonotonically increasing during the commutation period.
In the embodiment of the invention, the voltage signal between the virtual neutral point and the bus midpoint is acquired through the subtracter, the inverted voltage signal of the voltage signal is acquired through the second inverter, and the target voltage signal is acquired through the gate, so that the target voltage signal can be acquired through the hardware circuit, and the interrupt resource and the calculation resource of the commutation error compensation system 100 of the brushless direct current motor can be saved.
The embodiment of the present invention further provides a commutation error compensation method for a brushless dc motor, which is applied to the commutation error compensation system 100 for a brushless dc motor provided in the above embodiment, and has the beneficial effect of the commutation error compensation 100 for a brushless dc motor.
Fig. 8 is a flowchart illustrating a commutation error compensation method of a brushless dc motor according to an embodiment of the present invention, which is applied to the commutation error compensation system 100 of the brushless dc motor shown in fig. 1. As shown in fig. 8, the commutation error compensation method specifically includes the steps of:
s101, determining a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless direct current motor.
Specifically, the target voltage acquisition circuit 110 can acquire the voltage signal U between the virtual neutral point N' and the bus midpoint MMN’And according to the voltage signal UMN’Determining a target voltage signal Umult。
S102, according to the target voltage signal, determining a first direct current voltage value corresponding to a positive voltage signal and a second direct current voltage value corresponding to a negative voltage signal in the target voltage signal.
Specifically, the dc voltage obtaining circuit 120 can receive the target voltage signal U output by the target voltage obtaining circuit 110multAccording to the received target voltage signal UmultDetermining a target voltage signal UmultPositive voltage signal U inmult+And a negative voltage signal Umult-And respectively determine a positive voltage signal Umult+Corresponding first DC voltage value Umult+_dcAnd a negative voltage signal Umult-Corresponding second DC voltage value Umult-_dc。
S103, determining a type signal of the commutation error according to the absolute value of the second direct current voltage value and the first direct current voltage value.
The type signal includes a high level signal or a low level signal, and the type signal is used to indicate whether the type of the commutation error is a phase lead or a phase lag.
Specifically, the commutation error type obtaining circuit 130 can receive the second dc voltage value U output by the dc voltage obtaining circuit 120mult-_dcAnd determining its absolute value | Umult-_dcL. The commutation error type obtaining circuit 130 can also receive the first dc voltage value U output by the dc voltage obtaining circuit 120mult+_dcAnd according to the second DC voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| and a first direct current voltage value Umult+_dcDetermining the type of commutation error as either phase lead or phase lag, and outputting a type signal S indicative of the commutation errorcType signal S herecIs a digital signal, i.e. a high level signal 1 or a low level signal 0.
And S104, determining commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor.
Specifically, the digital processor 140 can directly acquire the type signal S through the general input/output interface GcDue to type signal ScIs a digital signal and therefore does not require an ADC. The digital processor 140 can beAccording to type signal ScDetermining commutation error compensation
Can also be initially compensated for by commutation error
And the convergence factor lambda can determine the commutation error compensation quantity
The size of (2).
In the technical scheme provided by the embodiment of the invention, a target voltage signal is determined according to a voltage signal between a virtual neutral point and a bus midpoint; determining a first direct current voltage value corresponding to a positive voltage signal and a second direct current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal; determining a type signal of the commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, namely the type signal is a digital signal and is used for indicating that the type of the commutation error is phase lead or phase lag; the commutation error compensation quantity is determined according to the type signal, the commutation error initial compensation quantity and the convergence factor, the digital processor can directly obtain the type signal through the general input and output interface, and the commutation error compensation quantity can be determined according to the type signal, the initial compensation quantity and the convergence factor, so that the commutation error compensation can be realized through the general input and output interface of the digital processor without setting an ADC (analog to digital converter).
Fig. 9 is a schematic flowchart of another commutation error compensation method for a brushless dc motor according to an embodiment of the present invention, and fig. 9 is a detailed description of a possible implementation manner when S104 is executed on the basis of the embodiment shown in fig. 8, where the method includes:
and S1041, determining flag bit information corresponding to the type signal according to the type signal.
Specifically, as shown in fig. 1, the digital processor 140 includes a flag bit information acquisition unit 141 and a compensation unit 142, a flagThe bit information obtaining unit 141 can obtain the type signal ScDetermining the type signal ScCorresponding zone bit information k, the zone bit information k is 1 or-1, the zone bit information k is used for representing commutation error compensation quantity
Sign of, i.e. commutation error compensation quantity
In the direction of (a).
And S1043, determining the commutation error compensation amount according to the formula (3).
Specifically, the compensation unit 142 initially compensates a preset phase error by a preset compensation amount
The amount of phase error compensation can be determined by substituting the convergence factor lambda into equation (3)
The size of (2).
According to the formula (3), the process of commutation error compensation is divided into two stages:
the first stage is that when N is less than or equal to N, the first compensation amount after compensation is started is the initial compensation amount of commutation error
On the basis of the above, each compensation increment
The attenuation is lambda times of the increment of the last compensation, the increment of the compensation is gradually reduced, and the overshoot and the oscillation are effectively weakened. Plus k determines the commutation error compensation
The lag compensation quantity or the lead compensation quantity is continuously accumulated in the mode, so that the commutation error is gradually reduced and converged.
The second stage is to avoid errorFinally, the increment of the difference compensation is attenuated to zero, and when the compensation times satisfy n>N, the amount of increase in compensation is maintained as the number of compensations increases
The method is unchanged, so that the closed-loop compensation capability is still ensured when the commutation error compensation converges to a steady state, and slow error change caused by circuit drift and device aging is responded.
In the embodiment of the invention, the compensation process of the commutation error is divided into two stages, wherein the first stage is a commutation error compensation convergence stage, the compensation increment is gradually reduced, overshoot and oscillation are effectively weakened, and the second stage is a commutation error compensation stabilization stage, so that the commutation error compensation amount is prevented from being attenuated to zero, and the commutation error compensation system still has closed-loop compensation capability, thereby being capable of coping with slow error change caused by circuit drift and device aging.
Optionally, with continued reference to fig. 9, before performing S1043, the method further includes:
s1042, determining the preset threshold according to formula (5):
where δ is the commutation error compensation increment at which the error compensation converges to a steady state.
Specifically, the compensation unit 142 initially compensates the preset delta and phase errors by a preset compensation amount
And substituting the convergence factor lambda into the formula (5), determining a preset threshold value N, and when the compensation times reach the preset threshold value N, indicating that the commutation error compensation enters a steady state. The smaller the delta, the slower the convergence process of commutation error compensation, the weaker the steady-state periodic oscillation, and the higher the precision of commutation error compensation.
Fig. 10 is a schematic flowchart of another commutation error compensation method for a brushless dc motor according to an embodiment of the present invention, and fig. 10 is a detailed description of a possible implementation manner when S103 is executed on the basis of the embodiment shown in fig. 9, where the implementation manner includes:
s103', if the absolute value of the second direct current voltage value is larger than the first direct current voltage value, outputting a low level signal; and if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal.
Specifically, as shown in fig. 1, the commutation error type obtaining circuit 130 includes a second inverter 131 and a comparator 132, and the second inverter 131 can receive the second dc voltage value U output by the dc voltage obtaining circuit 120mult-_dcAnd determining its absolute value | Umult-_dcThe comparator 132 can receive the second dc voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| and a first direct current voltage value Umult+_dcAnd at a second DC voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| is greater than the first DC voltage value Umult+_dcWhen the voltage is on, a low level signal 0 is output, and the voltage is at a second DC voltage value Umult-_dcAbsolute value of (1 | U)mult-_dc| is less than the first DC voltage value Umult+_dcAt this time, a high level signal 1 is output.
A detailed description of one possible implementation manner when S1041 is performed is shown in fig. 10:
and S1041', determining flag bit information corresponding to the type signal according to the formula (4).
Illustratively, as shown in FIG. 5,
i.e. phase lag, ScFor low level signal 0, determining flag bit information k as-1 according to formula (4), and compensating for commutation error
Thereby enabling phase commutation errors to be reduced. As shown in figure 6 of the drawings,
i.e. phase lead, ScFor a high level signal 1, determining flag bit information k as 1 according to formula (4), and compensating for commutation error
Thereby enabling phase commutation errors to be reduced.
In the embodiment of the invention, the sign of the commutation error compensation quantity can be obtained according to the type signal, so that the commutation error can be effectively reduced under the action of the phase error compensation quantity, and the commutation precision is improved.
Fig. 11 is a schematic flowchart of another commutation error compensation method for a brushless dc motor according to an embodiment of the present invention, and fig. 11 is a detailed description of a possible implementation manner when executing S101 on the basis of the embodiment shown in fig. 8, where the method includes:
s1011, obtaining the inverse voltage signal of the voltage signal.
Specifically, the second inverter 112 receives the voltage signal U output by the subtractor 111MN’And according to the voltage signal UMN’Obtaining its corresponding inverse voltage signal-UMN’。
And S1012, acquiring the target voltage signal according to the voltage signal, the inverted signal and the gating signal.
The target voltage signal monotonically increases or monotonically decreases during the commutation period.
Illustratively, as shown in fig. 7, when the strobe signal S is high, the gate 113 gates the output terminal of the second inverter 112, i.e., gate-UMN’When the gating signal S is low, the gate 113 gates the output terminal of the subtractor 111, i.e., gates UMN’Thereby obtaining the target voltage signal U which monotonically decreases in the commutation periodmult。
In other embodiments, the strobe signal S may be high, and the strobe signal U may be highMN’gating-U when gating signal S is lowMN’Thereby obtaining the target voltage signal U which monotonically increases in the commutation periodmult。
Based on a voltage signal UMN’Voltage signal U whether phase change is accurate, leading or laggingMN’Of positive voltage electrical signal during a cycleThe absolute values of the direct current component and the direct current component of the negative voltage electrical signal are both equal. According to the embodiment of the invention, the target voltage signal is obtained according to the voltage signal, and the target voltage signal can break through the rule, so that when the phase is advanced or lagged, the absolute values of the direct current component of the positive voltage electric signal and the direct current component of the negative voltage electric signal in one period are not equal, and the commutation error can be accurately reflected.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A commutation error compensation system for a brushless dc motor, comprising: the device comprises a target voltage acquisition circuit, a direct current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;
a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the target voltage obtaining circuit is used for determining a target voltage signal according to a voltage signal between the virtual neutral point and the bus midpoint;
the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; the direct-current voltage acquisition circuit is used for determining a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal according to the target voltage signal;
a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; the commutation error type obtaining circuit is used for determining a type signal of a commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value; the type signal comprises a high level signal or a low level signal and is used for indicating the type of the commutation error as phase lead or phase lag;
a general input/output interface of the digital processor is electrically connected with an output end of the commutation error type acquisition circuit; the digital processor is used for determining commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor;
the digital processor includes: a flag bit information acquisition unit and a compensation unit;
the input end of the zone bit information acquisition unit is electrically connected with the general input/output interface, and the zone bit information acquisition circuit is used for determining corresponding zone bit information according to the type signal;
the input end of the compensation unit is electrically connected with the output end of the zone bit information acquisition unit, and the compensation unit is used for determining the commutation error compensation quantity according to the following formula:
wherein n is the number of compensation times,
for the commutation error compensation amount at the nth compensation,
for initial compensation of commutation errors, kiAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.
2. The commutation error compensation system of claim 1, wherein the commutation error type obtaining circuit comprises: a first inverter and a comparator;
the input end of the first inverter is electrically connected with the second input end of the commutation error type acquisition circuit, and the first inverter is used for acquiring the absolute value of the second direct-current voltage value;
a first input end of the comparator is electrically connected with an output end of the first phase inverter, and a second input end of the comparator is electrically connected with a first input end of the commutation error type obtaining circuit; the comparator is used for outputting a low level signal if the absolute value of the second direct current voltage value is greater than the first direct current voltage value; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;
the compensation unit is further configured to determine flag bit information corresponding to the type signal according to the following formula:
k＝(Sc-0.5)×2；
wherein S iscAnd k is a low level signal or a high level signal, and is flag bit information corresponding to the type signal.
3. The commutation error compensation system of claim 1 or 2, wherein the dc voltage acquisition circuit comprises: a positive voltage direct current voltage acquisition circuit and a negative voltage direct current voltage acquisition circuit;
the positive voltage direct current voltage acquisition circuit comprises a first half-wave rectifier and a first capacitor, wherein the input end of the first half-wave rectifier is electrically connected with the first end of the first capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the first half-wave rectifier is electrically connected with the second end of the first capacitor and the first output end of the direct current voltage acquisition circuit respectively; the first half-wave rectifier is used for acquiring a positive voltage signal in the target voltage signal, and the first capacitor is used for acquiring a first direct-current voltage value corresponding to the positive voltage signal;
the negative voltage direct current voltage acquisition circuit comprises a second half-wave rectifier and a second capacitor, wherein the input end of the second half-wave rectifier is electrically connected with the first end of the second capacitor and the input end of the direct current voltage acquisition circuit respectively, and the output end of the second half-wave rectifier is electrically connected with the second end of the second capacitor and the second output end of the direct current voltage acquisition circuit respectively; the second half-wave rectifier is used for acquiring a negative voltage signal in the target voltage signal, and the second capacitor is used for acquiring a second direct-current voltage value corresponding to the negative voltage signal.
4. The commutation error compensation system of claim 1 or 2, wherein the target voltage acquisition circuit comprises: the subtractor, the second inverter and the gate;
a first input end of the subtractor is electrically connected with a first input end of the target voltage acquisition circuit, and a second input end of the subtractor is electrically connected with a second input end of the target voltage acquisition circuit; the subtracter is used for acquiring a voltage signal between the virtual neutral point and the bus midpoint;
the input end of the second inverter is electrically connected with the output end of the subtracter, and the second inverter is used for acquiring an inverted voltage signal of the voltage signal;
the first input end of the gate is electrically connected with the output end of the second inverter, the second input end of the gate is electrically connected with the output end of the subtracter respectively, and the gate is used for generating the target voltage signal according to the voltage signal, the inverted voltage signal and the gate signal.
5. A commutation error compensation method for a brushless DC motor, the commutation error compensation method being applicable to a commutation error compensation system for a brushless DC motor, the commutation error compensation system comprising: the device comprises a target voltage acquisition circuit, a direct-current voltage acquisition circuit, a commutation error type acquisition circuit and a digital processor;
a first input end of the target voltage acquisition circuit is electrically connected with a virtual neutral point of a stator winding of the brushless direct current motor, and a second input end of the target voltage acquisition circuit is electrically connected with a bus midpoint of the brushless direct current motor; the input end of the direct-current voltage acquisition circuit is electrically connected with the output end of the target voltage acquisition circuit; a first input end of the commutation error type acquisition circuit is electrically connected with a first output end of the direct-current voltage acquisition circuit, and a second input end of the commutation error type acquisition circuit is electrically connected with a second output end of the direct-current voltage acquisition circuit; a general input/output interface of the digital processor is electrically connected with an output end of the commutation error type acquisition circuit;
the commutation error compensation method comprises the following steps:
determining a target voltage signal according to a voltage signal between a virtual neutral point and a bus midpoint in the brushless direct current motor;
according to the target voltage signal, determining a first direct-current voltage value corresponding to a positive voltage signal and a second direct-current voltage value corresponding to a negative voltage signal in the target voltage signal;
determining a type signal of the commutation error according to the absolute value of the second direct-current voltage value and the first direct-current voltage value, wherein the type signal comprises a high level signal or a low level signal, and the type signal is used for indicating that the type of the commutation error is phase lead or phase lag;
determining commutation error compensation quantity according to the type signal, the commutation error initial compensation quantity and the convergence factor:
the determining the commutation error compensation amount according to the type signal, the commutation error initial compensation amount and the convergence factor specifically includes:
determining flag bit information corresponding to the type signal according to the type signal;
determining the commutation error compensation amount according to the following formula:
wherein n is the number of compensation times,
for the commutation error compensation amount at the nth compensation,
for initial compensation of commutation errors, kiAnd λ is a convergence factor, and N is a preset threshold, for the flag bit information corresponding to the type signal acquired during the ith compensation.
6. The method of claim 5, wherein prior to determining the commutation error compensation amount, further comprising:
determining the preset threshold value according to the following formula:
where δ is the commutation error compensation increment at which the error compensation converges to a steady state.
7. The method of claim 5, wherein determining the type signal of commutation error based on the absolute value of the second DC voltage value and the first DC voltage value comprises:
if the absolute value of the second direct current voltage value is larger than the first direct current voltage value, outputting a low level signal; if the absolute value of the second direct current voltage value is smaller than the first direct current voltage value, outputting a high level signal;
the determining flag bit information corresponding to the type signal includes:
determining flag bit information corresponding to the type signal according to the following formula:
k＝(Sc-0.5)×2；
wherein S iscAnd k is a low level signal or a high level signal, and k is flag bit information corresponding to the type signal.
8. The method according to any one of claims 5-7, wherein determining a target voltage signal from a voltage signal between a virtual neutral point and a bus midpoint in the brushless DC motor comprises:
acquiring an inverted voltage signal of the voltage signal;
and acquiring the target voltage signal according to the voltage signal, the inverted voltage signal and the gating signal, wherein the target voltage signal is monotonically increased or monotonically decreased in a commutation period.
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