CN113314489B

CN113314489B - Semiconductor structure and method for forming semiconductor structure

Info

Publication number: CN113314489B
Application number: CN202110584317.4A
Authority: CN
Inventors: 邢程; 王清蕴
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2023-03-10
Anticipated expiration: 2041-05-27
Also published as: CN113314489A

Abstract

A semiconductor structure and method of forming the same, the structure comprising: the first substrate is provided with a first surface and a second surface, a plurality of first connecting layers are arranged in the first substrate, the first surface of each first connecting layer is exposed out of the surface of the corresponding first connecting layer, the projection of each first connecting layer on the first surface of the first substrate is rectangular, each rectangle is provided with a first side and a second side, and the first side is larger than the second side; the second substrate is bonded with the first substrate, the second substrate is provided with a third face and a fourth face, the third face of the second substrate is bonded with the first face of the first substrate, the second substrate is internally provided with a plurality of second connecting layers, the third face of the second connecting layers is exposed out of the surface of the second connecting layer, the projection of the second connecting layers on the surface of the second substrate is rectangular, the rectangle is provided with a third face and a fourth face, the third face is larger than the fourth face, the first connecting layers and the second connecting layers are in one-to-one correspondence, the corresponding surfaces of the first connecting layers and the second connecting layers coincide, and the first face is perpendicular to the third face. The performance of the semiconductor structure is improved.

Description

Semiconductor structure and method for forming semiconductor structure

Technical Field

The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Semiconductor devices in planar structures have approached their practical expansion limits, posing serious challenges to the semiconductor industry. The new 3D technology, which vertically stacks multiple layers of device units, can support the accommodation of higher capacity in a smaller space, thereby bringing great cost savings, energy consumption reduction, and significant performance improvement to fully meet the needs of numerous consumer mobile devices and the most demanding enterprise deployment.

The existing 3D technology is to attach two wafers of devices with different functions together by generating covalent chemical bonds.

However, there are many problems with existing 3D technologies that we need to continuously solve.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which aims to improve the existing 3D technology.

To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate having opposing first and second faces; the substrate comprises a plurality of connecting layers positioned in the substrate, wherein the first surface of the substrate is exposed out of the surface of the connecting layers, the projection of the connecting layers on the first surface of the substrate is rectangular, the rectangle is provided with a first side and a second side which are perpendicular to each other, and the first side is larger than the second side.

Optionally, the substrate includes a plurality of chip regions, a plurality of the connection layers are distributed in an array in the chip regions, a first distance is provided between adjacent connection layers in a direction parallel to the first edge, a second distance is provided between adjacent connection layers in a direction parallel to the second edge, the first distance is smaller than the second distance, and the first distance is smaller than the size of the first edge.

Optionally, the size of the second space is equal to the size of the first side, and the size of the first space is equal to the size of the second side.

Optionally, the length ratio of the first side to the second side is 7.

Optionally, the method further includes: a device layer located within the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the connection layer is on the device layer and electrically connected to the device structure.

Optionally, the material of the connection layer includes a metal including one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

In order to solve the above technical problem, a technical solution of the present invention further provides a semiconductor structure, including: the first substrate is provided with a first surface and a second surface which are opposite, a plurality of first connecting layers are arranged in the first substrate, the first surface of the first substrate is exposed out of the surface of the first connecting layers, the projection of the first connecting layers on the first surface of the first substrate is rectangular, the rectangle is provided with a first side and a second side which are vertical to each other, and the first side is larger than the second side; with the second substrate of first substrate bonding, the second substrate has relative third face and fourth face, the bonding of second substrate third face and first substrate, a plurality of second articulamentum has in the second substrate, second substrate third face exposes second articulamentum surface, the projection of second articulamentum on the second substrate surface is the rectangle, the rectangle has mutually perpendicular's third edge and fourth side, and the third edge is greater than the fourth side, and is a plurality of first articulamentum and a plurality of second articulamentum one-to-one, the coincidence of corresponding first articulamentum surface and second articulamentum surface, just first edge is perpendicular with third edge.

Optionally, the surface of each first connection layer is overlapped with the surface of one second connection layer to form an overlapped region, and the areas of the overlapped regions are the same.

Optionally, the first side and the third side have the same length, and the second side and the fourth side have the same length.

Optionally, the first substrate includes a plurality of first chip regions, the first connection layers are distributed in an array in the first chip regions, a first distance is formed between adjacent first connection layers in a direction parallel to the first edge, a second distance is formed between adjacent first connection layers in a direction parallel to the second edge, the first distance is smaller than the second distance, and the first distance is smaller than a size of the first edge.

Optionally, the second substrate includes a plurality of second chip regions, and is a plurality of the second connection layers are distributed in an array in the second chip region, and are parallel to each other between adjacent second connection layers the third distance is formed in the third direction, and are parallel to each other between adjacent second connection layers the fourth distance is formed in the fourth direction, and the third distance is smaller than the fourth distance, and the third distance is smaller than the size of the third side.

Optionally, the size of the third distance is equal to the size of the fourth side, and the size of the fourth distance is equal to the size of the third side.

Optionally, the length ratio of the first side to the second side is 7.

Optionally, the method further includes: a first device layer located within a first substrate, the first device layer including a first isolation structure and a first device structure located within the first isolation structure, the first device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the first connection layer is on the first device layer and is electrically connected to the first device structure.

Optionally, the method further includes: a second device layer located within a second substrate, the second device layer including a second isolation structure and a second device structure located within the second isolation structure, the second device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the second connection layer is located on a second device layer, and the second connection layer is electrically connected with the second device structure.

Optionally, the material of the first connection layer includes a metal including one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the material of the second connection layer comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate having first and second opposing faces; the method comprises the steps of forming a plurality of connecting layers in a substrate, wherein the surface of the connecting layer is exposed out of the first surface of the substrate, the projection of the connecting layers on the first surface of the substrate is rectangular, the rectangle is provided with a first side and a second side which are perpendicular to each other, and the first side is larger than the second side.

Optionally, the length ratio of the first side to the second side is 7.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite, a plurality of first connecting layers are arranged in the first substrate, the first surface of the first substrate is exposed out of the surface of the first connecting layers, the projection of the first connecting layers on the first surface of the first substrate is rectangular, the rectangle is provided with a first side and a second side which are perpendicular to each other, and the first side is larger than the second side; providing a second substrate, wherein the second substrate is provided with a third surface and a fourth surface which are opposite to each other, a plurality of second connecting layers are arranged in the second substrate, the third surface of the second substrate is exposed out of the surface of the second connecting layer, the projection of the second connecting layers on the surface of the second substrate is a rectangle, the rectangle is provided with a third edge and a fourth edge which are perpendicular to each other, and the third edge is larger than the fourth edge; and bonding the first surface of the first substrate with the third surface of the second substrate, wherein the first connecting layers correspond to the second connecting layers one to one, the surfaces of the corresponding first connecting layers coincide with the surfaces of the second connecting layers, and the first edge is perpendicular to the third edge.

Optionally, the surface of each first connection layer coincides with the surface of one second connection layer to form an overlapping region, and the areas of the overlapping regions are the same.

Optionally, the second substrate includes a plurality of second chip regions, and is a plurality of the second connection layers are distributed in an array in the second chip region, and are parallel to each other between adjacent second connection layers the third distance is formed in the third edge direction, and are parallel to each other between adjacent second connection layers the fourth distance is formed in the fourth edge direction, and the third distance is smaller than the fourth distance, and the third distance is smaller than the size of the third edge.

Optionally, the length ratio of the first side to the second side is 7.

Optionally, the size of the first side and the third side is 1.4a, the size of the second side and the fourth side is 0.6a, and a is a length coefficient; when the first surface of the first substrate and the third surface of the second substrate are bonded by taking the coincidence of the center of the first connecting layer and the center of the second connecting layer as a reference, the offset range of the first connecting layer and the second connecting layer in the extending direction of the first edge is as follows: -1.4 a-0.6 a)/2 to + (1.4 a-0.6 a)/2, the offset range of the first and second connection layers in the third extension direction is: (-1.4 a-0.6 a)/2 to (-1.4 a-0.6 a)/2.

Compared with the prior art, the technical scheme of the invention has the following beneficial effects:

in the structure of the technical scheme of the invention, the substrate is internally provided with a plurality of connecting layers, the projection of each connecting layer on the first surface of the substrate is rectangular, the rectangle is provided with a first side and a second side which are perpendicular to each other, and the first side is larger than the second side. The connecting layer distributes the surface area of the connecting layer along the direction of the first edge on the premise of meeting the design rule, so that the limit of excursion when two substrates are bonded subsequently is improved, namely, the two connecting layers can be ensured to have larger overlapping area only by ensuring the surface cross overlapping of the two connecting layers, and the resistance value of the bonded device is ensured.

Furthermore, the connecting layers are distributed in an array mode in the chip area, the first distance is smaller than the second distance, and the first distance is smaller than the size of the first edge. Therefore, the limitation that the two substrates can be deviated when being bonded subsequently is improved, and the requirements can be met only by ensuring that the surfaces of the two connecting layers are crossed and superposed and the two first edges are vertical.

In the structure of the technical scheme of the invention, the third surface of the second substrate is bonded with the first surface of the first substrate, the plurality of first connecting layers correspond to the plurality of second connecting layers one by one, the surfaces of the corresponding first connecting layers are superposed with the surfaces of the second connecting layers, and the first edge is perpendicular to the third edge. When the first surface of the first substrate is bonded with the third surface of the second substrate, on one hand, the bonding area of the first connecting layer and the second connecting layer can be ensured, and the resistance value of the device is ensured; on the other hand, the limit of excursion when the first surface of the first substrate is bonded with the third surface of the second substrate is improved, namely the requirement can be met only by ensuring that the surface of the first connecting layer is crossed and superposed with the surface of the second connecting layer, and the first edge is perpendicular to the third edge. Thereby improving the production yield.

Furthermore, the surface of each first connecting layer is overlapped with the surface of one second connecting layer to form an overlapped area, and the areas of the overlapped areas are the same. Therefore, the resistance value of the bonded first substrate and the bonded second substrate is stable, and the contact resistance uniformity of the first connecting layer and the second connecting layer is good.

Further, the first side and the third side have the same length, and the second side and the fourth side have the same length. I.e. the projected pattern of the first connection layer and the projected pattern of the second connection layer are both equal in circumference and area. Therefore, when the connecting layer with the same size as the first connecting layer and the second connecting layer is formed on one wafer, the flattening process is uniform when the connecting layer is formed, the surface smoothness of the formed connecting layer is good, the first substrate and the second substrate can be tightly combined when the first substrate and the second substrate are bonded, and the bonding yield is improved.

Drawings

FIGS. 1-3 are schematic views illustrating a semiconductor structure formation process according to an embodiment;

FIGS. 4-7 are schematic structural diagrams illustrating a semiconductor structure formation process according to an embodiment of the present invention;

fig. 8 to 17 are schematic structural views illustrating a process of forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

As described in the background, there are many problems with existing 3D technologies that we need to continuously solve. The analysis will now be described with reference to specific examples.

Fig. 1 to 3 are schematic structural diagrams illustrating a semiconductor structure forming process according to an embodiment.

Referring to fig. 1, a first substrate 100 is provided, the first substrate 100 having a first side and a second side opposite to each other; a first dielectric layer (not shown) and a plurality of first connection layers 101 located in the first dielectric layer are formed on a first substrate 100, the first connection layers 101 are arranged in an array, the first dielectric layer exposes the surface of the first connection layer 101, the surface of the first dielectric layer is a first surface of the first substrate 100, a projection of the first connection layer 101 on the first substrate 100 is a first square, and a side length of the first square is L1.

Referring to fig. 2, a second substrate 200 is provided, the second substrate 200 having a third surface and a fourth surface opposite to each other; a second dielectric layer (not shown) and a plurality of second connection layers 201 located in the second dielectric layer are formed on a second substrate 200, the plurality of second connection layers 201 are arranged in an array, the second dielectric layer exposes the surface of the second connection layer 201, the surface of the second dielectric layer is the third surface of the second substrate 200, the projection of the second connection layer 201 on the second substrate 200 is a second square, the side length of the second square is L2, and the length of the L2 is less than the length of the L1.

Referring to fig. 3, in fig. 3, the second substrate 200 is omitted, the first surface of the first substrate 100 is bonded to the third surface of the second substrate 200, the plurality of first connection layers 101 correspond to the plurality of second connection layers 201 one by one, and the projection of the second connection layer 201 is located within the projection range of the first connection layer 101.

In the process of forming the semiconductor structure, the process of forming the first connection layer 101 causes a deviation between the position of the first connection layer 101 and the position of the design pattern, and the process of forming the second connection layer 201 causes a deviation between the position of the second connection layer 201 and the position of the design pattern, and when the first surface of the first substrate 100 and the third surface of the second substrate 200 are bonded, a machine deviation occurs, and thus, when two wafers are bonded, a deviation is inevitable.

When the first surface of the first substrate 100 is bonded to the third surface of the second substrate 200, the projection of the second connection layer 201 needs to be located within the projection range of the first connection layer 101, so as to ensure that the resistance value of the second connection layer 201 and the first connection layer 101 after being bonded meets the requirement. However, it cannot be completely ensured that the projection of the attached second connection layer 201 is located within the projection range of the first connection layer 101, and when only a part of the projection of the attached second connection layer 201 is located within the projection range of the first connection layer 101, the attachment area of the second connection layer 201 and the first connection layer 101 is small, and the resistance value is large, which affects the performance of the device.

In order to solve the above problems, embodiments of the present invention provide a semiconductor structure and a method for forming the same, so as to improve 3D technology.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 4 to 7 are schematic structural diagrams illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 4 and fig. 5, fig. 4 is a top view of fig. 5, and fig. 5 is a schematic cross-sectional view taken along a section line AA1 of fig. 4, providing a substrate 300, where the substrate 300 has a first side and a second side opposite to each other.

The substrate 300 includes a plurality of chip regions (not shown), and in this embodiment, the substrate 300 further includes scribe line regions (not shown) located between adjacent chip regions.

With continued reference to fig. 4 and 5, device layers are formed within the substrate 300, including isolation structures 302 and device structures 303 located within the isolation structures 302.

The device structure 303 includes one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure. In this embodiment, the device structure 303 includes a transistor.

The material of the isolation structure 302 comprises a dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In the present embodiment, the material of the isolation structure 302 includes silicon oxide.

With continued reference to fig. 4 and 5, a dielectric layer 304 is formed over the device layer.

The dielectric layer 304 provides structural support for subsequently formed connecting layers.

The material of the dielectric layer 304 comprises a dielectric material comprising one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride in combination. In the present embodiment, the material of the dielectric layer 304 includes silicon oxide.

In this embodiment, the substrate 300 includes a base 301, a device layer on the base 301, and a dielectric layer 304 on the device layer.

In this embodiment, the material of the substrate 301 is silicon.

In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

Referring to fig. 6 and 7, fig. 7 is a schematic cross-sectional structure of fig. 6 along a cross-sectional line BB1, fig. 6 is a top view of fig. 7, a plurality of connection layers 305 are formed in a substrate 300, a surface of the connection layers 305 is exposed on a first surface of the substrate 300, a projection of the connection layers 305 on the first surface of the substrate 300 is a rectangle, the rectangle has a first side L1 and a second side S1 perpendicular to each other, and the first side L1 is greater than the second side S1.

The projection of the connecting layer 305 on the first surface of the substrate 300 is a rectangle, the rectangle has a first edge L1 and a second edge S1 which are perpendicular to each other, and the first edge L1 is larger than the second edge S1, so that the connecting layer 305 distributes the surface area of the connecting layer 305 along the direction of the first edge L1 on the premise of meeting the design rule, thereby improving the limitation of excursion when bonding two substrates subsequently, namely, only ensuring that the surfaces of the two connecting layers 305 are crossed and overlapped, ensuring that the two connecting layers 305 have larger overlapping area, and ensuring the resistance value of the bonded device.

The connection layer 305 is located on the device layer, and the connection layer 305 is electrically connected to the device structure 303.

In this embodiment, the connection layers 305 are distributed in an array in the chip region, a first distance d1 is between adjacent connection layers 305 in a direction parallel to the first side L1, a second distance d2 is between adjacent connection layers 305 in a direction parallel to the second side S1, the first distance d1 is smaller than the second distance d2, and the first distance d1 is smaller than the size of the first side L1.

The connection layers 305 are distributed in an array in the chip region, the first distance d1 is smaller than the second distance d2, and the first distance d1 is smaller than the size of the first edge L1. The limitation of offset when subsequently bonding two substrates is increased, and the requirement can be met only by ensuring that the surfaces of the two connection layers 305 are crossed and overlapped and the two first edges L1 are perpendicular.

In this embodiment, the second distance d2 is equal to the first side L1, and the first distance d1 is equal to the second side S1. So as to meet the design requirement of the size of the device and save the area of the chip.

The length ratio of the first side L1 to the second side S1 is 7.

In this embodiment, the dimension of the first side L1 is 1.4a, the dimension of the second side S1 is 0.6a, the dimension of the second pitch d2 is 1.4a, the dimension of the first pitch d1 is 0.6a, and a is a length coefficient.

In other embodiments, the connection layers may be distributed in the chip region in a manner other than an array.

The forming method for forming the plurality of connection layers 305 includes: forming openings (not shown) in the dielectric layer 304; forming a layer of connecting material (not shown) within the opening and over the dielectric layer 304; the connecting material layer is planarized until the surface of the dielectric layer 304 is exposed, forming a connecting layer 305 within the dielectric layer 304.

The material of the connection layer 305 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Accordingly, an embodiment of the present invention further provides a semiconductor structure, with reference to fig. 6 and fig. 7, including:

a substrate 300, the substrate 300 having opposing first and second faces;

the plurality of connection layers 305 are located in the substrate 300, the surface of the connection layer 305 is exposed on the first surface of the substrate 300, the projection of the connection layer 305 on the first surface of the substrate 300 is a rectangle, the rectangle has a first side L1 and a second side S1 which are perpendicular to each other, and the first side L1 is larger than the second side S1.

In this embodiment, the substrate 300 includes a plurality of chip regions, a plurality of the connection layers 305 are distributed in an array in the chip regions, a first distance d1 is provided between adjacent connection layers 305 in a direction parallel to the first side L1, a second distance d2 is provided between adjacent connection layers 305 in a direction parallel to the second side S1, the first distance d1 is smaller than the second distance d2, and the first distance d1 is smaller than the size of the first side L1.

In this embodiment, the second distance d2 is equal to the first side L1, and the first distance d1 is equal to the second side S1.

In this embodiment, the length ratio of the first side L1 to the second side S1 is 7.

In this embodiment, the method further includes: a device layer within the substrate 300, the device layer comprising an isolation structure 302 and a device structure 303 within the isolation structure 302, the device structure 303 comprising a combination of one or more of a transistor, a diode, a transistor, a capacitor, an inductor, or a conductive structure; the connection layer 305 is located on the device layer, and the connection layer 305 is electrically connected to the device structure 303.

In this embodiment, the material of the connection layer 305 includes a metal including one or a combination of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Fig. 8 to 17 are schematic structural views illustrating a semiconductor structure forming process according to another embodiment of the present invention.

Referring to fig. 8 and 9, fig. 9 is a schematic cross-sectional view taken along a section line CC1 in fig. 8, and fig. 8 is a top view of fig. 9, providing a first substrate 400, where the first substrate 400 has a first side and a second side opposite to each other.

The first substrate 400 includes a plurality of first chip regions (not shown), and in this embodiment, the first substrate 400 further includes first scribe line regions (not shown) located between adjacent first chip regions.

With continued reference to fig. 8 and 9, a first device layer is formed within the first substrate 400, the first device layer including a first isolation structure 402 and a first device structure 403 within the first isolation structure 402, the first device structure 403 including one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure. In this embodiment, the first device structure 403 includes a transistor.

The material of the first isolation structure 402 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first isolation structure 402 includes silicon oxide.

With continued reference to fig. 8 and 9, a first dielectric layer 404 is formed over the first device layer.

The first dielectric layer 404 provides structural support for a subsequently formed first interconnect layer.

The material of the first dielectric layer 404 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the first dielectric layer 404 includes silicon oxide.

In this embodiment, the first substrate 400 includes a first base 401, a device layer located on the first base 401, and a first dielectric layer 404 located on the device layer.

In this embodiment, the material of the first substrate 401 is silicon.

In other embodiments, the material of the first substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multielement semiconductor material formed by III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

Referring to fig. 10 and 11, fig. 11 is a schematic cross-sectional view taken along a section line DD1 in fig. 10, fig. 10 is a top view of fig. 11, a plurality of first connection layers 405 are formed in the first substrate 400, a first surface of the first substrate 400 is exposed on a surface of the first connection layers 405, a projection of the first connection layers 405 on the first surface of the first substrate 400 is a rectangle, the rectangle has a first side L2 and a second side S2 perpendicular to each other, and the first side L2 is greater than the second side S2.

The projection of the first connection layer 405 on the first surface of the first substrate 400 is rectangular, the rectangle has a first side L2 and a second side S2 which are perpendicular to each other, and the first side L2 is larger than the second side S2, so that the surface area of the first connection layer 405 is distributed along the direction of the first side L2 on the premise that the first connection layer 405 meets the design rule, and thus the limit of offset when the first substrate and the second substrate are bonded subsequently is increased, that is, the first connection layer 405 and the second connection layer can be ensured to have a larger overlapping area only by ensuring that the surfaces of the first connection layer 405 and the second connection layer are overlapped in a cross manner, and the resistance value of the bonded device is ensured.

The first connection layer 405 is located on a first device layer, and the first connection layer 405 is electrically connected to the first device structure 403.

In this embodiment, a plurality of the first connection layers 405 are distributed in an array in the first chip region, a first distance d3 is provided between adjacent first connection layers 405 in a direction parallel to the first side L2, a second distance d4 is provided between adjacent first connection layers 405 in a direction parallel to the second side S2, the first distance d3 is smaller than the second distance d4, and the first distance d3 is smaller than the size of the first side L2.

The first connection layers 405 are distributed in an array in the first chip region, the first distance d1 is smaller than the second distance d2, and the first distance d1 is smaller than the size of the first edge L1. Therefore, the limitation that the first substrate and the second substrate can shift when being bonded subsequently is increased, and the requirement can be met only by ensuring that the surfaces of the first connecting layer 405 and the second connecting layer are crossed and overlapped and the first edge L2 and the third edge are perpendicular.

In this embodiment, the second distance d4 is equal to the first side L2, and the first distance d3 is equal to the second side S2. So as to meet the design requirement of the device size and save the chip area.

The length ratio of the first side L1 to the second side L2 is 7.

In this embodiment, the dimension of the first side L2 is 1.4a, the dimension of the second side S2 is 0.6a, the dimension of the second pitch d4 is 1.4a, the dimension of the first pitch d3 is 0.6a, and a is a length coefficient.

The forming method for forming the plurality of first connection layers 405 includes: forming openings (not shown) in the first dielectric layer 404; forming a layer of connecting material (not shown) within the opening and on the first dielectric layer 404; and flattening the connecting material layer until the surface of the first dielectric layer 404 is exposed, and forming the first connecting layer 405.

The material of the first connection layer 405 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Referring to fig. 12 and 13, fig. 13 is a schematic cross-sectional view taken along a cross-sectional line EE1 of fig. 12, and fig. 12 is a top view of fig. 13, providing a second substrate 500, wherein the second substrate 500 has a third side and a fourth side opposite to each other.

The second substrate 500 includes a plurality of second chip regions (not shown), and in this embodiment, the second substrate 500 further includes second scribe line regions (not shown) located between adjacent second chip regions.

With continued reference to fig. 12 and fig. 13, a second device layer is formed in the second substrate 500, where the second device layer includes a second isolation structure 502 and a second device structure 503 located in the second isolation structure 502, and the second device structure 503 includes a transistor, a diode, a transistor, a capacitor, an inductor, or a conductive structure. In this embodiment, the second device structure 503 includes a transistor.

The material of the second isolation structure 502 comprises a dielectric material comprising a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second isolation structure 502 includes silicon oxide.

With continued reference to fig. 12 and 13, a second dielectric layer 504 is formed over the first device layer.

The second dielectric layer 504 provides structural support for a subsequently formed second connection layer.

The material of the second dielectric layer 504 comprises a dielectric material comprising one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the material of the second dielectric layer 504 includes silicon oxide.

In this embodiment, the second substrate 500 includes a second base 501, a device layer located on the second base 501, and a second dielectric layer 504 located on the device layer.

In this embodiment, the material of the second substrate 501 is silicon.

In other embodiments, the material of the second substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the multicomponent semiconductor material of III-V group elements comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.

Referring to fig. 14 and 15, fig. 15 is a schematic cross-sectional view taken along a section line FF1 in fig. 14, fig. 14 is a top view of fig. 15, a plurality of second connection layers 505 are formed in the second substrate 500, a third surface of the second substrate 500 exposes a surface of the second connection layers 505, a projection of the second connection layers 505 on the surface of the second substrate 500 is a rectangle, the rectangle has a third side L3 and a fourth side S3 perpendicular to each other, and the third side L3 is larger than the fourth side S3.

The projection of the second connection layer 505 on the first surface of the second substrate 500 is a rectangle, the rectangle has a third edge L3 and a fourth edge S3 which are perpendicular to each other, and the third edge L3 is larger than the fourth edge S3, so that the second connection layer 505 distributes the surface area of the second connection layer 505 along the direction of the third edge L3 on the premise of meeting the design rule, thereby improving the boundary of excursion when the first substrate and the second substrate are bonded subsequently, i.e. only by ensuring that the surfaces of the first connection layer 405 and the second connection layer 505 are crossed and overlapped, the first connection layer 405 and the second connection layer 505 can be ensured to have a larger overlapping area, and the resistance value of the bonded device is ensured.

The second connection layer 505 is located on a second device layer, and the second connection layer 505 is electrically connected to the second device structure 503.

In this embodiment, the first side L2 and the third side L3 have the same length, and the second side S2 and the fourth side S3 have the same length.

The first side L2 and the third side L3 have the same length, and the second side S2 and the fourth side S3 have the same length, so that the projected pattern of the first connection layer 405 and the projected pattern of the second connection layer 505 have the same circumference and area. This makes the planarization process more uniform when forming the connection layer having the same size as the first connection layer 405 and the second connection layer 505, and the surface smoothness of the formed connection layer, when subsequently bonding the first substrate 400 and the second substrate 500, the first substrate 400 and the second substrate 500 can be tightly bonded, and the bonding yield is improved.

In this embodiment, a plurality of the second connection layers 505 are distributed in an array in the second chip region, a third distance d5 is provided between adjacent second connection layers 505 in a direction parallel to the third side L3, a fourth distance d6 is provided between adjacent second connection layers 505 in a direction parallel to the fourth side S3, the third distance d5 is smaller than the fourth distance d6, and the third distance d5 is smaller than the size of the third side L3.

A plurality of the second connection layers 505 are distributed in an array in the second chip region, the third distance d5 is smaller than the fourth distance d6, and the third distance d5 is smaller than the size of the third side L3. Therefore, the limitation of offset during the subsequent bonding of the first substrate 400 and the second substrate 500 is increased, and the requirement can be met only by ensuring that the surfaces of the first connecting layer 405 and the second connecting layer 505 are crossed and overlapped and the first side L2 and the third side L3 are perpendicular.

In this embodiment, the third distance d5 is equal to the fourth side S3, and the fourth distance d6 is equal to the third side L3. So as to meet the design requirement of the size of the device and save the area of the chip.

The length ratio of the third side L3 to the fourth side S3 is 7.

In this embodiment, the third side L3 has a dimension of 1.4a, the fourth side S3 has a dimension of 0.6a, the fourth distance d6 has a dimension of 1.4a, the third distance d5 has a dimension of 0.6a, and a is a length coefficient.

The forming method for forming the plurality of second connection layers 505 includes: forming openings (not shown) in the second dielectric layer 504; forming a layer of connecting material (not shown) within the opening and on the second dielectric layer 504; and flattening the connecting material layer until the surface of the second dielectric layer 504 is exposed, and forming the second connecting layer 505.

The material of the second connection layer 505 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Referring to fig. 16 and 17, fig. 17 is a schematic cross-sectional structure view along a section line GG1 in fig. 16, fig. 16 is a top view of fig. 17 showing only the first connection layer 405, the first surface of the first substrate 400 is bonded to the third surface of the second substrate 500, a plurality of the first connection layers 405 and a plurality of the second connection layers 505 are in one-to-one correspondence, the surfaces of the corresponding first connection layers 405 and the second connection layers 505 are overlapped, and the first side L2 is perpendicular to the third side L3.

The third surface of the second substrate 500 is bonded to the first surface of the first substrate 400, the plurality of first connection layers 405 and the plurality of second connection layers 505 correspond to each other one by one, the surfaces of the corresponding first connection layers 405 and the surfaces of the corresponding second connection layers 505 are overlapped, and the first side L2 is perpendicular to the third side L3. When the first surface of the first substrate 400 is bonded to the third surface of the second substrate 500, on one hand, the bonding area of the first connection layer 405 and the second connection layer 505 can be ensured, so that the resistance value of the device is ensured; on the other hand, the limitation of the offset when bonding the first surface of the first substrate 400 and the third surface of the second substrate 500 is increased, that is, only by ensuring that the surface of the first connection layer 405 and the surface of the second connection layer 505 are overlapped and crossed, and the first side L2 is perpendicular to the third side L3, the requirement can be satisfied. Thereby improving the production yield.

In the embodiment, the surface of each first connection layer 405 and the surface of one second connection layer 505 coincide to form an overlap region, and the areas of the overlap regions are the same. Therefore, the resistance value of the bonded first substrate 400 and the bonded second substrate 500 is stable, and the contact resistance uniformity of the first connection layer 405 and the second connection layer 505 is good.

In the present embodiment, the first side L2 and the third side L3 have a size of 1.4a, the second side S2 and the fourth side S3 have a size of 0.6a, and a is a length coefficient. When the first surface of the first substrate 400 is bonded to the third surface of the second substrate 500 based on the coincidence of the center of the first connection layer 405 and the center of the second connection layer 505, the offset range of the first connection layer 405 and the second connection layer 505 in the extending direction of the first edge is as follows: -1.4 a-0.6 a)/2 to + 1.4a-0.6 a)/2, the offset range of the first connection layer 400 and the second connection layer 500 in the extension direction of the third side L3 is: (-1.4 a-0.6 a)/2 to (-1.4 a-0.6 a)/2. The offset range when the first surface of the first substrate 400 is bonded to the third surface of the second substrate 500 is increased, and the yield is improved.

Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 16 and 17, including:

a first substrate 400, wherein the first substrate 400 has a first surface and a second surface opposite to each other, the first substrate 400 has a plurality of first connection layers 405 therein, the first surface of the first substrate 400 exposes the surface of the first connection layers 405, a projection of the first connection layers 405 on the first surface of the first substrate 400 is a rectangle, the rectangle has a first side L2 and a second side S2 perpendicular to each other, and the first side L2 is larger than the second side S2;

with second substrate 500 of first substrate 400 bonding, second substrate 500 has relative third face and fourth face, second substrate 500 third face and the first face bonding of first substrate 400, a plurality of second articulamentum 505 have in the second substrate 500, second substrate 500 third face exposes second articulamentum 505 surface, second articulamentum 505 is the rectangle in the projection on second substrate 500 surface, the rectangle has mutually perpendicular' S third limit L3 and fourth limit S3, and third limit L3 is greater than fourth limit S3, and is a plurality of first articulamentum 405 and a plurality of second articulamentum 505 one-to-one, the first articulamentum 405 surface and the coincidence of second articulamentum 505 surface that correspond, just first limit L2 is perpendicular with third limit L3.

In the embodiment, the surface of each first connection layer 405 and the surface of one second connection layer 505 coincide to form an overlap region, and the areas of the overlap regions are the same.

In this embodiment, the first substrate 400 includes a plurality of first chip regions, a plurality of first connection layers 405 are distributed in an array in the first chip regions, a first distance d3 is provided between adjacent first connection layers 405 in a direction parallel to the first side L2, a second distance d4 is provided between adjacent first connection layers 405 in a direction parallel to the second side S2, the first distance d3 is smaller than the second distance d4, and the first distance d3 is smaller than the size of the first side L2.

In this embodiment, the second distance d4 is equal to the first side L2, and the first distance d3 is equal to the second side S2.

In this embodiment, the second substrate 500 includes a plurality of second chip regions, the plurality of second connection layers 505 are distributed in an array in the second chip regions, a third distance d5 is provided between adjacent second connection layers 505 in a direction parallel to the third side L3, a fourth distance d6 is provided between adjacent second connection layers 505 in a direction parallel to the fourth side S3, the third distance d5 is smaller than the fourth distance d6, and the third distance d5 is smaller than the size of the third side L3.

In this embodiment, the third distance d5 is equal to the fourth side S3, and the fourth distance d6 is equal to the third side L3.

In this embodiment, the length ratio of the first side L2 to the second side S2 is 7.

In this embodiment, the method further includes: a first device layer located within the first substrate 400, the first device layer comprising a first isolation structure 402 and a first device structure 403 located within the first isolation structure 402, the first device structure 403 comprising one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure; the first connection layer 405 is located on a first device layer, and the first connection layer 405 is electrically connected to the first device structure 403.

In this embodiment, the method further includes: a second device layer located within the second substrate 500, the second device layer comprising a second isolation structure 502 and a second device structure 503 located within the second isolation structure 502, the second device structure 503 comprising one or more of a transistor, a diode, a transistor, a capacitor, an inductor, and a conductive structure; the second connection layer 505 is located on a second device layer, and the second connection layer 505 is electrically connected to the second device structure 503.

In this embodiment, the material of the first connection layer 405 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the material of the second connection layer 505 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate having opposing first and second sides;

the substrate comprises a plurality of connecting layers positioned in the substrate, wherein the first surface of the substrate is exposed out of the surface of the connecting layer, the projection of the connecting layer on the first surface of the substrate is rectangular, the rectangle is provided with a first edge and a second edge which are perpendicular to each other, the first edge is larger than the second edge, a first distance is formed between the adjacent connecting layers in the direction parallel to the first edge, a second distance is formed between the adjacent connecting layers in the direction parallel to the second edge, the first distance is smaller than the second distance, and the first distance is smaller than the size of the first edge.

2. The semiconductor structure of claim 1, wherein the substrate comprises a plurality of chip regions, and wherein a plurality of the connection layers are arranged in an array within the chip regions.

3. The semiconductor structure of claim 2, wherein the second pitch has a size equal to the first side and the first pitch has a size equal to the second side.

4. The semiconductor structure of claim 1, wherein the ratio of the lengths of the first side and the second side is 7.

5. The semiconductor structure of claim 1, further comprising: a device layer located within the substrate, the device layer including an isolation structure and a device structure located within the isolation structure, the device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the connection layer is on the device layer and is electrically connected to the device structure.

6. The semiconductor structure of claim 1, wherein a material of the connection layer comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

7. A semiconductor structure, comprising:

the first substrate is provided with a first surface and a second surface which are opposite, a plurality of first connecting layers are arranged in the first substrate, the first surface of the first substrate is exposed out of the surface of the first connecting layers, the projection of the first connecting layers on the first surface of the first substrate is in a rectangle shape, the rectangle is provided with a first side and a second side which are vertical to each other, the first side is larger than the second side, a first interval is arranged between the adjacent first connecting layers in the direction parallel to the first side, a second interval is arranged between the adjacent first connecting layers in the direction parallel to the second side, the first interval is smaller than the second interval, and the first interval is smaller than the size of the first side;

with the second substrate of first substrate bonding, the second substrate has relative third face and fourth face, the first face bonding of second substrate third face and first substrate, a plurality of second articulamentum has in the second substrate, second substrate third face exposes second articulamentum surface, the projection of second articulamentum on the second substrate surface is the rectangle, the rectangle has mutually perpendicular's third side and fourth side, and the third side is greater than the fourth side, and is a plurality of first articulamentum and a plurality of second articulamentum one-to-one, the coincidence of corresponding first articulamentum surface and second articulamentum surface, just first side and third side are perpendicular, be on a parallel with between the adjacent second articulamentum have the third interval in the third side, be on a parallel with between the adjacent second articulamentum have the fourth interval in the fourth side direction, the third interval is less than the fourth interval, just the third interval is less than the size of third side.

8. The semiconductor structure of claim 7, wherein each first connection layer surface coincides with a second connection layer surface to form an overlap region, and the areas of the overlap regions are the same.

9. The semiconductor structure of claim 8, wherein the first side and the third side are the same length, and the second side and the fourth side are the same length.

10. The semiconductor structure of claim 9, wherein the first substrate comprises a plurality of first chip regions, and a plurality of the first connection layers are arranged in an array in the first chip regions.

11. The semiconductor structure of claim 10, wherein the second pitch has a size equal to the first side and the first pitch has a size equal to the second side.

12. The semiconductor structure of claim 10, wherein the second substrate comprises a plurality of second chip regions, and wherein a plurality of the second connection layers are arranged in an array in the second chip regions.

13. The semiconductor structure of claim 12, wherein the third pitch is equal in size to the fourth side and the fourth pitch is equal in size to the third side.

14. The semiconductor structure of claim 9, wherein the ratio of the lengths of the first side and the second side is 7.

15. The semiconductor structure of claim 7, further comprising: a first device layer located within a first substrate, the first device layer including a first isolation structure and a first device structure located within the first isolation structure, the first device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the first connection layer is on a first device layer, and the first connection layer is electrically connected to the first device structure.

16. The semiconductor structure of claim 7, further comprising: a second device layer located within a second substrate, the second device layer including a second isolation structure and a second device structure located within the second isolation structure, the second device structure including one or more of a transistor, a diode, a triode, a capacitor, an inductor, and a conductive structure; the second connection layer is on a second device layer, and the second connection layer is electrically connected to the second device structure.

17. The semiconductor structure of claim 7, wherein a material of the first connection layer comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the material of the second connection layer comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum.

18. A method of forming a semiconductor structure, comprising:

providing a substrate having first and second opposing faces;

the method comprises the steps of forming a plurality of connecting layers in a substrate, wherein the first surface of the substrate is exposed out of the surfaces of the connecting layers, the projection of each connecting layer on the first surface of the substrate is rectangular, the rectangle is provided with a first edge and a second edge which are perpendicular to each other, the first edge is larger than the second edge, a first distance is formed between every two adjacent connecting layers in the direction parallel to the first edge, a second distance is formed between every two adjacent connecting layers in the direction parallel to the second edge, the first distance is smaller than the second distance, and the first distance is smaller than the size of the first edge.

19. The method of forming a semiconductor structure of claim 18, wherein the substrate comprises a plurality of chip regions, and wherein a plurality of the connection layers are arranged in an array within a chip region.

20. The method of claim 19, wherein the second pitch has a size equal to the first side and the first pitch has a size equal to the second side.

21. The method of forming a semiconductor structure according to claim 18, wherein the ratio of the lengths of the first side and the second side is 7.

22. A method of forming a semiconductor structure, comprising:

providing a first substrate, wherein the first substrate is provided with a first surface and a second surface which are opposite, a plurality of first connecting layers are arranged in the first substrate, the first surface of the first substrate is exposed out of the surface of the first connecting layers, the projection of the first connecting layers on the first surface of the first substrate is in a rectangle shape, the rectangle shape is provided with a first side and a second side which are perpendicular to each other, the first side is larger than the second side, a first distance is formed between the adjacent first connecting layers in the direction parallel to the first side, a second distance is formed between the adjacent first connecting layers in the direction parallel to the second side, the first distance is smaller than the second distance, and the first distance is smaller than the size of the first side;

providing a second substrate, wherein the second substrate is provided with a third face and a fourth face which are opposite, a plurality of second connecting layers are arranged in the second substrate, the third face of the second substrate is exposed out of the surface of the second connecting layer, the projection of the second connecting layers on the surface of the second substrate is in a rectangle shape, the rectangle is provided with a third face and a fourth face which are perpendicular to each other, the third face is larger than the fourth face, a third distance is formed between every two adjacent second connecting layers in a direction parallel to the third face, a fourth distance is formed between every two adjacent second connecting layers in a direction parallel to the fourth face, the third distance is smaller than the fourth distance, and the third distance is smaller than the size of the third face;

and bonding the first surface of the first substrate with the third surface of the second substrate, wherein the first connecting layers correspond to the second connecting layers one by one, the surfaces of the corresponding first connecting layers coincide with the surfaces of the second connecting layers, and the first edge is perpendicular to the third edge.

23. The method of claim 22, wherein each of the first interconnect layer surfaces overlaps a second interconnect layer surface to form an overlap region, and wherein the overlap regions have the same area.

24. The method of forming a semiconductor structure of claim 22, wherein the first side and the third side are the same length, and the second side and the fourth side are the same length.

25. The method of forming a semiconductor structure of claim 22, wherein the first substrate comprises a plurality of first chip regions, and a plurality of the first connection layers are arranged in an array in the first chip regions.

26. The method of forming a semiconductor structure of claim 25, wherein the second pitch is equal in size to the first side and the first pitch is equal in size to the second side.

27. The method of forming a semiconductor structure of claim 25, wherein the second substrate includes a plurality of second die regions, and wherein a plurality of the second connection layers are arranged in an array in the second die regions.

28. The method of claim 27, wherein the third pitch is equal in size to the fourth pitch and the fourth pitch is equal in size to the third pitch.

29. The method of forming a semiconductor structure according to claim 25, wherein a ratio of lengths of the first side and the second side is 7.

30. The method for forming a semiconductor structure according to claim 29, wherein the first side and the third side have a size of 1.4a, the second side and the fourth side have a size of 0.6a, and a is a length factor; when the first surface of the first substrate and the third surface of the second substrate are bonded by taking the coincidence of the center of the first connecting layer and the center of the second connecting layer as a reference, the offset range of the first connecting layer and the second connecting layer in the extending direction of the first edge is as follows: -1.4 a-0.6 a)/2 to + 1.4a-0.6 a)/2, the offset range of the first connection layer and the second connection layer in the third extending direction is: (-1.4 a-0.6 a)/2 to (-1.4 a-0.6 a)/2.