CN113314175B

CN113314175B - Write auxiliary device, working method thereof and memory

Info

Publication number: CN113314175B
Application number: CN202110574056.8A
Authority: CN
Inventors: 孙燃; 姚其爽; 魏依苒
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-05-25
Filing date: 2021-05-25
Publication date: 2023-11-21
Anticipated expiration: 2041-05-25
Also published as: CN113314175A

Abstract

The embodiment of the invention discloses a write-assist device, a working method thereof and a memory, which relate to the technical field of computers and can effectively improve write-assist efficiency and suitability. The device comprises: a voltage identification part, one end of which is connected with the monitored voltage, and the other end of which is connected with an auxiliary voltage generation part, and is used for identifying the voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; and one end of the auxiliary voltage generating part is connected with the voltage identification part, and the other end of the auxiliary voltage generating part is connected with the write data transmission part, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write the data to be written into the target position. The method and the device are suitable for memory write operation.

Description

Write auxiliary device, working method thereof and memory

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a write assist apparatus, a working method thereof, and a memory.

Background

Low power consumption is an important issue in present day integrated circuit designs, and for chips, both dynamic power consumption and static power consumption are directly related to power supply voltage, so reducing power supply voltage is one of the effective ways to achieve low power consumption.

However, for many circuits, a reduction in supply voltage, while reducing power consumption, may also adversely affect circuit performance. For example, in an SRAM (Static Random Access Memory ) memory circuit, an SRAM memory cell array is provided in the SRAM memory circuit. The SRAM memory cell array is composed of several memory cells bitcell, each of which can be used to store one bit binary 0 or 1. The reduction of the power supply voltage can save the working power consumption of bitcells, but also can lead to the reduction of the gate-source voltage difference of a transistor (also called a transmission tube) for transmitting the written data during the writing operation, and the writing current is reduced, so that the writing time can be prolonged, and even the writing failure can occur. For this reason, write assist techniques have been developed.

The write assist technique may be implemented in various ways, for example, a negative impact voltage may be applied to a bit select line of a memory cell during a write operation, so as to reduce a source voltage of a transmission tube, so as to increase a gate-source voltage difference of the transmission tube, increase a write current, and increase a write success rate; or, during the writing operation, a forward impulse voltage is applied to the word line of the memory cell, so that the gate voltage of the transmission tube is increased, the gate-source voltage difference of the transmission tube is further increased, the writing current is increased, and the writing success rate is improved. However, for a large number of chips produced, process variations often occur from chip to chip, and in particular which voltage of which chip requires a large surge voltage, a large number of tests must be performed, and the test results burned into the fuse array of the chip. In this way, on the one hand, the determination of the surge voltage is very inefficient, and on the other hand, the write-assisted on surge voltage cannot be adapted to different voltage scenarios, since a fixed value is burned into the fuse array.

Aiming at the problems of low efficiency and poor suitability of the write-assisted starting impulse voltage, no effective solution exists in the related art.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a write assist device, a working method thereof, and a memory, which can effectively improve write assist efficiency and adaptability.

In a first aspect, an embodiment of the present invention provides a write assist apparatus, including: a voltage identification part, one end of which is connected with the monitored voltage, and the other end of which is connected with an auxiliary voltage generation part, and is used for identifying the voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; and one end of the auxiliary voltage generating part is connected with the voltage identification part, and the other end of the auxiliary voltage generating part is connected with the write data transmission part, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write the data to be written into the target position.

Optionally, the voltage identifying part includes: the input end of the voltage dividing module is connected with the monitored voltage, the output end of the voltage dividing module comprises at least one output channel, the output voltage of each output channel is respectively a divided voltage of the monitored voltage, and the output voltages of the output channels are mutually unequal; the identification module is connected with the voltage division module and is used for identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel of the voltage division module and the preset threshold value to obtain a target voltage interval.

Optionally, the identification module is specifically configured to: comparing the output voltage of each output channel of the voltage dividing module with the preset threshold according to a preset sequence; and discarding the comparison operation of the subsequent output channels under the condition that the output voltage of one of the output channels is determined to be larger than the preset threshold value.

Optionally, the preset sequence is a sequence from low to high of the output voltage.

Optionally, the auxiliary voltage generating part includes: the decoding module is connected with the voltage identification part and used for gating an auxiliary channel required by generating the auxiliary voltage according to the target voltage interval identified by the voltage identification part; and the generation module is connected with the decoding module and is used for generating the auxiliary voltage through the auxiliary channel gated by the decoding module.

Optionally, the decoding module is specifically configured to: respectively establishing coding-gating corresponding relation for each target voltage interval and the corresponding auxiliary channels, wherein each target voltage interval corresponds to 0 gating, one or more auxiliary channels; and gating an auxiliary channel required by generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, the decoding module includes a first logic gate; the generating module comprises at least one auxiliary channel, and each auxiliary channel comprises a second logic gate and a capacitor connected in series with the second logic gate.

Optionally, the write assist apparatus further includes: and a latch unit having one end connected to the voltage identification unit and the other end connected to the auxiliary voltage generation unit, for latching the target voltage range identified by the voltage identification unit.

Optionally, the voltage identifying part is further configured to close the dc path according to the identified target voltage interval.

Optionally, the monitored voltage includes at least one of: a first power supply voltage for providing a write strobe signal for the write data transfer section; a first node voltage having a preset logic level under a preset condition.

Optionally, the auxiliary voltage comprises a surge voltage.

Optionally, the target location includes at least one of: target register, target storage unit, target port.

Optionally, the write data transmission part is provided with a write strobe end, a data input end and a data output end; the data output end is connected with the target position; the auxiliary voltage generating part is connected with the data input end and is used for generating a first auxiliary voltage according to the target voltage interval identified by the voltage identifying part and applying the first auxiliary voltage to the data input end, wherein the polarity of the first auxiliary voltage is opposite to that of the voltage of the writing strobe end; and/or the auxiliary voltage generating part is connected with the writing strobe terminal and is used for generating a second auxiliary voltage according to the target voltage interval identified by the voltage identifying part and applying the second auxiliary voltage to the writing strobe terminal, wherein the polarity of the second auxiliary voltage is the same as that of the writing strobe terminal.

In a second aspect, an embodiment of the present invention further provides a method for operating a write assist apparatus, including: identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; generating auxiliary voltage according to the target voltage interval so as to write the data to be written into the target position under the assistance of the auxiliary voltage.

Optionally, identifying, from a preset voltage interval set, a voltage interval in which the monitored voltage is located, and obtaining the target voltage interval includes: dividing the monitored voltage and then passing through at least one output channel, wherein the output voltage of each output channel is respectively one divided voltage of the monitored voltage, and the output voltages of the output channels are mutually unequal; and identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel and the preset threshold value, and obtaining a target voltage interval.

Optionally, the identifying, from the preset voltage interval set, a voltage interval in which the monitored voltage is located according to a relationship between the output voltage of each output channel and a preset threshold value includes: comparing the output voltage of each output channel with the preset threshold value according to a preset sequence; and discarding the comparison operation of the subsequent output channels under the condition that the output voltage of one of the output channels is determined to be larger than the preset threshold value.

Optionally, the generating the auxiliary voltage according to the target voltage interval includes: according to the target voltage interval, gating an auxiliary channel required by generating the auxiliary voltage; the auxiliary voltage is generated through the auxiliary channel.

Optionally, the gating the auxiliary channel required for generating the auxiliary voltage according to the target voltage interval includes: respectively establishing coding-gating corresponding relation for each target voltage interval and the corresponding auxiliary channels, wherein each target voltage interval corresponds to 0 gating, one or more auxiliary channels; and gating an auxiliary channel required by generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, after the voltage interval in which the monitored voltage is located is identified from the preset voltage interval set, and the target voltage interval is obtained, before the auxiliary voltage is generated according to the target voltage interval, the method further includes: latching the target voltage interval.

Optionally, after the voltage interval in which the monitored voltage is located is identified from the preset voltage interval set to obtain the target voltage interval, the method further includes: and stopping the identification of the monitored voltage according to the identified target voltage interval.

In a third aspect, embodiments of the present invention further provide a memory in which any of the write assist devices provided by the embodiments of the present invention is disposed.

The write auxiliary device, the working method thereof and the memory provided by the embodiment of the invention can monitor the monitored voltage in real time, identify the voltage interval where the monitored voltage is located from the preset voltage interval set, obtain the target voltage interval, generate auxiliary voltage according to the target voltage interval, and apply the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write the data to be written into the target position. Therefore, the proper auxiliary voltage required by the writing auxiliary device during data writing operation can be timely determined according to the actual size of the monitored voltage in the actual work of the circuit, and the auxiliary voltage is timely generated, so that complex testing operation is not required, and the method is applicable to various scenes, and therefore the writing auxiliary efficiency and the suitability are effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic circuit diagram of a bit line negative pressure write assist technique in accordance with an embodiment of the present invention;

FIG. 2 is a timing diagram of writing data corresponding to the circuit shown in FIG. 1 according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a write assist apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another embodiment of a write assist apparatus;

FIG. 5 is a schematic diagram of a write assist apparatus according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a first logic gate in a write assist device according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a second logic gate in a write assist device according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of still another embodiment of a write assist apparatus according to the present invention;

FIG. 9 is a schematic diagram showing a latch structure of a write assist device according to an embodiment of the present invention;

FIG. 10 is a schematic diagram showing a connection relationship between an auxiliary voltage generating portion and a write data transmitting portion in a write auxiliary device according to an embodiment of the present invention;

FIG. 11 is a schematic diagram showing a detailed structure of a write assist apparatus according to an embodiment of the present invention;

FIG. 12 is a state transition diagram illustrating the circuit behavior of the write assist device of the embodiment of FIG. 11;

FIG. 13 is a schematic diagram showing a structure of the voltage divider circuit in the voltage identification state of FIG. 12;

FIG. 14 is a schematic diagram of a circuit structure for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 15 is a schematic diagram of another circuit structure for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 16 is a schematic diagram of a circuit structure for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 17 is a schematic diagram of still another circuit configuration for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 18 is a schematic diagram of a circuit structure for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 19 is a schematic diagram of a circuit configuration of the DC-DC converter of FIG. 12;

FIG. 20 is a flowchart of a method of operating a write assist device according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As described in the background, for many circuits, a reduction in power supply voltage may reduce power consumption, but may also adversely affect circuit performance, thus creating a write assist technique. Aiming at the problems of low efficiency and poor suitability of the write-assist starting surge voltage in the related art, the embodiment of the invention provides a write-assist device.

In order to facilitate understanding of the present invention, a brief description will be given of a write operation, taking an SRAM memory as an example.

FIG. 1 is a schematic diagram of a bit line negative voltage (NegBL) write assist technique, wherein each SRAM bitcell includes two inverters with their inputs and outputs connected back to back, the PMOS (P-Metal Oxide Semi-conductor Field Effect Transistor, P-type Metal Oxide field Effect transistor) of each inverter is referred to as the pull-up tube MPU of the bitcell, the NMOS of the inverter is referred to as the pull-down tube MPD of the bitcell, and the NMOS gated by the Word Line (WL) is referred to as the transmission tubes PGT, PGC. In the figure, the "@" symbol after a word line WL indicates that the voltage domain of the word line WL is VDDM (the supply voltage source of the word line WL is VDDM). The circuit part where C1/C2/C3 is located is a write assist circuit. The power supply voltage of the write assist circuit may be the same as or different from WL. C1/C2/C3 is a capacitive element, WA1/WA2/WA3 can generate different cc1/cc2/cc3 signals through different combinations of logic values, and generate negative pressure shocks at the falling edges of cc1/cc2/cc3 respectively. The C1/C2/C3 capacitor may be composed of MOS capacitor or line-to-line coupling capacitor. NMOS PDWR is a negative pressure pull-down tube, is gated by a signal WA_ENX, is turned on when negative pressure is not required to be generated, enables BL lowest pull-down voltage to be 0v, is turned off when negative pressure is required to be generated, floats VSS_WA, and uses the characteristic that differential pressure between two ends of a capacitor is not abrupt, and uses a capacitor C1/C2/C3 to perform negative pressure impact on the VSS_WA.

The operation of the write assist will be briefly described. When a write operation to bitcell is required, the case of writing and storing the same value and different values may be considered. When the same value is written, supposing that bitcell stores 0, preparing to write 0 (namely wrdata=0), BLT is ready to write the value 0 at this time, BLC is 1, PGT and PGC of the transmission tube are started, logic 0 prepared in advance on a bit line BLT is the same as bitcell QT logic 0, BLC is prepared in advance in 1 is the same as bitcell QC logic 1, the value of bitcell cannot be rewritten, and after PGT and PGC of the transmission tube are closed, bitcell enters a holding state; when the writing value is opposite to the bitcell storing value, for example, bitcell stores 1, at this time, 0 is ready to be written (i.e. wrdata=0), BLT is ready for logic 0, BLC is 1, when the transmission tubes PGT and PGC are opened, the bit line BLT pulls down QT 1 to 0 through the transmission tube PGT, the opposite pull-up tube PUC is opened, QC is pulled up to logic 1, after the subsequent transmission tubes PGT and PGC are closed, bitcell enters the holding state, and the bit lines BLT and BLC are recharged back to logic 1 through PCHT and PCHC, so as to complete the writing operation.

Since the write value is opposite to the bitcell storage value, after the supply voltage VDDM of the bitcell drops, if the write assist is not turned on, the write may not be successful. Specifically, as shown in fig. 2, when the power supply voltage VDDM of bitcell is reduced, the word line WL voltage is reduced, and the write assist is not turned on in the first write cycle. After the signal becomes 1 to turn on WPGT and WPGC, BLT is reduced to 0 level, WL becomes 1 to turn on PGT and PGC, QT is gradually pulled down to a certain intermediate voltage, but the intermediate voltage does not reach the voltage value of bitcell inversion, the opposite QC point does not rise to 1, and writing fails. The second writing period is the same as the first writing period, when the negative pressure enables WA_ENX to become 0, the situation that QT and QC can be seen is the same as the first writing period, writing cannot be performed until WA_ENX becomes 0, the ground signals VSS_WA of BLT and BLC writing driving inverters X1 and X2 float, meanwhile, the signal cc1/cc2/cc3 is changed from 1 to 0 through the combination of WA1/WA2/WA3, the voltage at two ends of a capacitor is not suddenly changed, one end of the capacitor C1/C2/C3 is connected with VSS_WA and is coupled with the negative pressure from the initial 0, the negative pressure is transmitted to the BLT, the gate-source voltage difference of a transmission tube PGT of the bitcell is increased, the current of the transmission tube is increased, the voltage of the QT point is pulled down, and the overturn point of the bitcell is reached, and writing is successful.

WA [3:1] is a control port for negative pressure impact opening. In an integrated circuit, the working condition of the circuit is complex and changeable, and the specific requirement of the circuit on the opening of negative pressure impact and the requirement of the opening of the circuit on the opening of the circuit can be determined by WA [3:1 ]. When WA [3:1] is 1, no negative pressure is generated; when one bit in WA [3:1] is 0 and the other bit is 1, starting negative pressure generated by the corresponding capacitor; when two bits in WA [3:1] are 0 and one bit is 1, the negative pressure of the combination of the two capacitors is started; when WA [3:1] three bits are all 0, three capacitor combinations are started to generate negative pressure with the largest amplitude.

In order to effectively improve the efficiency of starting the write auxiliary voltage and enable the write auxiliary voltage to adapt to various application scenes, the embodiment of the invention provides the write auxiliary device, which can timely determine the proper auxiliary voltage required by the write auxiliary device when data writing operation is performed according to the actual working condition of a circuit and timely generate the auxiliary voltage, so that complex test operation is not needed, and the write auxiliary device can be suitable for various scenes, thereby effectively improving the write auxiliary efficiency and the suitability. The following is a detailed description of specific examples. It should be noted that, the write assist device provided in the embodiment of the present invention may be applied not only in SRAM, but also in other situations where write operation is required.

As shown in fig. 3, an embodiment of the present invention provides a write assist apparatus, which may include:

a voltage identification part 1, one end of which is connected with the monitored voltage Vdect, and the other end of which is connected with an auxiliary voltage generation part 2, for identifying a voltage section where the monitored voltage Vdect is located from a preset voltage section set, so as to obtain a target voltage section Vob;

an auxiliary voltage generating section 2 having one end connected to the voltage identifying section 1 and the other end connected to the write data transmitting section 3, for generating an auxiliary voltage Vass based on the target voltage section Vob, and applying the auxiliary voltage Vass to the write data transmitting section 3 to assist the write data transmitting section 3 to write data datawrite to be written to the target location Pob.

In the write assist device provided by the embodiment of the invention, the voltage identification part 1 can monitor the monitored voltage Vdect in real time, identify the voltage section where the monitored voltage Vdect is located from the preset voltage section set, obtain the target voltage section Vob, and the assist voltage generation part 2 can generate the assist voltage Vass according to the target voltage section Vob, and apply the assist voltage Vass to the write data transmission part 3 so as to assist the write data transmission part 3 to write the data to be written into the target position Pob. Therefore, the proper auxiliary voltage Vass required by the writing auxiliary device during data writing operation can be timely determined according to the actual size of the monitored voltage Vdect in the actual operation of the circuit, and the auxiliary voltage Vass is timely generated, so that complex testing operation is not needed, the method is applicable to various scenes, and the writing auxiliary efficiency and the suitability are effectively improved.

Alternatively, the monitored voltage Vdect may be any voltage signal that can directly or indirectly reflect the difficulty level of the writing operation. For example, in one embodiment of the invention, the monitored voltage Vdect may include one or more of the following: a first power supply voltage for providing a write strobe signal for the write data transfer section; a first node voltage having a preset logic level under a preset condition.

It will be appreciated that the performance of the chip may vary from one PVT (process voltage temperature, process voltage temperature angle) to another, and therefore, the performance of different chips may vary. Meanwhile, the running speed of the chip and the consumption of resources can also change due to the distribution of the business and the calculated amount carried by the chip. Therefore, the output voltage of each power supply supplying power to the chip may also vary. For example, when the chip performs a large number of operations and is complex, the voltage consumption consumed by each operation module is relatively large, resulting in a lower output voltage of the power supply. And if the power supply is exactly the power supply that supplies the write strobe signal to the write data transfer section 3, the difficulty of the write operation may be increased.

Furthermore, when the output voltage of the power supply is low, the node voltages of some special nodes in the circuit can be influenced, and when the power supply output voltage is inconvenient to monitor, the voltages of the special nodes can be monitored, so long as the voltage fluctuation range of the nodes under the preset condition is known in advance. For example, a node voltage has a preset logic level 1 under a preset condition, and the corresponding voltage should be 1.1V or more, but the voltage of the node under the preset condition is 0.9V due to the change of the power supply voltage, so that the writing operation may be in a difficult state. In this way, the write assist device provided by the embodiment of the invention can timely and accurately grasp whether the write operation is difficult or not and the difficulty degree through monitoring the power supply voltage and the node voltage, thereby providing proper write assist for the write assist device so as to enable the write operation to be completed smoothly.

The specific structure of the voltage identifying section 1 may be varied. Specifically, as shown in fig. 4, in one embodiment of the present invention, the voltage identifying section 1 may specifically include:

the voltage dividing module 11, the input end is connected with the monitored voltage Vdect, the output end includes at least one output channel, the output voltage Vn of each output channel is a divided voltage of the monitored voltage Vdect, where n is a positive integer, and the output voltages Vn (e.g. V1, V2 … …) of each output channel are different from each other;

The identifying module 12 is connected to the voltage dividing module 11, and is configured to identify a voltage interval in which the monitored voltage Vdect is located from a preset voltage interval set according to a relationship between the output voltage Vn of each output channel of the voltage dividing module 11 and a preset threshold value, so as to obtain a target voltage interval Vob.

The output voltage Vn of each output channel may divide the monitored voltage Vdect in various manners. For example, in one embodiment of the present invention, a plurality of voltage dividing elements may be connected in series between the monitored voltage Vdect and the ground signal, and the output voltages may be taken from the different voltage dividing elements, respectively. Alternatively, the voltage dividing element may be one or more of the following: resistor, diode, triode, MOS tube, etc. For example, in one embodiment of the present invention, 3 resistors with equal resistance values are connected in series between the monitored voltage Vdect and the ground signal, so that two output channels can be formed, and the output voltages of the two output channels are Vdect/3 and 2Vdect/3 respectively. Thus, the tracking of the process, voltage, temperature and the like can be realized in the form of partial pressure through a device for tracking the change of the process parameters through the diffusion resistance.

Alternatively, in another embodiment of the present invention, a plurality of different paths may be provided in parallel between the monitored voltage Vdect and the ground signal, wherein each path corresponds to one output channel and one output voltage. After the monitored voltage Vdect is divided by the voltage dividing module 11, different output voltages of each output channel can be obtained, and the different output voltages are respectively compared with a preset threshold value, so that a voltage interval where the monitored voltage Vdect is located can be determined, and a target voltage interval Vob is obtained. The preset threshold value can be realized in various manners on the circuit, such as a starting voltage of an MOS tube, a conducting voltage of a diode, and the preset threshold value realized by various clamping measures, voltage stabilizing measures and the like.

For example, in one embodiment of the present invention, the predetermined set of voltage intervals is { [0.3, 0.6), [0.6V, 0.8V), [0.8V, 1.2V), [1.2V,1.5V ] }, the output voltage v1=vdect-Vdelta, v2=vdect-2 Vdelta, v3=vdect-3 Vdelta, wherein 0<3delta < V, and the predetermined threshold is Vth. Comparing V1, V2, V3 with Vth, respectively, if V3> Vth, i.e., vdect-3Vdelta > Vth, then the monitored voltage Vdect is sufficiently large, e.g., vdect is greater than 1.2V, vdect does not cause write failure in this voltage interval, so write assist may not be turned on. If V3< Vth, i.e., vdect-3Vdelta < Vth, then it is indicated that the monitored voltage Vdect is not large enough, e.g., vdect is less than 1.2V, vdect may cause write failure in this voltage interval, so write assist can be turned on. However, the write assist specifically needs to turn on how much auxiliary voltage, and the output voltages of different output channels can be further compared with a preset threshold value to examine the voltage interval where the monitored voltage Vdect is located. For example, if V2> Vth, i.e., vdect-2Vdelta > Vth, then it is indicated that Vdect is medium, e.g., vdect is greater than 0.8V, at a voltage interval of [0.8V, 1.2V), so only a small write assist voltage needs to be turned on. Similarly, if V2< Vth, the magnitude relationship of V1 and Vth may be further determined in order to determine the actual magnitude of the monitored voltage Vdect. If Vdect is in a larger voltage interval, a smaller write auxiliary voltage can be started; if Vdect is in a smaller voltage interval, a larger write assist voltage needs to be turned on.

Alternatively, when comparing the output voltages of the output channels with the preset threshold, the comparison may be performed in various orders, for example, simultaneously, in a random order, or the like, so long as the target voltage interval in which the monitored voltage Vdect is located can be identified. In order to improve the identification efficiency of the monitored voltage Vdect, in one embodiment of the present invention, the identification module 12 may specifically be configured to: comparing the output voltage of each output channel of the voltage dividing module with the preset threshold according to a preset sequence; and discarding the comparison operation of the subsequent output channels under the condition that the output voltage of one of the output channels is determined to be larger than the preset threshold value. Alternatively, the preset sequence may be a sequence in which the output voltage is from low to high. In this way, the lowest one of the output channels is compared with the preset threshold first, and if the lowest one of the output channels is larger than the preset threshold, the monitored voltage Vdect is large enough, and the write assist is not required to be started. If the lowest output voltage is less than the preset threshold, the next lowest output voltage is greater than the preset threshold, indicating that the monitored voltage Vdect is greater, a smaller write assist voltage may be turned on. And so on.

In the above embodiment, after different divided voltages are performed on the monitored voltage Vdect, each divided voltage is compared with the same preset threshold value, so as to determine the target voltage interval in which the monitored voltage Vdect is located, but the embodiment of the present invention is not limited thereto, and in other embodiments of the present invention, the monitored voltage Vdect may also be directly compared with different preset threshold values, so as to obtain the target voltage interval in which the monitored voltage Vdect is located. For example, if Vdect is greater than 1.2V, it can be determined that the target voltage interval of Vdect is [1.2,1.5] by comparing Vdect with preset thresholds of 1.2V, 0.8V, and 0.6V, respectively.

Further, after the monitored voltage Vdect is recognized as the target voltage segment Vob, the auxiliary voltage corresponding to the target voltage segment can be generated by the auxiliary voltage generating unit 2. Alternatively, the auxiliary voltage may include a surge voltage or other stable voltage, a transient voltage, such as a voltage supplied from a constant voltage source, a voltage supplied from an oscillator, or the like, as long as the difficulty level of the writing operation can be reduced.

After the auxiliary voltage is applied to the write data transfer section 3, the write data transfer section 3 can be assisted in writing the data to be written to the target position Pob. Wherein target location Pob may comprise any location capable of receiving a write operation, for example, target location Pob may comprise one or more of the following in one embodiment of the present invention: target register, target storage unit, target port.

Specifically, as shown in fig. 5, the auxiliary voltage generating section 2 may include in one embodiment of the present invention:

a decoding module 21 connected to the voltage identification unit 1 for gating the auxiliary channel Wa required for generating the auxiliary voltage according to the target voltage interval identified by the voltage identification unit 1;

the generating module 22 is connected to the decoding module 21, and is configured to generate an auxiliary voltage through the auxiliary channel gated by the decoding module 21.

In this embodiment, since the monitored voltage Vdect identified by the voltage identifying unit 1 may be in any one of a plurality of target voltage intervals, the decoding module 21 may be configured to generate the corresponding required auxiliary voltage when Vdect is in any one of the target voltage intervals: respectively establishing a coding-gating corresponding relation for each target voltage interval and the corresponding auxiliary channel, wherein each target voltage interval can be correspondingly gated with 0 auxiliary channels or one or more auxiliary channels; and gating an auxiliary channel required by generating the auxiliary voltage according to the coding-gating corresponding relation.

Alternatively, in one embodiment of the present invention, which target voltage interval the monitored voltage Vdect is in may be represented by a set of signal codes. For example, when the voltage identification portion 1 compares the multiple divided voltages of the monitored voltage Vdect with the preset threshold values, different comparison results may correspond to different output levels, and the comparison results of the divided voltages may form a combination logic, i.e. a code. For example, the comparison result of the output voltage V3 of the output channel ch3 and the preset threshold Vth is V3< Vth, so as to obtain a logic low level "0", the comparison result of the output voltage V2 of the output channel ch2 and the preset threshold Vth is V2< Vth, so as to obtain a logic low level "0", the comparison result of the output voltage V1 of the output channel ch1 and the preset threshold Vth is V1> Vth, so as to obtain a logic high level "1", and the code corresponding to the target voltage interval where the monitored voltage Vdect is located may be expressed as v3OK v2OK v1 ok=001. Similarly, codes corresponding to other target voltage intervals may be denoted 010, 100, 111, etc., as long as different target voltage intervals can be distinguished.

The decoding module 21 is able to decode the above-mentioned code, gating the corresponding auxiliary channel WA. For each set of codes, different auxiliary channels or combinations of auxiliary channels can be turned on according to different target voltage intervals to generate different auxiliary voltages. For example, in one embodiment of the invention, code 0101 may turn on auxiliary channel WA1, generating auxiliary voltage VA, code 0111 may turn on auxiliary channel WA2, generating auxiliary voltage 2VA, code 1001 may turn on auxiliary channels WA2 and WA3, generating auxiliary voltage 4VA, etc.

In particular implementations, the decode module 21 may include a first logic gate. Alternatively, the first logic gate may comprise a series of AND gates, NOT gates, OR gates, and combinations thereof. The input signal of the first logic gate may be a signal combination corresponding to the target voltage interval where the monitored voltage Vdect is located, for example, V3OK V2OK V1OK, which is recognized by the voltage recognition part 1, and the output signal of the first logic gate may be a gated auxiliary channel, for example, the auxiliary channel WA2 is gated, and the signal corresponding to the auxiliary channel WA2 in the output signal of the first logic gate is "1", and the signals corresponding to other non-gated auxiliary channels are "0". Illustratively, in an embodiment of the present invention, one configuration of the first logic gate may be as shown in FIG. 6.

The generating module 22 may generate the corresponding auxiliary voltage through the auxiliary channel gated by the decoding module 21. Specifically, the generation module 22 may include one or more auxiliary channels, wherein each auxiliary channel may include a second logic gate and a capacitor connected in series with the second logic gate. Alternatively, the input terminal of the second logic gate may be connected to the decoding module 21, and it is determined whether each auxiliary channel is gated according to the output of the decoding module 21. The output of the second logic gate may be connected to a corresponding capacitor, which may be charged and a voltage difference may be formed between the plates of the capacitor.

The second logic gate may output a high level or a low level depending on whether the auxiliary channel needs to generate an auxiliary voltage, and suddenly increases or decreases one plate potential of the capacitor by switching between the high level and the low level. Since the voltage between the two plates of the capacitor cannot be suddenly changed, the potential of the other plate of the capacitor is suddenly increased or decreased, thereby generating an impulse voltage which can be applied as an auxiliary voltage to the write data transfer section 3 so that the data to be written is smoothly written into the target position through the write data transfer section 3. As the capacitor is charged or discharged more slowly, the surge voltage gradually disappears and the circuit reaches a new equilibrium. Illustratively, in an embodiment of the present invention, one configuration of the second logic gate and the capacitor may be as shown in FIG. 7.

In order to further reduce power consumption, in one embodiment of the present invention, as shown in fig. 8, the write assist device may further include a latch section 4, one end of the latch section 4 being connected to the voltage identifying section 1, and the other end being connected to the assist voltage generating section 2, for latching the target voltage section identified by the voltage identifying section 1. In this way, after the target voltage section in which the monitored voltage is located is identified, the auxiliary voltage generating unit 2 can decode and generate the auxiliary voltage by the target voltage section latched by the latch unit 4, and the voltage identifying unit 1 does not need to perform the continuous voltage identifying operation. Alternatively, in one embodiment of the present invention, the voltage identifying unit 1 may be periodically triggered to perform a voltage identifying operation by means of a timer or the like.

The latch unit 4 is divided into circuits according to the functions of the circuits, and the latch unit 4 may be provided independently of the voltage recognizing unit 1 and the auxiliary voltage generating unit 2, or may be provided in the voltage recognizing unit 1 or in the auxiliary voltage generating unit 2. The embodiments of the present invention are not limited in this regard.

Further, in an embodiment of the present invention, when the voltage identification portion 1 does not perform the voltage identification operation, the voltage identification portion 1 may be further configured to close its dc path according to the identified target voltage interval, so as to further reduce power consumption. For example, the output signal of the voltage identification unit 1 may be fed back to the input terminal of the voltage identification unit 1 through appropriate combinational logic to close the dc path of the voltage identification unit 1. In order to ensure that the latch 4 has successfully latched the identified target voltage interval when the dc path of the voltage identification part 1 is closed, in one embodiment of the present invention, the output signal of the voltage identification part 1 may be fed back to the input terminal of the voltage identification part 1 after passing through a plurality of delays. In another embodiment of the present invention, the output signal of the latch unit 4 may be introduced into the input terminal of the voltage identification unit 1 to be matched with the output signal of the voltage identification unit 1, thereby closing the dc path of the voltage identification unit 1. Illustratively, in one embodiment of the present invention, one configuration of the latch 4 may be as shown in fig. 9.

The foregoing embodiments describe in detail the structure and operation principle of the write assist device, in which the assist voltage generating section 2 is capable of generating a corresponding assist voltage based on the identification of the monitored voltage by the voltage identifying section 1, and applying the assist voltage to the write data transmitting section 3, that is, assisting the write data transmitting section 3 to write the data to be written to the target location. Specifically, in one embodiment of the present invention, the write data transfer section 3 may include a plurality of different ports, and may include a plurality of auxiliary voltage application modes.

As shown in fig. 10, in one embodiment of the present invention, the write data transfer section 3 is provided with a write gate 31, a data input 32, a data output 33; the data output 33 is connected to the target location Pob. For example, the write data transmission section 3 may be a MOS transistor, wherein the write gate terminal 31 may be a gate of the MOS transistor, the data input terminal 32 may be a source of the MOS transistor, and the data output terminal 33 may be a drain of the MOS transistor. Of course, the write data transfer section 3 may have other structures having a data transfer function, such as a transistor, a gate, and the like.

The auxiliary voltage generating unit 2 may be connected to the data input terminal 32, and generates the first auxiliary voltage Vass1 according to the target voltage section identified by the voltage identifying unit 1, and applies the first auxiliary voltage Vass1 to the data input terminal 32, wherein the first auxiliary voltage Vass1 has a polarity opposite to that of the voltage of the write gate terminal 31. In this way, the addition of the auxiliary voltage increases the voltage difference between the write gate 31 and the data input 32 of the write data transfer section 3, thereby increasing the write current and improving the write success rate.

Alternatively, in another embodiment of the present invention, the auxiliary voltage generating part 2 may be connected to the write gate terminal 31 for generating the second auxiliary voltage Vass2 according to the target voltage section identified by the voltage identifying part 1 and applying the second auxiliary voltage Vass2 to the write gate terminal 31, wherein the second auxiliary voltage Vass2 has the same voltage polarity as the write gate terminal 31. In this way, the addition of the auxiliary voltage can increase the voltage difference between the write gate terminal 31 and the data input terminal 32 of the write data transfer section 3, thereby increasing the write current and improving the write success rate.

Of course, in other embodiments of the present invention, the first auxiliary voltage Vass1 may be applied to the data input terminal 32 and the second auxiliary voltage Vass2 may be applied to the write gate terminal 31 to generate the superimposed write assist effect.

In addition, the write assist apparatus provided by the embodiments of the present invention may further incorporate sequential logic to help the sequential logic achieve proper signal setup hold times.

The write assist device provided by the embodiments of the present invention will be described in detail below by way of specific embodiments.

FIG. 11 is a schematic diagram of a write assist apparatus according to an embodiment of the present invention. The write assist apparatus may include: the voltage identifying module 61 is configured to detect a voltage of a voltage domain in which the tracking word line WL is located (i.e. a power supply for supplying power to the word line WL), and identify a target voltage interval to which the voltage domain belongs; a latch module 62 for latching the target voltage section identified by the voltage identification module 61; a decoding module 63, configured to gate an auxiliary channel to be opened according to the code corresponding to the target voltage interval; an auxiliary voltage generation module 64 for generating an auxiliary voltage according to the auxiliary channel according to the gating; the dc path closing module 65 is configured to close the dc path in the voltage identifying module 61 after the target voltage interval is identified, so as to save power consumption.

Fig. 12 is a state transition diagram of the circuit behavior of the write assist device provided by an embodiment of the present invention. The circuit behavior may include: a power ready state (state s 0), a voltage identification state (state s 1), a decoding state (state s 2), a dc path off state (state s 3), an auxiliary voltage non-on state (state s 4), and an auxiliary voltage on state (s 5).

Power ready state (state s 0). When the system power is ready, the state goes to voltage identification s1; otherwise, the system continues to stay in the state and waits for the power supply to be ready.

The voltage identifies the state (state s 1). When the circuit receives a signal that the power ready signal provided by the system starts to analyze the voltage, the circuit enters a voltage identification state, the circuit identifies the actual voltage of the current working environment of the chip and generates a grade code corresponding to the voltage, the voltage identification code expresses which interval the current voltage is in, and the voltage identification code generates a unique negative pressure code through downstream coding. For example, in one embodiment of the present invention, the voltage may be divided into 4 voltage intervals, and then 4 voltage identifiers (V1, V2, V3, V4) are generated corresponding to the 4-speed voltage intervals. The voltage identification code can generate 4-bit negative pressure programming codes (V4 OK and WA [3:1 ]) through s2 coding, wherein the 4 th bit V4OK is used for identifying whether negative pressure needs to be started or not, and the remaining three bits are used for adjusting the negative pressure starting amplitude. In another embodiment of the present invention, the voltage identification code is 5 bits, and the negative pressure code is 5 bits (V5 OK, WA [4:1 ]), wherein V5OK is used to indicate that the negative pressure generation is turned on or off. The number of voltage intervals can be realized differently according to different design requirements.

Fig. 13 is a schematic diagram of a voltage dividing circuit for voltage identification in the state s1, and fig. 14 to 18 are schematic diagrams of circuit structures for voltage interval identification. Referring to fig. 13-18, in an embodiment of the present invention, the voltage dividing circuit may have a plurality of methods, where a diode-connected MOS transistor is used to complete the interval grading of the voltage. The identification of the voltage interval is explained below in terms of two circuits V1 and V4.

Looking first at the V4 generation circuit. The enable signal required by the V4 circuit comes from Disable, pwrOK and Start. The V4 generation circuit is explained from two states, off and on:

1) When disable=1 (indicating off detection) or start=0 (indicating no detection) or pwrok=0 (indicating no power is Ready), ready_v4=1, nmos NTL4 is on, v4=0;

2) When disable=0 (indicating in detect), start and pwrok=1 (indicating power is Ready and detect is on), ready_v4=0, V4 voltage state is VDDM minus threshold voltage Vtp of 4 PMOS. Let vddm=1.0v, vtp=200 mv (millivolts), v4=1-0.2x4=200 mv. The NMOS NDIO4 is used for providing an extremely weak pull-down current for the PMOS series circuit, so that V4 is ensured not to be pulled up to be close to the VDDM level due to the fact that NTL4 is closed.

The voltage generation of V1 is the same as the principle of V4, and when voltage identification is carried out, the voltage of V1 is VDDM-1 x Vtp. The circuit of V1, V2, V3 differs from V4 in the source of the shut-down signal of the dc path. V4 closes the dc path by Disable, and V3 closes the dc path by V4OK, and at this time, it is considered that when v4 ok=1, it means that the power supply level is in the V4 section, and it is not determined that V3 or below is necessary. If v4ok=0, then again judge V3, see if the voltage level is in V3 interval, if yes, turn off the identification circuit of V2 and following interval, if not, continue to judge v2. and so on, until judging V1.

The off signal of the V2 dc path is V34OK, where V34OK indicates v3 ok=1 or v4 ok=1, which means that the voltage interval falls in the higher voltage or the high voltage interval, and the medium voltage interval represented by V2 does not need to be continuously determined, so that the dc path can be closed. The off signal of the V1 dc path is V234OK, which indicates that the voltage is determined to be in the medium voltage or higher voltage or high voltage section, and the determination of the low voltage section represented by V1 is not required, and the dc path can be closed.

After the voltage interval set (V1, V2, V3, V4) is obtained, the voltage interval where the power supply voltage VDDM is located can be identified. Specifically, in the case of power ready, start=0 sets all VOK signals to 0. Waiting for start=1 to come, and performing voltage analysis; after start=1, analysis starts from V4, and if the voltage level of V4 can turn on NMOS NE4, signal eval4 is pulled down to 0 and V4OK becomes 1. V4OK and system clock or other signals may generate the negative enable signal wa_enx for use by the auxiliary voltage generation module 64 in fig. 11. When v4ok=1, the analysis paths of V3 and below are turned off, and V3OK, V2OK, V1OK are set to 0, vmin is set to 0. If the voltage level of V4 is insufficient to turn on NE4, V4OK will be locked to 0 by PFB4 and turn on the V3 analysis path. The PFB4 and the NFB4 jointly lock the eval value in each analysis path, and the voltage identification result is prevented from being lost after the voltage identification module is closed.

The V3, V2, V1 path principles are similar to the V4 path. Except for the more set MOS and pass gates. If PMOS PRST3 is added to the V3 path, this MOS is used to set V3OK to 0 when v4 ok=1. The transmission gate turns off V3 to turn on the path of NE3 when v4ok=1. The addition of the set MOS and the transfer gate means in a design sense that when the voltage interval is identified as V4 (the highest interval), the lower interval does not need to be judged and analyzed any more. NEN3 sets the input of NE3 to 0 when the transmission gate is turned off, thereby preventing the generation of floating network.

When the voltage is identified, the voltage identification code at the highest position can be calculated, and if the voltage identification code at the highest position is valid, an auxiliary circuit is not required to be started to generate negative pressure impact; if the highest voltage identification code is not valid, the identification level may be sequentially lowered until a certain bit voltage identification code is considered valid. For example, V4, V3, V2, and V1 may be analyzed sequentially until v4ok=1 or v3ok=1 or v2ok=1 or v1ok=1 occurs, which sequentially represents that the current voltage is in the highest voltage, the next highest voltage, the middle voltage, and the low voltage section, and the corresponding negative voltage amplitude is the non-opening, weak amplitude, the middle amplitude, and the maximum amplitude. If none of the VOK changes from initial state 0 to 1. Then Vmin will become 1. Indicating that the current power supply identification is in the lowest voltage interval. The maximum negative pressure amplitude needs to be turned on.

Specifically, as shown in fig. 14, if the voltage identification code V4 of the highest order is valid (i.e., V4 is high enough to turn on NE 4), v4ok=1, V3, V2, V1, vmin stop judging, v4ok=1 indicates that the current voltage is in the negative pressure section without turning on. If V4 is not valid (i.e., V4 is low enough to turn on NE 4), v4ok=0, and the auxiliary circuit needs to be turned on to generate negative pressure, and then it needs to be continuously determined whether V3 is valid. Referring to fig. 15, if V3 is valid, v3ok=1, indicating that the voltage is in a higher interval, the negative voltage needs only a small amplitude to be turned on; if V3 is invalid, v3ok=0, and V2 needs to be continuously determined, see fig. 16. And so on until V1 is determined. Referring to fig. 17, if V1 is valid, a larger negative pressure amplitude is turned on, and if V1 is invalid, vmin=1 as shown in fig. 18. Vmin represents turning on all coupling capacitors for negative pressure surge.

Decoding state (state s 2). The code generated by the identification state can be decoded to obtain the auxiliary channel needed by the auxiliary voltage. For example, the combination codes of V3OK, V2OK, V1OK and Vmin may be decoded to obtain the strobe signals WA3, WA2, WA1 of the auxiliary channels. V4OK may generate the negative pressure enable signal wa_enx (see fig. 14).

The dc path off state (state s 3). After the negative pressure generated in s1 is encoded for a period of time, the voltage identification can be considered to be stable and effective, and the voltage identification code can reflect the actual working voltage. At this time, the logical operation may be performed on V4OK and V3 ok..vmin output from s1, the operation result is returned to s1, and the dc path existing in the voltage identification module is closed by the Disable signal, so as to reduce the power consumption of the identification circuit. The identified voltage identification code is latched by a latch unit in the circuit, and the voltage identification code continues to play a role in the subsequent negative pressure programming. Fig. 19 is a circuit embodiment for turning off the dc path. As shown in fig. 19, when the power supply voltage of the word line WL is recognized, it can be considered that the voltage recognition module can be turned off to achieve the purpose of saving power consumption. The delay unit is added in the circuit to ensure that the voltage is fully identified and analyzed, and the direct current path of the voltage identification module is turned off after each analysis path latches the corresponding voltage analysis value.

The auxiliary voltage state (state s 4) is not turned on. The circuit for generating negative pressure encoding according to VOK consists of NR1/NR2/NR3/IN1/XD1/XD2/XD 3. When v4ok=1, WA [3:1] =111, wa_enx=1 at clock enable, and no negative pressure is generated.

The auxiliary voltage state is turned on (s 5). When v4ok=0, wa [3:1] generates negative pressures of corresponding magnitudes from the above-mentioned 4 th strip, respectively. If v3 ok=1, WA [3:1] =011; if v2 ok=1, WA [3:1] =001; if v1 ok=1, WA [3:1] =000; if V3OK/V2OK/V1OK is 0 and Vmin=1, WA [3:1] =000 is started as the maximum negative pressure as V1 OK.

In a second aspect, correspondingly, the embodiment of the invention further provides a working method of the write-assist device, which can effectively improve the operation efficiency and the suitability of write assist.

As shown in fig. 20, the working method of the write assist apparatus provided by the embodiment of the present invention may include:

s71, identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

s72, generating auxiliary voltage according to the target voltage interval so as to write the data to be written into the target position under the assistance of the auxiliary voltage.

According to the working method of the write auxiliary device provided by the embodiment of the invention, the voltage interval where the monitored voltage is located is identified from the preset voltage interval set, the target voltage interval is obtained, and the auxiliary voltage is generated according to the target voltage interval, so that the data to be written is written into the target position under the assistance of the auxiliary voltage. Therefore, the proper auxiliary voltage required by the writing auxiliary device during data writing operation can be timely determined according to the actual size of the monitored voltage in the actual work of the circuit, and the auxiliary voltage is timely generated, so that complex testing operation is not required, and the method is applicable to various scenes, and therefore the writing auxiliary efficiency and the suitability are effectively improved.

Optionally, in step S71, identifying, from a preset set of voltage intervals, a voltage interval in which the monitored voltage is located, where the obtaining a target voltage interval may specifically include:

dividing the monitored voltage and then passing through at least one output channel, wherein the output voltage of each output channel is respectively one divided voltage of the monitored voltage, and the output voltages of the output channels are mutually unequal;

and identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel and the preset threshold value, and obtaining a target voltage interval.

Optionally, identifying, from the preset set of voltage intervals, a voltage interval in which the monitored voltage is located according to a relationship between the output voltage of each output channel and a preset threshold value may include:

comparing the output voltage of each output channel with the preset threshold value according to a preset sequence;

and discarding the comparison operation of the subsequent output channels under the condition that the output voltage of one of the output channels is determined to be larger than the preset threshold value.

Optionally, in step S72, generating the auxiliary voltage according to the target voltage interval may include:

According to the target voltage interval, gating an auxiliary channel required by generating the auxiliary voltage;

the auxiliary voltage is generated through the auxiliary channel.

Optionally, the gating the auxiliary channel required for generating the auxiliary voltage according to the target voltage interval may include:

respectively establishing coding-gating corresponding relation for each target voltage interval and the corresponding auxiliary channels, wherein each target voltage interval corresponds to 0 gating, one or more auxiliary channels;

and gating an auxiliary channel required by generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, after identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set and obtaining a target voltage interval, before generating the auxiliary voltage according to the target voltage interval, the working method of the write auxiliary device provided by the embodiment of the invention may further include: latching the target voltage interval.

Optionally, after identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set and obtaining the target voltage interval, the working method of the write assist device provided by the embodiment of the invention may further include: and stopping the identification of the monitored voltage according to the identified target voltage interval.

The specific circuit structure and the working process of the write assist device according to the embodiment of the present invention are described in the foregoing, and are not repeated here.

In a third aspect, correspondingly, the embodiment of the present invention further provides a memory, where any of the write assist devices provided in the foregoing embodiment of the present invention is disposed, so that corresponding beneficial technical effects can also be generated, and specific reference may be made to the foregoing embodiment, which is not repeated herein.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.

In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.

For convenience of description, the above apparatus is described as being functionally divided into various units/modules, respectively. Of course, the functions of the various elements/modules may be implemented in the same piece or pieces of software and/or hardware when implementing the present invention.

Those skilled in the art will appreciate that implementing all or part of the above-described methods in accordance with the embodiments may be accomplished by way of a computer program stored on a computer readable storage medium, which when executed may comprise the steps of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), or the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims

1. A write assist device, comprising:

a voltage identification part, one end of which is connected with the monitored voltage, and the other end of which is connected with an auxiliary voltage generation part, and is used for identifying the voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

the auxiliary voltage generating part is connected with the voltage identifying part at one end and the writing data transmitting part at the other end, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the writing data transmitting part so as to assist the writing data transmitting part to write the data to be written into the target position, wherein the monitored voltage comprises a first power supply voltage and/or a first node voltage, the first node voltage is related to the first power supply voltage, and the first power supply voltage is used for providing a writing strobe signal for the writing data transmitting part.

2. The write assist device of claim 1, wherein the voltage identification portion comprises:

the input end of the voltage dividing module is connected with the monitored voltage, the output end of the voltage dividing module comprises at least one output channel, the output voltage of each output channel is respectively a divided voltage of the monitored voltage, and the output voltages of the output channels are mutually unequal;

the identification module is connected with the voltage division module and is used for identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel of the voltage division module and the preset threshold value to obtain a target voltage interval.

3. The write-assist device of claim 2, wherein the identification module is specifically configured to:

comparing the output voltage of each output channel of the voltage dividing module with the preset threshold according to a preset sequence;

4. The write assist device of claim 1 wherein the assist voltage generating section comprises:

The decoding module is connected with the voltage identification part and used for gating an auxiliary channel required by generating the auxiliary voltage according to the target voltage interval identified by the voltage identification part;

and the generation module is connected with the decoding module and is used for generating the auxiliary voltage through the auxiliary channel gated by the decoding module.

5. The write assist device of claim 4 wherein the decode module is specifically configured to:

6. The write assist device of claim 4 wherein the decode module comprises a first logic gate; the generating module comprises at least one auxiliary channel, and each auxiliary channel comprises a second logic gate and a capacitor connected in series with the second logic gate.

7. The write assist device of claim 1, further comprising: and a latch unit having one end connected to the voltage identification unit and the other end connected to the auxiliary voltage generation unit, for latching the target voltage range identified by the voltage identification unit.

8. The write assist device of claim 1 wherein the voltage identification section is further configured to close its own dc path based on the identified target voltage interval.

9. The write assist device of claim 1 wherein the monitored voltage comprises at least one of: a first power supply voltage for providing a write strobe signal for the write data transfer section; a first node voltage having a preset logic level under a preset condition.

10. The write assist device of claim 1 wherein the assist voltage comprises a surge voltage.

11. The write assist device of claim 1 wherein the target location comprises at least one of: target register, target storage unit, target port.

12. The write assist device according to any one of claims 1 to 11, wherein the write data transfer section is provided with a write gate, a data input, a data output; the data output end is connected with the target position;

the auxiliary voltage generating part is connected with the data input end and is used for generating a first auxiliary voltage according to the target voltage interval identified by the voltage identifying part and applying the first auxiliary voltage to the data input end, wherein the polarity of the first auxiliary voltage is opposite to that of the voltage of the writing strobe end;

And/or the number of the groups of groups,

the auxiliary voltage generating part is connected with the writing strobe terminal and is used for generating a second auxiliary voltage according to the target voltage interval identified by the voltage identifying part and applying the second auxiliary voltage to the writing strobe terminal, wherein the second auxiliary voltage has the same voltage polarity as the writing strobe terminal.

13. A method of operating a write assist device, comprising:

identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

generating an auxiliary voltage according to the target voltage interval, so as to write the data to be written into the target position under the assistance of the auxiliary voltage, wherein the monitored voltage comprises a first power supply voltage and/or a first node voltage, the first node voltage is associated with the first power supply voltage, and the first power supply voltage is used for providing a write strobe signal for the write data transmission part.

14. The method of claim 13, wherein identifying the voltage interval in which the monitored voltage is located from the preset set of voltage intervals, and obtaining the target voltage interval comprises:

15. The method of claim 14, wherein the identifying, from the preset set of voltage intervals, the voltage interval in which the monitored voltage is located according to the relationship between the output voltage of each output channel and a preset threshold value comprises:

16. The method of claim 13, wherein the generating an auxiliary voltage from the target voltage interval comprises:

The auxiliary voltage is generated through the auxiliary channel.

17. The method of claim 16, wherein gating the auxiliary channel required to generate the auxiliary voltage according to the target voltage interval comprises:

18. The method of claim 13, wherein the identifying a voltage interval in which the monitored voltage is located from a preset set of voltage intervals, after obtaining a target voltage interval, and before generating the auxiliary voltage according to the target voltage interval, further comprises:

latching the target voltage interval.

19. The method of claim 13, wherein after identifying the voltage interval in which the monitored voltage is located from the preset set of voltage intervals, the method further comprises: and stopping the identification of the monitored voltage according to the identified target voltage interval.

20. A memory, characterized in that the memory is provided with a write assist device as claimed in any one of claims 1-12.