CN113314175A

CN113314175A - Write-assist device, working method thereof and memory

Info

Publication number: CN113314175A
Application number: CN202110574056.8A
Authority: CN
Inventors: 孙燃; 姚其爽; 魏依苒
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-05-25
Filing date: 2021-05-25
Publication date: 2021-08-27
Anticipated expiration: 2041-05-25
Also published as: CN113314175B

Abstract

The embodiment of the invention discloses a write assist device, a working method thereof and a memory, relates to the technical field of computers, and can effectively improve write assist efficiency and adaptability. The device comprises: the voltage identification part is connected with the monitored voltage at one end and the auxiliary voltage generation part at the other end, and is used for identifying a voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; and the auxiliary voltage generating part is connected with the voltage identification part at one end and connected with a write data transmission part at the other end, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write data to be written into a target position. The invention is suitable for the memory write operation.

Description

Write-assist device, working method thereof and memory

Technical Field

The invention relates to the technical field of computers, in particular to a writing auxiliary device, a working method thereof and a memory.

Background

Low power consumption is an important issue in today's integrated circuit design, and both dynamic power consumption and static power consumption are directly related to the power supply voltage for the chip, so reducing the power supply voltage is one of the effective ways to achieve low power consumption.

However, for many circuits, power supply voltage reduction, while reducing power consumption, may also adversely affect circuit performance. For example, as for a Static Random Access Memory (SRAM) storage circuit, an SRAM storage cell array is provided in the SRAM storage circuit. The SRAM memory cell array is composed of a plurality of memory cells bitcell, and each memory cell can be used for storing a one-bit

binary number

0 or 1. Although the reduction of the power supply voltage can save the working power consumption of the bitcell, the gate-source voltage difference of a transistor (also called a transmission transistor) for transmitting write data during write operation is reduced, and the write current is reduced, so that the write time is prolonged, and even a write failure may occur. For this reason, write assist techniques have been developed.

The write assist technique may be implemented in various ways, for example, during a write operation, a negative surge voltage may be applied to a bit selection line of the memory cell to lower a source voltage of a pass transistor, so as to increase a gate-source voltage difference of the pass transistor, increase a write current, and increase write power; or, during the writing operation, a positive surge voltage can be added to the word selection line of the storage unit to increase the grid voltage of the transmission tube, so that the grid-source voltage difference of the transmission tube is increased, the writing current is increased, and the writing power is increased. However, for a large number of chips, process variations often occur between different chips, and a large number of tests are required to determine which voltage of which chip requires a large surge voltage, and the test results are burned into the fuse array of the chip. This results in, on the one hand, a very inefficient determination of the surge voltage, and, on the other hand, the surge voltage for write-assist activation cannot be adapted to different voltage scenarios due to the burning-in of fixed values in the fuse array.

Aiming at the problems of low efficiency and poor adaptability of the write-assist starting impulse voltage, no effective solution is available in the related technology.

Disclosure of Invention

In view of this, embodiments of the present invention provide a write assist apparatus, a working method thereof, and a memory, which can effectively improve write assist efficiency and adaptability.

In a first aspect, an embodiment of the present invention provides a write assist apparatus, including: the voltage identification part is connected with the monitored voltage at one end and the auxiliary voltage generation part at the other end, and is used for identifying a voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; and the auxiliary voltage generating part is connected with the voltage identification part at one end and connected with a write data transmission part at the other end, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write data to be written into a target position.

Optionally, the voltage identification part includes: the input end of the voltage division module is connected with the monitored voltage, the output end of the voltage division module comprises at least one output channel, the output voltage of each output channel is divided by the monitored voltage, and the output voltages of the output channels are not equal to each other; and the identification module is connected with the voltage division module and used for identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel of the voltage division module and a preset threshold value to obtain a target voltage interval.

Optionally, the identification module is specifically configured to: comparing the output voltage of each output channel of the voltage division module with the preset threshold value according to a preset sequence; and in the case that the output voltage of one output channel is determined to be larger than the preset threshold value, abandoning the comparison operation of the subsequent output channel.

Optionally, the preset sequence is a sequence of the output voltages from low to high.

Optionally, the auxiliary voltage generating unit includes: the decoding module is connected with the voltage identification part and used for gating an auxiliary channel required by generating the auxiliary voltage according to the target voltage interval identified by the voltage identification part; and the generating module is connected with the decoding module and used for generating the auxiliary voltage through the auxiliary channel gated by the decoding module.

Optionally, the decoding module is specifically configured to: respectively establishing coding-gating corresponding relations for each target voltage interval and the auxiliary channels corresponding to the target voltage intervals, wherein each target voltage interval correspondingly gates 0 or one or more auxiliary channels; and gating an auxiliary channel required for generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, the decoding module includes a first logic gate; the generation module includes at least one of the auxiliary channels, each of which includes a second logic gate and a capacitor connected in series with the second logic gate.

Optionally, the write assist apparatus further includes: and the latch part is connected with the voltage identification part at one end and the auxiliary voltage generation part at the other end and is used for latching the target voltage interval identified by the voltage identification part.

Optionally, the voltage identification unit is further configured to close a dc path of the voltage identification unit according to the identified target voltage interval.

Optionally, the monitored voltage comprises at least one of: a first power supply voltage for supplying a write strobe signal to the write data transfer section; a first node voltage having a preset logic level under a preset condition.

Optionally, the auxiliary voltage comprises a surge voltage.

Optionally, the target location includes at least one of: target register, target memory location, target port.

Optionally, the write data transmission part is provided with a write strobe, a data input end and a data output end; the data output end is connected with the target position; the auxiliary voltage generating part is connected with the data input end and used for generating a first auxiliary voltage according to the target voltage interval identified by the voltage identification part and applying the first auxiliary voltage to the data input end, wherein the polarity of the first auxiliary voltage is opposite to that of the voltage of the write gating end; and/or the auxiliary voltage generating part is connected with the write-in strobe end and used for generating a second auxiliary voltage according to the target voltage interval identified by the voltage identification part and applying the second auxiliary voltage to the write-in strobe end, wherein the polarity of the second auxiliary voltage is the same as that of the write-in strobe end.

In a second aspect, an embodiment of the present invention further provides a method for operating a write assist apparatus, including: identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval; and generating an auxiliary voltage according to the target voltage interval so as to write the data to be written into the target position with the aid of the auxiliary voltage.

Optionally, identifying the voltage interval in which the monitored voltage is located from the preset voltage interval set, and obtaining the target voltage interval includes: dividing the monitored voltage and then passing through at least one output channel, wherein the output voltage of each output channel is divided into one part of the monitored voltage, and the output voltages of the output channels are not equal to each other; and identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set according to the relation between the output voltage of each output channel and a preset threshold value to obtain a target voltage interval.

Optionally, the identifying, according to a relationship between the output voltage of each output channel and a preset threshold, a voltage interval in which the monitored voltage is located from the preset voltage interval set includes: comparing the output voltage of each output channel with the preset threshold value according to a preset sequence; and in the case that the output voltage of one output channel is determined to be larger than the preset threshold value, abandoning the comparison operation of the subsequent output channel.

Optionally, the generating the auxiliary voltage according to the target voltage interval includes: according to the target voltage interval, gating an auxiliary channel required by generating the auxiliary voltage; the auxiliary voltage is generated through the auxiliary channel.

Optionally, the gating an auxiliary channel required for generating the auxiliary voltage according to the target voltage interval includes: respectively establishing coding-gating corresponding relations for each target voltage interval and the auxiliary channels corresponding to the target voltage intervals, wherein each target voltage interval correspondingly gates 0 or one or more auxiliary channels; and gating an auxiliary channel required for generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, after the voltage interval in which the monitored voltage is located is identified from the preset voltage interval set, and after the target voltage interval is obtained, before the auxiliary voltage is generated according to the target voltage interval, the method further includes: and latching the target voltage interval.

Optionally, after the voltage interval where the monitored voltage is located is identified from the preset voltage interval set and the target voltage interval is obtained, the method further includes: and stopping the identification of the monitored voltage according to the identified target voltage interval.

In a third aspect, an embodiment of the present invention further provides a memory, where any one of the write assist apparatuses provided by the embodiments of the present invention is disposed in the memory.

The write assist device, the operating method thereof and the memory provided by the embodiment of the invention can monitor the monitored voltage in real time, identify the voltage interval where the monitored voltage is located from the preset voltage interval set to obtain the target voltage interval, generate the assist voltage according to the target voltage interval, and apply the assist voltage to the write data transmission part so as to assist the write data transmission part to write the data to be written into the target position. Therefore, the appropriate auxiliary voltage required by the write auxiliary device during data write operation can be determined in time according to the actual size of the monitored voltage in the actual work of the circuit, the auxiliary voltage can be generated in time, complex test operation is not needed, and the auxiliary voltage can be applied to various scenes, so that the write auxiliary efficiency and the adaptability are effectively improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic circuit diagram of a bitline negative write assist technique in an embodiment of the present invention;

FIG. 2 is a timing diagram of write data corresponding to the circuit shown in FIG. 1 in an embodiment of the present invention;

FIG. 3 is a schematic diagram of a write assist apparatus according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of another structure of a write assist apparatus according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of another structure of a write assist apparatus according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a first logic gate of a write assist apparatus according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a second logic gate of the write assist apparatus according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of yet another structure of a write assist apparatus provided in accordance with an embodiment of the present invention;

FIG. 9 is a schematic structural diagram of a latch portion in the write assist apparatus according to an embodiment of the present invention;

FIG. 10 is a schematic diagram illustrating a connection relationship between an auxiliary voltage generating unit and a write data transmitting unit in a write assist apparatus according to an embodiment of the present invention;

FIG. 11 is a detailed structural diagram of a write assist apparatus according to an embodiment of the present invention;

FIG. 12 is a state transition diagram illustrating the circuit behavior of the write assist device of the embodiment of FIG. 11;

FIG. 13 is a schematic diagram of a voltage divider circuit in the voltage identification state of FIG. 12;

FIG. 14 is a schematic diagram of a circuit structure for identifying voltage intervals in the voltage identification state of FIG. 12;

FIG. 15 is a schematic diagram of another circuit configuration for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 16 is a schematic diagram of another circuit structure for voltage interval identification in the voltage identification state of FIG. 12;

FIG. 17 is a schematic diagram of yet another circuit configuration for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 18 is a schematic diagram of another circuit structure for performing voltage interval identification in the voltage identification state of FIG. 12;

FIG. 19 is a schematic circuit diagram of the DC path OFF processing state of FIG. 12;

FIG. 20 is a flowchart of a method for operating a write assist device according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As background, for many circuits, power supply voltage reduction, while reducing power consumption, may also adversely affect circuit performance, thus creating a write assist technique. The embodiment of the invention provides a write assist device, aiming at the problems of low efficiency and poor adaptability of write assist starting impulse voltage in the related art.

In order to facilitate understanding of the present invention, the write operation will be briefly described by taking an SRAM memory as an example.

Fig. 1 is a schematic diagram of a bit line negative voltage (NegBL) write assist technique, in which each SRAM bitcell includes two inverters with input and output connected back to back, a PMOS (P-Metal Oxide semiconductor Field Effect Transistor) of each inverter is referred to as a pull-up Transistor MPU of the bitcell, an NMOS of the inverter is referred to as a pull-down Transistor MPD of the bitcell, and an NMOS gated by a Word Line (WL) is referred to as pass transistors PGT and PGC. In the figure, the "@" symbol following the word line WL indicates that the voltage domain of the word line WL is VDDM (the power supply voltage source for the word line WL is VDDM). The circuit part where C1/C2/C3 is located is a write assist circuit. The write assist circuit may use the same power supply as the WL or a power supply different from the WL. C1/C2/C3 is a capacitive element, WA1/WA2/WA3 can generate different cc1/cc2/cc3 signals through different logic value combinations, and negative pressure impact is generated on the falling edge of cc1/cc2/cc3 respectively. The C1/C2/C3 capacitor can be composed of MOS capacitor or line-to-line coupling capacitor. The NMOS PDWR is a negative pressure pull-down tube, is gated by a signal WA _ ENX, is opened when negative pressure does not need to be generated, enables the lowest pull-down voltage of BL to be 0v, is closed when negative pressure needs to be generated, floats VSS _ WA, and performs negative pressure impact on the VSS _ WA by using the characteristic that the pressure difference between two ends of a capacitor does not change suddenly by using capacitors C1/C2/C3.

The operation of the write assist is briefly described below. When a write operation needs to be performed on a bitcell, a case of writing and storing the same value and a different value may be considered. When the same value is written, assuming that bitcell stores 0, writing 0 is ready (namely WrData is 0), the BLT prepares the value 0 to be written at this time, the BLC is 1, the pipes PGT and PGC to be transmitted are opened, the logic 0 prepared in advance on the bit line BLT is the same as the logic 0 of the bitcell QT, the logic 1 prepared in advance on the BLC is the same as the logic 1 of the bitcell QC, the value of the bitcell cannot be rewritten, and the bitcell enters a holding state after the transmission pipes PGT and PGC are closed; when the written value is opposite to the stored value of the bitcell, if the bitcell stores 1, at this time, 0 is ready to be written (that is, WrData is 0), the BLT is ready to be logic 0, the BLC is 1, when the transmission pipe PGT and PGC are opened, the bit line BLT pulls down 1 of QT to 0 through the transmission pipe PGT, the opposite pull-up pipe PUC is opened, the QC is pulled up to logic 1, after the subsequent transmission pipe PGT and PGC are closed, the bitcell enters a hold state, and the bit lines BLT and BLC are recharged back to logic 1 through PCHT and PCHC, so that the writing operation is completed.

Since the written value is opposite to the stored value of bitcell, when the supply voltage VDDM of bitcell is lowered, if the write assist is not turned on, the case of unsuccessful writing may occur. Specifically, as shown in fig. 2, when the VDDM of the bitcell is lowered, the WL voltage of the word line is lowered, and in the first writing period, the write assist is not turned on. After the signals become 1 to turn on the WPGT and the WPGC, the BLT is reduced to 0 level, the WL is waited to become 1, the WL becomes 1 to turn on the PGT and the PGC, the QT is gradually pulled down to a certain intermediate voltage, but the intermediate voltage does not reach the voltage value of the inversion of the bitcell, the opposite QC point does not rise to 1, and the writing fails. And in the second writing period, 0 is written into QT as in the first writing period, before the negative pressure enable WA _ ENX is changed into 0, the situation that QT and QC are same as the situation in the first period can be seen, and writing cannot be carried out until WA _ ENX is changed into 0, the ground signal VSS _ WA of BLT and BLC write-driving inverters X1 and X2 floats, meanwhile, the signal cc1/cc2/cc3 is changed from 1 to 0 through the combination of WA1/WA2/WA3, the voltage at two ends of a capacitor does not change suddenly, the negative pressure is coupled out from the initial 0 at one end of the capacitor C1/C2/C3 connected with VSS _ WA, the negative pressure is transmitted to the BLT, the grid-source voltage difference of a transmission pipe PGT of bitcell is increased, the current of the transmission pipe is increased, the voltage of a QT point is pulled down, the turnover point of the bitcell is reached, and writing is successful.

WA [3:1] is a control port opened by negative pressure impact. In the integrated circuit, the circuit working condition is complex and variable, and whether a certain circuit needs to be started or not and how much negative pressure impact needs to be started can be determined by WA [3:1 ]. When WA [3:1] is 1, no negative pressure is generated; when one bit of WA [3:1] is 0 and the other bit is 1, the negative voltage generated by the corresponding capacitor is started; two bits in WA [3:1] are 0, and when one bit is 1, the negative voltage of the two capacitor combinations is started; when all three bits of WA 3:1 are 0, the three capacitors are turned on to generate the maximum negative voltage.

In order to effectively improve the efficiency of starting the write-assist voltage and enable the write-assist voltage to be adaptive to various application scenarios, embodiments of the present invention provide a write-assist device, which can determine an appropriate assist voltage required by the write-assist device in data write operation in time according to the actual working condition of a circuit, and generate the assist voltage in time, so that not only is complicated test operation not required, but also the write-assist device can be applied to various scenarios, thereby effectively improving the write-assist efficiency and the adaptability. The following is a detailed description of specific examples. It should be noted that the write assist apparatus provided in the embodiments of the present invention can be applied not only to an SRAM, but also to other scenes requiring a write operation.

As shown in FIG. 3, an embodiment of the present invention provides a write assist apparatus, which may include:

a voltage identification part 1, one end of which is connected with the monitored voltage Vdect and the other end of which is connected with the auxiliary voltage generation part 2, for identifying the voltage interval in which the monitored voltage Vdect is located from a preset voltage interval set to obtain a target voltage interval Vob;

the auxiliary voltage generating unit 2 has one end connected to the voltage recognizing unit 1 and the other end connected to the write data transferring unit 3, and is configured to generate an auxiliary voltage Vass according to the target voltage interval Vob and apply the auxiliary voltage Vass to the write data transferring unit 3 to assist the write data transferring unit 3 in writing the data Datatowrite to be written into the target location Pob.

In the write assist device according to the embodiment of the present invention, the voltage identification unit 1 may monitor the monitored voltage Vdect in real time, identify the voltage interval in which the monitored voltage Vdect is located from the preset voltage interval set, obtain the target voltage interval Vob, and the auxiliary voltage generation unit 2 may generate the auxiliary voltage Vass according to the target voltage interval Vob and apply the auxiliary voltage Vass to the write data transmission unit 3 to assist the write data transmission unit 3 in writing the data to be written into the target position Pob. Therefore, the appropriate auxiliary voltage Vass required by the write auxiliary device during data write operation can be determined in time according to the actual size of the monitored voltage Vdect in the actual work of the circuit, and the auxiliary voltage Vass can be generated in time, so that the complicated test operation is not needed, and the auxiliary device can be applied to various scenes, thereby effectively improving the write auxiliary efficiency and the adaptability.

Alternatively, the monitored voltage Vdect may be any voltage signal that directly or indirectly reflects the difficulty of the write operation. For example, in one embodiment of the invention, the monitored voltage Vdect may include one or more of: a first power supply voltage for supplying a write strobe signal to the write data transfer section; a first node voltage having a preset logic level under a preset condition.

It is understood that the performance of the chips may vary under different PVTs (process voltage temperature angles), and thus, the performance of different chips may vary. Meanwhile, the running speed of the chip and the consumption of resources may also vary due to the distribution of the traffic and the computation carried by the chip. Therefore, the output voltage of each power supply that supplies power to the chip may also vary. For example, when the chip executes many and complicated operations, the voltage consumption consumed by each operation module is relatively large, resulting in a relatively low output voltage of the power supply. If the power supply is the power supply that supplies the write strobe signal to the write data transfer section 3, the difficulty of the write operation may be increased.

Further, when the output voltage of the power supply is low, the node voltages of some special nodes in the circuit may be affected, and when the output voltage of the power supply is inconvenient to monitor, the voltages of the special nodes may also be monitored, as long as the voltage fluctuation range of the node under the preset condition is known in advance. For example, a node voltage has a preset logic level 1 under a preset condition, and the corresponding voltage should be 1.1V or more, but due to the change of the power supply voltage, the voltage of the node under the preset condition is 0.9V, so that it can indirectly reflect that the writing operation may be in a difficult state. Thus, the write assist apparatus provided by the embodiment of the present invention can timely and accurately grasp whether the write operation is difficult and the difficulty level through monitoring the power supply voltage and the node voltage, thereby providing appropriate write assist to the write assist apparatus to smoothly complete the write operation.

The specific structure of the voltage discriminating portion 1 may be various. Specifically, as shown in fig. 4, in an embodiment of the present invention, the voltage identification unit 1 may specifically include:

a voltage dividing module 11, an input end of which is connected to the monitored voltage Vdect, an output end of which includes at least one output channel, an output voltage Vn of each output channel is a divided voltage of the monitored voltage Vdect, where n is a positive integer, and the output voltages Vn (e.g. V1, V2 … …) of each output channel are different from each other;

the identification module 12 is connected to the voltage dividing module 11, and configured to identify a voltage interval in which the monitored voltage Vdect is located from a preset voltage interval set according to a relationship between the output voltage Vn of each output channel of the voltage dividing module 11 and a preset threshold, so as to obtain a target voltage interval Vob.

The output voltage Vn of each output channel can divide the monitored voltage Vdect in various ways. For example, in one embodiment of the present invention, a plurality of voltage dividing elements may be connected in series between the monitored voltage Vdect and the ground signal, and the output voltages may be respectively obtained from different voltage dividing elements. Optionally, the voltage dividing element may be one or more of: resistors, diodes, triodes, MOS transistors, etc. For example, in one embodiment of the present invention, 3 resistors with equal resistance are connected in series between the monitored voltage Vdect and the ground signal, so that two output channels can be formed, and the output voltages thereof are Vdect/3 and 2Vdect/3 respectively. Therefore, the device for tracking the process parameter change through the diffusion resistor can realize the tracking of the process, the voltage, the temperature and the like in a voltage division mode.

Optionally, in another embodiment of the present invention, a plurality of different paths may be provided in parallel between the monitored voltage Vdect and the ground signal, where each path corresponds to one output channel and one output voltage. After the voltage division module 11 divides the monitored voltage Vdect, different output voltages of each output channel can be obtained, and the different output voltages are respectively compared with a preset threshold value, so that a voltage interval where the monitored voltage Vdect is located can be determined, and a target voltage interval Vob is obtained. The preset threshold may be implemented in various ways, such as a MOS transistor turn-on voltage, a diode turn-on voltage, a preset threshold implemented by various clamping measures, a voltage stabilizing measure, and the like.

For example, in one embodiment of the present invention, the preset voltage interval set is { [0.3, 0.6), [0.6V, 0.8V), [0.8V, 1.2V, [1.2V, 1.5V ] }, the output voltage V1 is Vdect-Vdelta, V2 is Vdect-2Vdelta, and V3 is Vdect-3Vdelta, where 0<3delta < V, and the preset threshold is Vth. Comparing V1, V2, and V3 with Vth respectively, if V3> Vth, i.e., Vdect-3Vdelta > Vth, it indicates that the monitored voltage Vdect is sufficiently large, e.g., Vdect is greater than 1.2V, and Vdect does not cause write failure in this voltage interval, so that the write assist may not be turned on. If V3< Vth, i.e., Vdrain-3 Vdrain < Vth, indicates that the monitored voltage Vdrain is not large enough, e.g., Vdrain is less than 1.2V, where Vdrain may cause write failure, thus turning on the write assist. However, the write assist specifically needs to turn on how much assist voltage, and can further compare the output voltages of different output channels with a preset threshold value to investigate a voltage interval where the monitored voltage Vdect is located. For example, if V2> Vth, i.e., Vdect-2Vdelta > Vth, it means that Vdect is equal, e.g., Vdect is greater than 0.8V and in the voltage range of [0.8V, 1.2V), so that only a small write assist voltage needs to be turned on. Similarly, if V2< Vth, the magnitude relationship of V1 to Vth may be further determined in order to determine the actual magnitude of the monitored voltage Vdect. If Vselect is in a larger voltage interval, a smaller write assist voltage can be turned on; if Vselect is in a smaller voltage interval, then a larger write assist voltage needs to be turned on.

Alternatively, when the output voltage of each output channel is compared with the preset threshold, the comparison may be performed in various orders, such as simultaneous comparison, comparison in a random order, and the like, as long as the target voltage interval in which the monitored voltage Vdect is located can be identified. In order to improve the efficiency of identifying the monitored voltage Vdect, in an embodiment of the present invention, the identifying module 12 may be specifically configured to: comparing the output voltage of each output channel of the voltage division module with the preset threshold value according to a preset sequence; and in the case that the output voltage of one output channel is determined to be larger than the preset threshold value, abandoning the comparison operation of the subsequent output channel. Alternatively, the preset sequence may be a sequence of the output voltages from low to high. Thus, the lowest one of the output voltages in each of the output channels is first compared with a preset threshold, and if the lowest one of the output voltages is greater than the preset threshold, it indicates that the monitored voltage Vdect is sufficiently large and the write assist does not need to be turned on. If the lowest output voltage is smaller than the preset threshold and the next lowest output voltage is larger than the preset threshold, it means that the monitored voltage Vdect is larger and the smaller write assist voltage can be turned on. And so on.

In the above embodiment, after the monitored voltage Vdect is subjected to different voltage division, each voltage division is compared with the same preset threshold value, so as to determine the target voltage interval where the monitored voltage Vdect is located. For example, Vdect is compared with preset threshold values of 1.2V, 0.8V and 0.6V, respectively, and if Vdect is greater than 1.2V, it can be determined that the target voltage range of Vdect is [1.2, 1.5 ].

Further, after the target voltage section Vob where the monitored voltage Vdect is located is identified, the auxiliary voltage generator 2 may generate the auxiliary voltage corresponding to the target voltage section. Alternatively, the auxiliary voltage may include a surge voltage or other stable voltage, a transient voltage, such as a voltage provided by a constant voltage source, a voltage provided by an oscillator, etc., as long as the difficulty of the write operation can be alleviated.

After the auxiliary voltage is applied to the write data transfer section 3, the write data transfer section 3 can be assisted in writing the data to be written to the target position Pob. Target location Pob may include any location capable of receiving a write operation, for example, in one embodiment of the invention, target location Pob may include one or more of the following: target register, target memory location, target port.

Specifically, as shown in fig. 5, in one embodiment of the present invention, the auxiliary voltage generating part 2 may include:

the decoding module 21 is connected with the voltage identification part 1 and used for gating an auxiliary channel Wa required by generating auxiliary voltage according to the target voltage interval identified by the voltage identification part 1;

and the generating module 22 is connected with the decoding module 21 and is used for generating the auxiliary voltage through the auxiliary channel gated by the decoding module 21.

In this embodiment, since the monitored voltage Vdect identified by the voltage identification unit 1 may be in any one of a plurality of target voltage intervals, in order to enable the auxiliary voltage generation unit 2 to generate the auxiliary voltage required by the voltage identification unit when the Vdect is in the target voltage intervals, the decoding module 21 may be configured to: respectively establishing coding-gating corresponding relations for each target voltage interval and the auxiliary channels corresponding to the target voltage intervals, wherein each target voltage interval can correspondingly gate 0 or one or more auxiliary channels; and gating an auxiliary channel required for generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, in an embodiment of the present invention, which target voltage interval the monitored voltage Vdect is in may be represented by a set of signal codes. For example, when the voltage identification portion 1 compares a plurality of divided voltages of the monitored voltage Vdect with the preset threshold, different comparison results may correspond to different output levels, and the comparison results of the divided voltages may form a combinational logic, i.e. a code. For example, if the comparison result between the output voltage V3 of the output channel ch3 and the preset threshold Vth is V3< Vth to obtain a logic low level "0", the comparison result between the output voltage V2 of the output channel ch2 and the preset threshold Vth is V2< Vth to obtain a logic low level "0", the comparison result between the output voltage V1 of the output channel ch1 and the preset threshold Vth is V1> Vth to obtain a logic high level "1", and the code corresponding to the target voltage interval where the monitored voltage Vdect is located may be represented as V3OK V2OK V1OK being 001. Similarly, codes corresponding to other target voltage intervals may be represented as 010, 100, 111, etc., as long as different target voltage intervals can be distinguished.

The decoding module 21 can decode the above codes and gate the corresponding auxiliary channel WA. For each group of codes, different auxiliary channels or combinations of auxiliary channels can be started according to different target voltage intervals to generate different auxiliary voltages. For example, in one embodiment of the present invention, the code 0101 may turn on the auxiliary channel WA1 to generate the auxiliary voltage VA, the code 0111 may turn on the auxiliary channel WA2 to generate the auxiliary voltage 2VA, the code 1001 may turn on the auxiliary channels WA2 and WA3 to generate the auxiliary voltage 4VA, and so on.

In one implementation, the decoding module 21 may include a first logic gate. Alternatively, the first logic gate may comprise a series of and gates, not gates, or gates, and combinations thereof. The input signal of the first logic gate may be a signal combination, for example, V3OK V2OK V1OK, corresponding to the target voltage interval in which the monitored voltage Vdect is located, which is recognized by the voltage recognition unit 1, and the output signal of the first logic gate may be a gated auxiliary channel, for example, the auxiliary channel WA2 is gated, so that the signal corresponding to the auxiliary channel WA2 in the output signal of the first logic gate is "1", and the signals corresponding to the other non-gated auxiliary channels are "0". For example, in an embodiment of the present invention, one structure of the first logic gate may be as shown in fig. 6.

The generating module 22 may generate the corresponding auxiliary voltage through the auxiliary channel gated by the decoding module 21. In particular, the generation module 22 may include one or more auxiliary channels, where each auxiliary channel may include a second logic gate and a capacitor connected in series with the second logic gate. Optionally, the input end of the second logic gate may be connected to the decoding module 21, and determine whether each auxiliary channel is gated according to the output of the decoding module 21. The output end of the second logic gate can be connected with a corresponding capacitor, and the capacitor can be charged and forms a voltage difference between two polar plates of the capacitor.

The second logic gate can output high level or low level according to whether the auxiliary channel needs to generate auxiliary voltage, and the potential of one plate of the capacitor is suddenly increased or decreased by switching between the high level and the low level. Since the voltage between the two plates of the capacitor cannot change suddenly, the potential of the other plate of the capacitor also increases or decreases suddenly, thereby generating a surge voltage, which can be applied to the write data transmission part 3 as an auxiliary voltage, so that the data to be written can be smoothly written into the target position by the write data transmission part 3. As the capacitor is charged or discharged more slowly, the surge voltage gradually disappears and the circuit reaches a new equilibrium. For example, in the embodiment of the present invention, a structure of the second logic gate and the capacitor may be as shown in fig. 7.

In order to further reduce power consumption, in an embodiment of the present invention, as shown in fig. 8, the write assist apparatus may further include a latch unit 4, where one end of the latch unit 4 is connected to the voltage identification unit 1, and the other end is connected to the assist voltage generation unit 2, and is configured to latch the target voltage interval identified by the voltage identification unit 1. Thus, after recognizing the target voltage section in which the monitored voltage is located, the auxiliary voltage generating unit 2 can decode and generate the auxiliary voltage depending on the target voltage section latched by the latch unit 4, and the voltage recognizing unit 1 does not need to perform a continuous voltage recognizing operation. Alternatively, in an embodiment of the present invention, the voltage identification unit 1 may be triggered periodically by means of a timer or the like to perform a voltage identification operation.

The latch unit 4 is divided according to the function of the circuit, and in the specific configuration of the circuit, the latch unit 4 may be provided in the voltage discriminating unit 1 or in the auxiliary voltage generating unit 2 independently of the voltage discriminating unit 1 and the auxiliary voltage generating unit 2. The embodiments of the present invention are not limited thereto.

Further, in an embodiment of the present invention, when the voltage identification portion 1 does not perform the voltage identification operation, the voltage identification portion 1 may also be configured to close its dc path according to the identified target voltage interval, so as to further reduce power consumption. For example, the output signal of the voltage identification part 1 may be fed back to the input terminal of the voltage identification part 1 through an appropriate combinational logic to close the dc path of the voltage identification part 1. In order to ensure that the latch unit 4 has successfully latched the identified target voltage interval when the dc path of the voltage identification unit 1 is closed, in an embodiment of the present invention, the output signal of the voltage identification unit 1 may be fed back to the input terminal of the voltage identification unit 1 after passing through a plurality of time delays. In another embodiment of the present invention, the output signal of the latch unit 4 may be introduced into the input terminal of the voltage identification unit 1 to cooperate with the output signal of the voltage identification unit 1 to close the dc path of the voltage identification unit 1. For example, in an embodiment of the present invention, a structure of the latch portion 4 may be as shown in fig. 9.

The foregoing embodiment describes the structure and operation principle of the write assist apparatus in detail, wherein the assist voltage generation unit 2 can generate a corresponding assist voltage according to the recognition of the monitored voltage by the voltage recognition unit 1, and apply the assist voltage to the write data transmission unit 3, that is, the write data transmission unit 3 can assist the write data transmission unit 3 to write the data to be written into the target location. Specifically, in one embodiment of the present invention, the write data transfer part 3 may include a plurality of different ports, and specifically may include a plurality of auxiliary voltage application manners.

As shown in fig. 10, in one embodiment of the present invention, the write data transfer section 3 is provided with a write enable terminal 31, a data input terminal 32, a data output terminal 33; the data output 33 is connected to the target location Pob. For example, the write data transfer unit 3 may be a MOS transistor, wherein the write gate 31 may be a gate of the MOS transistor, the data input terminal 32 may be a source of the MOS transistor, and the data output terminal 33 may be a drain of the MOS transistor. Of course, the write data transfer unit 3 may have other structures having a data transfer function, such as a transistor and a gate.

The auxiliary voltage generating unit 2 may be connected to the data input terminal 32, and configured to generate a first auxiliary voltage Vass1 according to the target voltage interval identified by the voltage identifying unit 1, and apply the first auxiliary voltage Vass1 to the data input terminal 32, wherein the first auxiliary voltage Vass1 has a polarity opposite to that of the write strobe terminal 31. Thus, the voltage difference between the write enable terminal 31 and the data input terminal 32 of the write data transmission unit 3 can be increased by adding the auxiliary voltage, so that the write current can be increased, and the write success rate can be improved.

Alternatively, in another embodiment of the present invention, the auxiliary voltage generating unit 2 may be connected to the write gate terminal 31, and configured to generate a second auxiliary voltage Vass2 according to the target voltage interval identified by the voltage identifying unit 1, and apply the second auxiliary voltage Vass2 to the write gate terminal 31, wherein the second auxiliary voltage Vass2 has the same voltage polarity as the write gate terminal 31. In this way, the voltage difference between the write enable terminal 31 and the data input terminal 32 of the write data transfer unit 3 can be increased by adding the auxiliary voltage, so that the write current can be increased, and the write success rate can be improved.

Of course, in other embodiments of the present invention, the first auxiliary voltage Vass1 may be applied to the data input terminal 32, and the second auxiliary voltage Vass2 may be applied to the write strobe terminal 31 to generate a superimposed write-assist effect.

In addition, the write assist apparatus provided by the embodiment of the present invention may further add sequential logic to help the sequential logic to achieve proper signal setup hold time.

The write assist apparatus provided by the embodiment of the present invention is explained in detail below by way of specific embodiments.

FIG. 11 is a schematic diagram of a write assist apparatus according to an embodiment of the present invention. The write assist apparatus may include: a voltage identification module 61, configured to detect a voltage of a voltage domain where the word select line WL is located (i.e., a power supply that supplies power to the word select line WL), and identify a target voltage interval to which the word select line WL belongs; a latch module 62, configured to latch the target voltage interval identified by the voltage identification module 61; a decoding module 63, configured to gate an auxiliary channel to be opened according to the code corresponding to the target voltage interval; an auxiliary voltage generation module 64 for generating an auxiliary voltage according to the gated auxiliary channel; and the direct current path closing module 65 is used for closing the direct current path in the voltage identification module 61 after the target voltage interval is identified, so that the power consumption is saved.

FIG. 12 is a state transition diagram of the circuit behavior of a write assist device provided by an embodiment of the present invention. The circuit behavior may mainly include: a power supply ready state (state s0), a voltage identification state (state s1), a decoding state (state s2), a direct current path closing state (state s3), a no auxiliary voltage opening state (state s4), and an auxiliary voltage opening state (s 5).

Power ready state (state s 0). When the system power is ready, the state goes to the voltage identification s 1; otherwise, the system stays in the present state to wait for the power supply to be ready.

The voltage identifies the state (state s 1). When the circuit receives a signal that a power supply ready signal provided by a system begins to analyze voltage, the circuit enters a voltage identification state, the circuit identifies the actual voltage of the current working environment of the chip and generates a grade code corresponding to the voltage, the voltage identification code expresses which interval the current voltage is in, and the voltage identification code generates a unique negative pressure code through a downstream code. For example, in one embodiment of the present invention, the voltage may be divided into 4 voltage intervals, and then 4 voltage identification codes (V1, V2, V3, V4) are generated, corresponding to the 4 voltage intervals. The voltage identification code is encoded by s2 to generate a 4-bit negative voltage programming code (V4OK and WA [3:1]), wherein the 4 th bit V4OK is used to identify whether the negative voltage needs to be turned on, and the remaining three bits are used to adjust the negative voltage turn-on amplitude. In another embodiment of the present invention, the voltage identification code is 5 bits, and the negative voltage encoding is 5 bits (V5OK, WA [4:1]), wherein V5OK is used to indicate whether to turn on or off the negative voltage generation. The number of the voltage intervals can be realized differently according to different design requirements.

Fig. 13 is a schematic diagram of a voltage divider circuit for voltage identification in the state s1, and fig. 14 to 18 are schematic diagrams of a circuit structure for voltage interval identification. In conjunction with fig. 13-18, the voltage divider circuit may have a variety of methods in embodiments of the present invention, where a diode-connected MOS transistor is used to achieve voltage step-by-step voltage grading. The identification of the voltage interval is explained below with two circuits V1 and V4.

Looking first at the V4 generation circuit. The enable signals required by the V4 circuit come from Disable, PwrOK, and Start. The following explains the V4 generation circuit from two states, closed and open:

1) when Disable is 1 (indicating off detection), Start is 0 (indicating no detection), or pwrik is 0 (indicating no power Ready), Ready _ V4 is 1, NMOS NTL4 is on, V4 is 0;

2) when Disable is 0 (indicating under test) and Start and PwrOK are 1 (indicating power Ready and on test), Ready _ V4 is 0 and the V4 voltage state is VDDM minus the 4 PMOS threshold voltages Vtp. Let VDDM be 1.0V, Vtp be 200mv (millivolts), and V4 be 1-0.2 4 be 200 mv. The use of NMOS NDIO4 is to provide a very weak pull-down current to the PMOS series path, ensuring that V4 is not drained and pulled up to near VDDM level because NTL4 is closed.

The voltage generation of V1 is the same principle as V4, and when voltage identification is performed, the voltage of V1 is VDDM-1 × Vtp. The difference between the circuits of V1, V2 and V3 and V4 lies in the source of the dc path closing signal. V4 closes the dc path by Disable, V3 closes the dc path by V4OK, and in this case, it is considered that when V4OK becomes 1, it indicates that the power supply level is in the V4 section, and it is not determined that V3 or less is necessary. If V4OK is equal to 0, then determine V3 again, see whether the voltage level is in the V3 interval, if yes, close the identification circuit in V2 and the following intervals, if not, continue to determine V2.

The closing signal of the dc path of V2 is V34OK, and V34OK indicates that V3OK is 1 or V4OK is 1, which means that the voltage interval falls into a higher voltage or a higher voltage interval at this time, and the intermediate voltage interval represented by V2 does not need to be continuously determined, and the dc path can be closed. The closing signal of the dc path of V1 is V234OK, which indicates that the voltage is already determined to be in the middle voltage or higher voltage or high voltage range, and the determination of the low voltage range represented by V1 is not necessary, so that the dc path can be closed.

After the voltage interval sets (V1, V2, V3, V4) are obtained, the voltage interval in which the power supply voltage VDDM is located can be identified. Specifically, when the power supply is ready, the start-0 sets all VOK signals to 0. Waiting for 1-start to arrive, and carrying out voltage analysis; after Start is 1, starting with V4, if the voltage level of V4 can turn on NMOS NE4, the signal eval4 is pulled down to 0 and V4OK becomes 1. V4OK and a system clock or other signals of the circuit may generate a negative voltage enable signal WA _ ENX for use by the auxiliary voltage generation module 64 of fig. 11. When V4OK is equal to 1, the analysis path of V3 and below is turned off, and V3OK, V2OK, V1OK are set to 0, and Vmin is set to 0. If the voltage level of V4 is not sufficient to turn on NE4, V4OK will be latched at 0 by PFB4 and turn on the V3 analysis path. PFB4 and NFB4 together latch eval values in each analysis path, preventing loss of voltage identification results after the voltage identification module is shut down.

The V3, V2, V1 paths are similar in principle to the V4 path. Only the set MOS and the transmission gate are added. If the V3 path has an extra PMOS PRST3, this MOS is used to set V3OK to 0 when V4OK is equal to 1. The transmission gate turns off V3 to open the path of NE3 when V4OK is equal to 1. The addition of the set MOS and the transfer gate means in a design sense that when the voltage interval is recognized as V4 (the most significant interval), the lower interval does not need to be judged and analyzed any more. NEN3 sets the input of NE3 to 0 when the transmission gate is turned off, preventing the generation of a floating network.

During voltage identification, the highest voltage identification code can be calculated, and if the highest voltage identification code is effective, an auxiliary circuit does not need to be started to generate negative pressure impact; if the highest voltage identification code is not valid, the identification level may be sequentially lowered until a certain bit of the voltage identification code is considered valid. For example, V4, V3, V2, and V1 may be sequentially analyzed until V4OK ═ 1, V3OK ═ 1, V2OK ═ 1, or V1OK ═ 1 appears, which sequentially represents that the current voltage is in the highest voltage, second highest voltage, middle voltage, and low voltage intervals, and the corresponding negative voltage amplitude is not turned on, weak amplitude, middle amplitude, and maximum amplitude. If none of the above VOK changes from initial state 0 to 1. Then Vmin will become 1. Indicating that the current power source identification is in the lowest voltage interval. The maximum negative pressure amplitude needs to be opened.

Specifically, as shown in fig. 14, if the voltage identifier V4 at the highest bit is valid (i.e., V4 is high enough to turn on NE4), V4OK is equal to 1, and V3, V2, V1, and Vmin stop the determination, and V4OK is equal to 1, which indicates that the current voltage is in the negative voltage section that does not need to be turned on. If V4 is not active (i.e. V4 is low and is not enough to turn on NE4), V4OK is 0, and it is necessary to turn on the auxiliary circuit to generate negative voltage, and it is necessary to continue to determine whether V3 is active. Referring to fig. 15, if V3 is active, V3OK is 1, which indicates that the voltage is in a higher interval, and the negative voltage to be turned on only needs a small amplitude; if V3 is invalid, V3OK is 0, and V2 needs to be determined continuously, as shown in fig. 16. And so on until V1 is determined. Referring to fig. 17, if V1 is active, a greater negative pressure magnitude is turned on, and if V1 is inactive, Vmin is 1 as shown in fig. 18. Vmin represents turning on all coupling capacitors for negative voltage surge.

The state is decoded (state s 2). The code generated by the identification state can be decoded to obtain the auxiliary channel required for generating the auxiliary voltage. For example, the combinations of V3OK, V2OK, V1OK and Vmin may be encoded and decoded to obtain the gate signals WA3, WA2 and WA1 of the auxiliary channel. V4OK may generate a negative pressure enable signal WA _ ENX (see fig. 14).

The dc path closed state (state s 3). After a period of time, the voltage identification code generated by the negative voltage code generated by s1 is considered to be stable and effective, and the voltage identification code can reflect the real working voltage. At this time, the V4OK and the V3ok.. Vmin output from s1 may be logically operated, and the operation result may be returned to s1, and the dc path existing in the voltage identification module may be closed by the Disable signal, so as to reduce the power consumption of the identification circuit. The recognized voltage identification code is latched by a latch unit in the circuit, and the subsequent negative voltage programming is continuously performed. Fig. 19 is a circuit embodiment for turning off the dc path. As shown in fig. 19, when the word line WL power voltage is recognized, it is considered that the voltage recognition block can be turned off for the purpose of saving power consumption. The time delay unit is added in the circuit to fully identify and analyze the voltage, so that after each analysis path latches a corresponding voltage analysis value, a direct current path of the voltage identification module is cut off.

The auxiliary voltage state is not turned on (state s 4). The circuit for generating negative pressure coding according to VOK consists of NR1/NR2/NR3/IN1/XD1/XD2/XD 3. When V4OK is equal to 1, WA [3:1] ═ 111, WA _ ENX is equal to 1 under clock enable, and no negative pressure is generated.

The auxiliary voltage state is turned on (s 5). When V4OK is equal to 0, WA [3:1] generates negative pressure of corresponding magnitude from the above item 4, respectively. If V3OK is 1, WA [3:1] = 011; if V2OK is equal to 1, WA [3:1] ═ 001; if V1OK is equal to 1, WA [3:1] ═ 000; if V3OK/V2OK/V1OK are both 0 and Vmin is 1, WA [3:1] is 000, as with V1OK, the maximum magnitude negative pressure is turned on.

In a second aspect, correspondingly, embodiments of the present invention further provide a working method of a write assist apparatus, which can effectively improve the operation efficiency and the adaptability of write assist.

As shown in fig. 20, an operating method of a write assist apparatus according to an embodiment of the present invention may include:

s71, identifying a voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

and S72, generating an auxiliary voltage according to the target voltage interval, and writing the data to be written into the target position with the aid of the auxiliary voltage.

According to the working method of the write assist device provided by the embodiment of the invention, the voltage interval where the monitored voltage is located is identified from the preset voltage interval set to obtain the target voltage interval, and the assist voltage is generated according to the target voltage interval so as to write the data to be written into the target position with the assistance of the assist voltage. Therefore, the appropriate auxiliary voltage required by the write auxiliary device during data write operation can be determined in time according to the actual size of the monitored voltage in the actual work of the circuit, the auxiliary voltage can be generated in time, complex test operation is not needed, and the auxiliary voltage can be applied to various scenes, so that the write auxiliary efficiency and the adaptability are effectively improved.

Optionally, identifying the voltage interval where the monitored voltage is located from the preset voltage interval set in step S71, and obtaining the target voltage interval may specifically include:

dividing the monitored voltage and then passing through at least one output channel, wherein the output voltage of each output channel is divided into one part of the monitored voltage, and the output voltages of the output channels are not equal to each other;

and identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set according to the relation between the output voltage of each output channel and a preset threshold value to obtain a target voltage interval.

Optionally, identifying, according to a relationship between the output voltage of each output channel and a preset threshold, a voltage interval in which the monitored voltage is located from the preset voltage interval set may include:

comparing the output voltage of each output channel with the preset threshold value according to a preset sequence;

and in the case that the output voltage of one output channel is determined to be larger than the preset threshold value, abandoning the comparison operation of the subsequent output channel.

Optionally, in step S72, generating the auxiliary voltage according to the target voltage interval may include:

according to the target voltage interval, gating an auxiliary channel required by generating the auxiliary voltage;

the auxiliary voltage is generated through the auxiliary channel.

Optionally, the gating of the auxiliary channel required for generating the auxiliary voltage according to the target voltage interval may include:

respectively establishing coding-gating corresponding relations for each target voltage interval and the auxiliary channels corresponding to the target voltage intervals, wherein each target voltage interval correspondingly gates 0 or one or more auxiliary channels;

and gating an auxiliary channel required for generating the auxiliary voltage according to the coding-gating corresponding relation.

Optionally, after the voltage interval in which the monitored voltage is located is identified from the preset voltage interval set, and after the target voltage interval is obtained, and before the auxiliary voltage is generated according to the target voltage interval, the operating method of the write-assist device provided in the embodiment of the present invention may further include: and latching the target voltage interval.

Optionally, after identifying the voltage interval in which the monitored voltage is located from the preset voltage interval set and obtaining the target voltage interval, the operating method of the write assist device provided in the embodiment of the present invention may further include: and stopping the identification of the monitored voltage according to the identified target voltage interval.

The specific circuit structure and operation process of the write assist device provided in the embodiment of the present invention based on any one of the write assist devices provided in the foregoing embodiments have been described in the foregoing, and are not described again here.

In a third aspect, correspondingly, an embodiment of the present invention further provides a memory, where any one of the write assist apparatuses provided in the foregoing embodiments of the present invention is disposed in the memory, so that corresponding beneficial technical effects can also be produced.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.

In particular, as for the apparatus embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

For convenience of description, the above devices are described separately in terms of functional division into various units/modules. Of course, the functionality of the units/modules may be implemented in one or more software and/or hardware implementations of the invention.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A write assist apparatus, comprising:

the voltage identification part is connected with the monitored voltage at one end and the auxiliary voltage generation part at the other end, and is used for identifying a voltage interval where the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

and the auxiliary voltage generating part is connected with the voltage identification part at one end and connected with a write data transmission part at the other end, and is used for generating auxiliary voltage according to the target voltage interval and applying the auxiliary voltage to the write data transmission part so as to assist the write data transmission part to write data to be written into a target position.

2. The write assist apparatus according to claim 1, wherein the voltage identifying section includes:

the input end of the voltage division module is connected with the monitored voltage, the output end of the voltage division module comprises at least one output channel, the output voltage of each output channel is divided by the monitored voltage, and the output voltages of the output channels are not equal to each other;

and the identification module is connected with the voltage division module and used for identifying the voltage interval where the monitored voltage is located from the preset voltage interval set according to the relation between the output voltage of each output channel of the voltage division module and a preset threshold value to obtain a target voltage interval.

3. The write assist device according to claim 2, wherein the identification module is specifically configured to:

comparing the output voltage of each output channel of the voltage division module with the preset threshold value according to a preset sequence;

4. The write assist apparatus according to claim 1, wherein the assist voltage generating section includes:

the decoding module is connected with the voltage identification part and used for gating an auxiliary channel required by generating the auxiliary voltage according to the target voltage interval identified by the voltage identification part;

and the generating module is connected with the decoding module and used for generating the auxiliary voltage through the auxiliary channel gated by the decoding module.

5. The write assist device of claim 4, wherein the decode module is specifically configured to:

6. The write assist apparatus of claim 4 wherein the decode module comprises a first logic gate; the generation module includes at least one of the auxiliary channels, each of which includes a second logic gate and a capacitor connected in series with the second logic gate.

7. The write assist apparatus according to claim 1, further comprising: and the latch part is connected with the voltage identification part at one end and the auxiliary voltage generation part at the other end and is used for latching the target voltage interval identified by the voltage identification part.

8. The write assist apparatus according to claim 1, wherein the voltage identification unit is further configured to close a dc path thereof according to the identified target voltage interval.

9. The write assist apparatus of claim 1 wherein the monitored voltage comprises at least one of: a first power supply voltage for supplying a write strobe signal to the write data transfer section; a first node voltage having a preset logic level under a preset condition.

10. The write assist apparatus of claim 1, wherein the assist voltage comprises a surge voltage.

11. The write assist apparatus of claim 1, wherein the target location comprises at least one of: target register, target memory location, target port.

12. The write assist device according to any one of claims 1 to 11, wherein the write data transfer section is provided with a write enable terminal, a data input terminal, a data output terminal; the data output end is connected with the target position;

the auxiliary voltage generating part is connected with the data input end and used for generating a first auxiliary voltage according to the target voltage interval identified by the voltage identification part and applying the first auxiliary voltage to the data input end, wherein the polarity of the first auxiliary voltage is opposite to that of the voltage of the write gating end;

and/or the presence of a gas in the gas,

the auxiliary voltage generating part is connected with the write-in gating end and used for generating a second auxiliary voltage according to the target voltage interval identified by the voltage identification part and applying the second auxiliary voltage to the write-in gating end, wherein the polarity of the second auxiliary voltage is the same as that of the write-in gating end.

13. A method of operating a write assist device, comprising:

identifying a voltage interval in which the monitored voltage is located from a preset voltage interval set to obtain a target voltage interval;

and generating an auxiliary voltage according to the target voltage interval so as to write the data to be written into the target position with the aid of the auxiliary voltage.

14. The method of claim 13, wherein identifying the voltage interval in which the monitored voltage is located from the set of preset voltage intervals, and obtaining the target voltage interval comprises:

15. The method of claim 14, wherein identifying the voltage interval in which the monitored voltage is located from the set of preset voltage intervals according to the relationship between the output voltage of each of the output channels and the preset threshold comprises:

16. The method of claim 13, wherein generating the auxiliary voltage according to the target voltage interval comprises:

the auxiliary voltage is generated through the auxiliary channel.

17. The method of claim 16, wherein gating the auxiliary channel required to generate the auxiliary voltage according to the target voltage interval comprises:

18. The method of claim 13, wherein after identifying the voltage interval in which the monitored voltage is located from the preset set of voltage intervals to obtain the target voltage interval, and before generating the auxiliary voltage according to the target voltage interval, the method further comprises:

and latching the target voltage interval.

19. The method of claim 13, wherein after identifying the voltage interval in which the monitored voltage is located from the preset set of voltage intervals to obtain the target voltage interval, the method further comprises: and stopping the identification of the monitored voltage according to the identified target voltage interval.

20. A memory, characterized in that the write assist apparatus of any one of claims 1-12 is provided in the memory.