CN113314174A - Circuit structure for column shift multi-bit multiplication binary decomposition operation of SRAM array - Google Patents
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Abstract
The invention discloses a circuit structure for column shift multi-bit multiplication binary decomposition operation of an SRAM array, which comprises the SRAM array consisting of N columns of 6T SRAM units, a switch group consisting of K switches Sk and a storage capacitor group Cm consisting of M storage capacitors; the binary bits of the multiplicand X are stored in the adjacent n 6T SRAM units in the same row; the binary bits of the multiplier Y are represented in the form of combinations of word line enable pulses; the high and low bits correspond to storage positions, and the bit line displacement among the storage capacitors is completed by a switch group consisting of K switches Sk; and the storage of the multiplication result is completed by a storage capacitor group Cm formed by M storage capacitors. The circuit can be used for correctly finishing multi-bit multiplication, simultaneously ensuring the voltage difference of the high LSB, simplifying the setting of a multiplier, enhancing the identifiability of an A/D module and expanding the operation number.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a circuit structure for column shift multi-bit multiplication binary decomposition operation of an SRAM (Static Random Access Memory, abbreviated as SRAM) array.
Background
With the expansion of artificial intelligence technology to multi-type equipment for application, the requirements on computing efficiency and energy consumption are higher and higher, an operation module and a memory in a traditional von neumann architecture are separated, when data needs to be used, the data needs to be read from the memory to the operation module, the operation force development process of the current operation module is far beyond the development process of the memory access speed, a large amount of running time and power consumption are used for data access, and the part actually used for operation is few. As one of effective strategies for breaking through the von neumann architecture, memory Computing (CIM) attracts wide attention, and memory computing combines a memory and an operation module into a whole, so that data movement is greatly reduced, and time and energy consumption overhead of the part are further saved.
In the prior art, operations such as addition, subtraction, multiplication and the like can be performed in the field of SRAM memory calculation, but the defects cannot be ignored, such as long operation period, tedious peripheral circuits, large operation power consumption, poor calculation precision and the like, so that an efficient and concise operation circuit solution capable of ensuring high precision is urgently needed.
Disclosure of Invention
The invention aims to provide a circuit structure for column shift multi-bit multiplication binary decomposition operation of an SRAM array, which can be used for correctly finishing multi-bit multiplication operation, simultaneously ensuring the voltage difference of a high-Least Significant Bit (LSB), simplifying the setting of a multiplier, enhancing the identifiability of an analog-to-digital (A/D) module and expanding the operation digit.
The purpose of the invention is realized by the following technical scheme:
a circuit arrangement for a column-shifting multi-bit multiplication binary decomposition operation of an SRAM array, the circuit comprising an SRAM array of N columns of 6T SRAM cells, a switch bank of K switches Sk, a storage capacitor bank Cm of M storage capacitors, wherein:
controlling and connecting a bit line BLB of the SRAM array and the storage capacitor group Cm through the switch group;
determining 6T SRAM units in a specified number of columns according to the multiplicand and the digit of the multiplier, wherein the 6T SRAM units in the specified number of columns correspond to a storage capacitor set Cm, and the number of storage capacitors in the storage capacitor set Cm is determined by the highest support digit of the operation result;
the binary bits of the multiplicand X are stored in the adjacent n 6T SRAM units in the same row;
the binary bits of the multiplier Y are represented in the form of combinations of word line enable pulses;
high-low data storage at corresponding positions is completed through the switch group and the storage capacitor group Cm, and the bit line displacement among the storage capacitors is completed through the switch group formed by K switches Sk; one end of Sk is connected with a bit line, the other end of Sk is connected with the upper end of each storage capacitor, the lower end of each storage capacitor is connected with a common ground terminal voltage VSS, and in the operation process, corresponding word line pulses and corresponding bit line shift signals are enabled to generate corresponding voltage differences on the storage capacitors;
the storage of the multiplication result is completed by a storage capacitor group Cm formed by M storage capacitors, and the storage capacitor group Cm corresponds to a binary group z formed by N binary numbers of the multiplication resultn(ii) a Wherein, what is stored on each storage capacitor in the storage capacitor group Cm is the least significant bit LSB voltage difference quantity which represents the counting value.
The technical scheme provided by the invention can be seen that the circuit can be used for correctly finishing the multi-bit multiplication operation, simultaneously ensuring the high LSB voltage difference, simplifying the setting of a multiplier, enhancing the identifiability of an A/D module and expanding the operation digit.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of a column shift multi-bit multiplication binary decomposition operation for an SRAM array according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a working waveform of the circuit according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of word line encoding of a 6T SRAM cell and a multiplier according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing the sequence of encoding and Sk enabling right word line WLR pulses of each column of the circuit according to the embodiment of the present invention;
fig. 6 is a schematic diagram illustrating a corresponding binary operation process stored at the upper end of the storage capacitor according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
The circuit of the embodiment of the invention converts unsigned decimal number multiplication into binary number multiplication, disperses the multiplication result to exist at the upper end of the capacitor corresponding to the weight in a counting mode, can expand the digits of a multiplier and a multiplicand, can also ensure a high LSB voltage difference value, and is convenient for the identification of an A/D module. In the following, embodiments of the present invention will be described in further detail with reference to the accompanying drawings, and as shown in fig. 1, a schematic circuit structure diagram of a column shift multi-bit multiplication binary decomposition operation for an SRAM array according to an embodiment of the present invention is provided, where the circuit includes an SRAM array composed of N columns of 6T SRAM cells, a switch group composed of K switches Sk, and a storage capacitor group Cm composed of M storage capacitors, where:
controlling and connecting a bit line BLB of the SRAM array and the storage capacitor group Cm through the switch group;
as shown in fig. 2, which is a partial enlarged schematic diagram of the circuit according to the embodiment of the present invention, a specified number of rows of 6T SRAM cells are determined according to the number of bits of the multiplicand and the multiplier, the specified number of rows of 6T SRAM cells corresponds to one storage capacitor bank Cm, and the number of storage capacitors in the storage capacitor bank Cm is determined by the highest supported bit number of the operation result;
the binary bits of the multiplicand X are stored in the adjacent n 6T SRAM units in the same row;
the binary bits of the multiplier Y are represented in the form of combinations of word line enable pulses;
high-low data storage at corresponding positions is completed through the switch group and the storage capacitor group Cm, and the bit line displacement among the storage capacitors is completed through the switch group formed by K switches Sk; one end of Sk is connected to a bit line, the other end of Sk is connected to the upper end of each storage capacitor, and the lower end of each storage capacitor is connected to a common ground voltage VSS (VSS for short), as shown in fig. 3, which is a schematic diagram of a working waveform of the circuit according to the embodiment of the present invention, during the operation, a corresponding word line pulse and a corresponding bit line shift signal are enabled, and a corresponding voltage difference is generated on each storage capacitor;
the storage of the multiplication result is completed by a storage capacitor group Cm formed by M storage capacitors, and the storage capacitor group Cm corresponds to a binary group z formed by N binary numbers of the multiplication resultn(ii) a Wherein, the voltage difference quantity of the least significant bit LSB representing the counting value is stored on each storage capacitor in the storage capacitor group Cm, not the counting valueThereby reducing the difficulty of A/D design.
Further, as shown in fig. 4, a word line coding diagram of the 6T SRAM cell and the multiplier according to the embodiment of the present invention is shown, where a binary bit of the multiplier Y is represented in a word line enable pulse combination form, specifically:
the 6T SRAM unit of the double word line is formed by 6 transmission tubes, the combination of 2 pairs of NMOS tubes and PMOS tubes forms two cross-coupled inverters, one end of the inverter is connected with Q, and the other end of the inverter is connected with QB;
the word line signals WLL and WLR form a double word line signal, and control switches of the two NMOS tubes are respectively connected with the word line signals WLL and WLR;
the multiplier Y is represented by K pulses of WLR, a single high-level pulse YkWhen the corresponding cell QB is 0, a unit voltage difference Δ V is generated.
In addition, as shown in fig. 5, a schematic diagram of the sequence of the encoding of the right word line WLR pulse and the Sk enabling of the right word line WLR pulse in each column of the circuit according to the embodiment of the present invention is shown, the word line signal WLR setting in each column is different, and the on and off of the switch group formed by the K switches Sk are set according to the weight, specifically:
corresponding binary number z1To z6The weights on the storage capacitors C1-C6 are 1,2, 4, 8, 16, 32, respectively, and the specific weight values are represented by the positions of the storage capacitors;
as shown in fig. 6, which is a schematic diagram illustrating a corresponding binary operation process stored at the upper end of the storage capacitor according to the embodiment of the present invention, the binary number is stored at the upper end of the designated storage capacitor by turning on and off the switch Sk; for example, switches S1 and S4 are open, and the remaining Sk are closed, resulting in a binary number z1And z4The result of the binary operation above is stored in the upper end of the assigned storage capacitors C1 and C4.
Limited by space, FIG. 5 shows the word line signal WLR for a 4bit by 3bit multiplication and the on and off settings of the switch Sk.
In addition, when the capacitance values of the storage capacitors in the storage capacitor group Cm are set, parasitic capacitors need to be considered, so that the difference value of the LSB voltage difference of each storage capacitor is consistent; meanwhile, due to charge sharing of the capacitors, storage of discharged quantities between different columns on the same storage capacitor should be performed simultaneously.
The operation process of the circuit provided by the embodiment of the invention specifically comprises the following steps:
before the operation starts, N-bit binary digits of a multiplicand X are stored into N adjacent 6T SRAM units in the same row, Q points are the same as corresponding binary digits, and QB points are inverted; the right word line BLB and the storage capacitor set Cm are precharged to VDD. The basic pulse combination is determined from the binary number representation of the multiplier Y.
The operation is started, firstly, the weight of the storage capacitor is represented by different positions of the storage capacitor, the storage capacitors corresponding to different weight bits complete the whole operation in a plurality of sub-periods, in order to enable the operation efficiency to reach the maximum, a specific switch Sk needs to be turned on in the same sub-period, so that the WLRs on the N columns are enabled correctly, for example, 4bit multiplied by 3bit multiplication, and in the 1 st sub-period, S1 is enabled, the WLRs on the 1 st column are enabled according to y1Enable, C1 completes the operation on the corresponding weight. Since columns 2-4 can also complete the operations on the weights corresponding to C4 without disturbing the operations on C1, S1 and S4 can be enabled simultaneously, but the right word line WLR on each column needs to be enabled to operate on corresponding binary bits according to the requirement shown in FIG. 5.
After the sub-periods are completed, the upper end of the storage capacitor group Cm represents the upper end of the capacitor of each weight, and the voltage difference accumulation of the corresponding number of LSBs generated by the binary multiplication of the corresponding weights is completed.
And accumulating and converting the LSB voltage difference stored by each storage capacitor into a count value of a digital domain through conversion of an A/D module, and multiplying and accumulating the count value and the corresponding high-low bit weight value to obtain a final multiplication result.
For space, only a single multi-bit multiply operation is shown, but the bank of storage capacitors Cm can store the multiply-accumulate value of n multi-bit multiply operations when the rows are on.
In order to show the operation process of the circuit of the present invention more clearly, the following description takes 4bit × 3bit multiplication as a structural sample and 15 × 5 as an embodiment sample:
because the multiplicand is 4 bits, the multiplier is 3 bits, and the operation result is supported to the 6 th bit at most, 1 storage capacitor group Cm is matched with 4 columns of 6T SRAM units in the array, the storage capacitor group Cm comprises 6 storage capacitors, the storage capacitors are connected with 3bit lines at most, and 3 times of shift is required to be carried out between the storage capacitors on a single bit line, so that the single bit line is connected with 3 shift switches.
Before the operation starts, the binary number of multiplicand X15 is stored in the array as shown in fig. 1, X4～x11111, Q of these 4 cells is 1111 and QB is 0000. The upper ends of the storage capacitors C1-C6 and the right bit lines of all the columns are precharged to VDD; the binary number of multiplier Y is 5 is 101, and the basic pulse combination Y3y2y1Set to 101.
When the operation starts, 6 capacitors corresponding to different weight bits complete the whole operation in 3 sub-periods. Referring to figures 1, 3 and 5:
the 1 st sub-period, S1, S4 enable, the word lines of the 1 st to 4 th columns according to y1y2y3y1By performing the enabling, C1 and C4 complete the operation on the corresponding weight.
In the sub-period 2, S2 and S5 are enabled, and the word lines in the 1 st to 4 th columns are according to y2y3y1y2By performing the enabling, C2 and C5 complete the operation on the corresponding weight.
The 3 rd sub-period, S3, S6 enable, the word lines of the 1 st to 4 th columns according to y3y1y2y3By performing the enabling, C3 and C6 complete the operation on the corresponding weight.
After the operation is finished, as shown in fig. 3, the number of LSB voltage differences accumulated in C6 to C1 matches the binary multiply-accumulate result at the corresponding position. Converting the number of LSB voltage differences accumulated on C6-C1 into count values of a digital domain through an A/D module, wherein the count values are 1,1,2,2,1 and 1 respectively; the count value is multiplied by the corresponding high and low weight values and accumulated, that is, 1 × 32+1 × 16+2 × 8+2 × 4+1 × 2+1 × 75, and the final multiplication result obtained is the same as the 15 × 5 theoretical calculation result 75.
It is noted that those skilled in the art will recognize that embodiments of the present invention are not described in detail herein.
In summary, the circuit structure of the present invention has the following advantages:
1. compared with the prior art that the voltage difference representing the multiplication result is stored at one point, the invention stores the part of the voltage difference at each corresponding weight value point separately, thus the LSB value and the identification of the A/D module can be greatly expanded.
2. The word line on pulse representing the multiplier eliminates the need to quantify the word line on time, voltage, etc., simplifying setup.
3. The counting value is stored in each storage point instead of the conventional calculation numerical value, so that the quantization difficulty is reduced.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A circuit arrangement for a column-shifting multi-bit multiplication binary decomposition operation of an SRAM array, the circuit comprising an SRAM array of N columns of 6T SRAM cells, a switch bank of K switches Sk, a storage capacitor bank Cm of M storage capacitors, wherein:
controlling and connecting a bit line BLB of the SRAM array and the storage capacitor group Cm through the switch group;
determining 6T SRAM units in a specified number of columns according to the multiplicand and the digit of the multiplier, wherein the 6T SRAM units in the specified number of columns correspond to a storage capacitor set Cm, and the number of storage capacitors in the storage capacitor set Cm is determined by the highest support digit of the operation result;
the binary bits of the multiplicand X are stored in the adjacent n 6T SRAM units in the same row;
the binary bits of the multiplier Y are represented in the form of combinations of word line enable pulses;
high-low data storage at corresponding positions is completed through the switch group and the storage capacitor group Cm, and the bit line displacement among the storage capacitors is completed through the switch group formed by K switches Sk; one end of Sk is connected with a bit line, the other end of Sk is connected with the upper end of each storage capacitor, the lower end of each storage capacitor is connected with a common ground terminal voltage VSS, and in the operation process, corresponding word line pulses and corresponding bit line shift signals are enabled to generate corresponding voltage differences on the storage capacitors;
the storage of the multiplication result is completed by a storage capacitor group Cm formed by M storage capacitors, and the storage capacitor group Cm corresponds to a binary group z formed by N binary numbers of the multiplication resultn(ii) a Wherein, what is stored on each storage capacitor in the storage capacitor group Cm is the least significant bit LSB voltage difference quantity which represents the counting value.
2. The circuit structure of claim 1, wherein the binary bits of the multiplier Y are represented in the form of combinations of word line enable pulses, in particular:
the 6T SRAM unit of the double word line is formed by 6 transmission tubes, the combination of 2 pairs of NMOS tubes and PMOS tubes forms two cross-coupled inverters, one end of the inverter is connected with Q, and the other end of the inverter is connected with QB;
the word line signals WLL and WLR form a double word line signal, and control switches of the two NMOS tubes are respectively connected with the word line signals WLL and WLR;
the multiplier Y is represented by K pulses of WLR, a single high-level pulse YkWhen the corresponding cell QB is 0, a unit voltage difference Δ V is generated.
3. The circuit structure of claim 1, wherein during operation, the word line signal WLR setting of each column is different, and the turning on and off of the switch group of K switches Sk is set according to the weight, specifically:
corresponding binary number z1To z6The weights of the storage capacitors C1-C6 are 1,2, 4, 8, 16, 32 respectively, and the specific weight values are obtained by storing electricityThe position of the container;
and the on and off of the switch Sk enables the binary number to be stored in the upper end of the designated storage capacitor.
4. The circuit structure for a column-shift multi-bit multiplicative binary decomposition operation for an SRAM array of claim 1,
when the capacitance values of the storage capacitors in the storage capacitor group Cm are set, parasitic capacitors need to be considered, and the difference value of the LSB voltage difference of each storage capacitor is consistent; and because of the charge sharing of the capacitors, the storage of the discharged amount between different columns on the same storage capacitor should be done simultaneously.
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