CN113300800A - Multi-mode deterministic data processing device and method - Google Patents

Multi-mode deterministic data processing device and method Download PDF

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CN113300800A
CN113300800A CN202110847351.6A CN202110847351A CN113300800A CN 113300800 A CN113300800 A CN 113300800A CN 202110847351 A CN202110847351 A CN 202110847351A CN 113300800 A CN113300800 A CN 113300800A
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CN113300800B (en
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赵许阳
杨汶佼
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Zhejiang Lab
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/0635Clock or time synchronisation in a network
    • H04J3/0638Clock or time synchronisation among nodes; Internode synchronisation
    • H04J3/0658Clock or time synchronisation among packet nodes
    • H04J3/0661Clock or time synchronisation among packet nodes using timestamps
    • H04J3/0667Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/08Configuration management of networks or network elements
    • H04L41/0803Configuration setting
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L67/00Network arrangements or protocols for supporting network services or applications
    • H04L67/01Protocols
    • H04L67/12Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks

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Abstract

The invention discloses a multi-mode deterministic data processing device and a method, which mainly solve the problem of deterministic data transmission of a time-sensitive network and ensure the compatibility of the traditional industrial equipment, and by providing the multi-mode deterministic data processing device, the deterministic function of uplink data transmission mainly suitable for field-level end equipment is realized in a CPU mode; the method is mainly suitable for the data exchange function of the factory-level network in the non-CPU mode. Through realizing the configuration of different modes, can effectually reform transform the upgrading in current industrial equipment for data transmission reliability, security and real-time in the network obtain promoting.

Description

Multi-mode deterministic data processing device and method
Technical Field
The invention relates to the technical field of time sensitive networks of industrial control systems, in particular to a multi-mode deterministic data processing device and a multi-mode deterministic data processing method.
Background
The development era of the internet of things (IIoT) in industry encounters various difficulties, the most typical difficulty of which is that the industrial field-level environment has a very rich field bus and various application protocols, so that the data access of the IT layer to the field must pass through different drivers or add conversion devices between different protocols, and meanwhile, in a traditional network domain, the real-time performance and reliability of data transmission between different devices are low, and the network obstacles in horizontal integration are difficult to eliminate. With the development of industrial internet technology, some safety related data related in the system have the requirements of low delay and high certainty, meanwhile, the tolerance requirement of the safety related data on frame loss or mistransmission is lower and lower, and the transmission complexity problem of the traditional industrial field causes that the integration of IT and OT in IIoT and intelligent manufacturing promotion is difficult to realize perfectly.
Data transmission of traditional industrial field level equipment is based on QoS transmission, the real-time performance of the data transmission is limited, the reliability of the data transmission is low, and with the increase of field level access equipment, the coexistence of available bandwidth and different flow types becomes an important problem of an uplink channel of a factory backbone network. When time-critical traffic and background traffic share the same network infrastructure, standard ethernet does not provide reliable real-time guarantees.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a multi-mode deterministic data processing apparatus and method, which solves the problems set forth in the background art.
In order to achieve the purpose, the invention is realized by the following technical scheme: a multi-mode deterministic data processing device comprises a CPU, and a POR module, a clock management module, a power management module, a storage module, a data interface, a debugging interface, a DDR module, a TSN Switch, a TSN network port and a DP interface which are connected with the CPU;
the apparatus has 5 external interfaces MAC0, swp0, swp1, swp2, swp 3; the CPU has 4 internal Ethernet controllers Eth0, Eth1, Eth2, Eth 3; eth0 interfaces MAC0 via SGMII interface; swp0, swp1, swp2 and swp3 are connected with controllers inside the TSN Switch through QSGMII interfaces, and the controllers inside the TSN Switch are connected with Eth2 and Eth3 of the CPU.
Preferably, the storage module comprises a NAND/NOR storage, an SD storage and an eMMC storage, and is used for storing bootloaders, kernel, file systems and toolkits of the device, and providing operating system files for device operation.
Preferably, the data interface module is used for exchanging external data and comprises a wired interface and a wireless interface, the wired interface comprises USB type a, USB type c, RS232 and CAN, and the wireless interface comprises 4G/WIFI.
Preferably, the CPU adopts Cortex-A72, the main frequency is 1.3GHz, 64 bits 1MB L2 buffer memory is provided with ECC protection; the POR module is a power-on reset configuration module and is used for initializing the function configuration of pins of the equipment and realizing the function starting of the equipment according to the pins designed in advance; the clock management module and the power supply management module are used for providing a standard clock and a power supply for normal operation of the equipment and ensuring that the power-on and power-off time sequence of the power supply meets the requirements of the equipment; the debugging interface module is a JTAG interface and is used for providing an external debugging interface for the CPU; the DDR module has a master frequency of 1.6GT/S and is used for providing data calculation processing of an external interface and a CPU; the DP interface module is mainly used for processing and converting video data.
The invention also provides a multi-mode deterministic data processing method, which comprises a CPU mode and a non-CPU mode, wherein in the CPU mode, a user uses a network equipment interface or a network bridge interface of a switch port, and adds a user-defined time-sensitive network function into a conventional Ethernet message by adopting the functions of frame injection and frame analysis; in the non-CPU mode, the device does not have the function of converting a conventional ethernet packet into a time-sensitive network packet, and the user needs to use the same peer port to send and receive packets.
Preferably, the CPU modes include a non-bridge CPU mode and a bridge CPU mode.
Wherein the non-bridging CPU mode comprises the steps of:
(a1) downloading the port configuration file in the non-bridge mode into a storage module;
(a2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting, configuring IP addresses of the ports as different network segments, and up connecting Eth3 ports of a CPU;
(a3) the four ports are respectively accessed into different Remote Host computers, wherein swp0 is consistent with a Remote Host1, swp1 is consistent with a Remote Host2, swp2 is consistent with a Remote Host3, and swp3 is consistent with a Remote Host 4;
(a4) the different Remote Host ping ports can pass through.
Wherein, the bridge CPU mode comprises the following steps:
(b1) downloading a port configuration file in a bridge CPU mode into a storage module;
(b2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting is completed, configuring IP addresses of the ports as different network segments, and up connecting Eth2 and Eth3 ports of a CPU;
(b3) configuring a Remote Host to be 192.168.0.1 connected to swp3, simultaneously configuring swp0, swp1, swp2 and swp3 ports under a bridge space, and configuring the IP of the whole bridge to be 192.168.0.2;
(b4) the Eth2 port of the CPU is configured to be 192.168.0.3, which is a data channel for data transmission, and the Eth3 of the CPU is a data channel for control command transmission, and is not configured;
(b5) any of the ports through swp0, swp1, swp2, swp3 may ping directly through the Eth2 port.
Aiming at the problems that the current industrial network is layered and heterogeneous and is difficult to flexibly and efficiently interconnect and intercommunicate, an industrial heterogeneous converged network architecture based on a time sensitive network is constructed. Establishing a model according to macroscopic operations such as matching, analyzing and forwarding of a data surface to a data packet, providing an accurate execution mechanism of equipment on a time dimension, and providing framework support for deterministic transmission according to time through a service requirement of a north interface docking of centralized network control equipment; by means of a framework with decoupled management plane and forwarding plane, the dynamic adaptation of the network to various and changing industrial services is realized, and the dynamic reconfiguration of the network is supported.
The industrial network mainly adopts an OPC UA TSN communication framework, wherein the OPC UA mainly solves the problem of safe semantic interoperation, ensures that data in a heterogeneous network can be defined according to a uniform standard, mainly focuses on three layers of application, conversation and representation of an ISO/OSI model, establishes connection, and expresses 'equipment regulations' in an application scene by using a uniform information model specification. The TSN solves the same network transmission problem of "real-time" and "non-real-time" data, mainly focuses on the data link layer of the ISO/OSI model, and mainly solves the problems of clock synchronization, data scheduling, and network configuration. The OPC UA TSN solves the problem of transmission complexity of the traditional industrial field, so that OT and IT fusion in the intelligent manufacturing process is perfectly realized.
The invention provides a multi-mode deterministic data processing device and a method, mainly aims to solve the problem of deterministic data transmission of a time-sensitive network and simultaneously ensures the compatibility of the traditional industrial equipment, and the multi-mode deterministic data processing device is mainly suitable for realizing the deterministic function of data uplink transmission of field-level end equipment in a CPU mode; the method is mainly suitable for the data exchange function of the factory-level network in the non-CPU mode. Through realizing the configuration of different modes, can effectually reform transform the upgrading in current industrial equipment for data transmission reliability, security and real-time in the network obtain promoting.
Drawings
FIG. 1 is a schematic block diagram of the present invention;
FIG. 2 is a diagram of the framework of the network port and CPU of the present invention;
FIG. 3 is a schematic interface diagram of the non-bridge CPU mode of the present invention;
FIG. 4 is a schematic diagram of the interface of the bridge CPU mode according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
1-2, a multi-mode deterministic data processing apparatus includes Cortex-A72 and POR module connected with Cortex-A72, clock management module, power management module, NAND/NOR storage, SD storage and eMMC storage, USB type A, USB type C, RS232, CAN, 4G/WIFI, JTAG interface, DDR4, L2 Switch, TSN portal, DP interface.
The POR module is a power-on reset configuration module and is used for initializing the function configuration of pins of the equipment and realizing the function starting of the equipment according to the pins designed in advance; the clock management module and the power supply management module are used for providing a standard clock and a power supply for normal operation of the equipment and ensuring that the power-on and power-off time sequence of the power supply meets the requirements of the equipment; the NAND/NOR storage, the SD storage and the eMMC storage are used for storing bootloaders, kernel, file systems and toolkits of the equipment, and operating system files are provided for equipment operation; the USB type A, the USB type C, the RS232, the CAN and the 4G/WIFI provide abundant external data exchange interfaces, and the application of various industrial protocols is realized; the JTAG interface provides an external debugging interface of Cortex-A72; the main frequency of Cortex-A72 is 1.3GHz, 64 bits of 1MB L2 buffer memory is provided with ECC protection, and the processing of a large amount of industrial field data can be realized; DDR4 has a master frequency as high as 1.6GT/S, and provides data calculation processing of an external interface and a CPU; the bandwidth of each port of the L2 Switch with 4 ports can reach 2.5Gbps, wherein 4 SGMII interfaces support the rate of 1Gbps, and one QSGMII/QXGMII interface supports the rate of 2.5 Gbps; 1 TSN port supports USXGMII and the supported bandwidth can reach 2.5 Gbps; the DP interface is mainly used for processing and converting video data.
As shown in fig. 3, the present apparatus has 5 external interfaces MAC0, swp0, swp1, swp2, swp 3; the CPU has 4 internal Ethernet controllers Eth0, Eth1, Eth2, Eth 3; eth0 interfaces MAC0 via SGMII interface; swp0, swp1, swp2 and swp3 are connected with controllers inside the TSN Switch through QSGMII interfaces, and the controllers inside the TSN Switch are connected with Eth2 and Eth3 of the CPU.
Connect to host CPU mode:
in this transport mode, the L2 Switch is connected to the ethernet controller inside the host CPU, as above Eth2 and Eth3 in fig. 1 are connected to the L2 Switch. In addition to the above connections, the L2 Switch also allows a single Switch port to operate in CPU mode.
The following table summarizes the differences between the CPU mode and the non-CPU mode:
Figure DEST_PATH_IMAGE002
in the non-CPU mode, the user needs to use the same peer network port to send and receive messages, instead of using the interface of the actual port of the switch. In the CPU port mode, the user will use the network device interface or bridge interface of the switch port.
In the time-sensitive network, in a non-CPU mode, the device does not have a function of converting a conventional ethernet packet into a time-sensitive network packet, so that a user needs to send and receive packets using the same opposite port, and data transmitted in the network is a conventional ethernet packet (without real-time property) and a time-sensitive network (with real-time property); under the CPU port mode, the CPU can adopt the functions of frame injection and frame analysis to add the time sensitive network function defined by the user into the conventional Ethernet message.
CPU mode:
the principle of operation of the CPU port is to select the switch destination port of the frame and address control frame from a known protocol (e.g., STP) for the host CPU.
When this mode is enabled on one of the internal switch ports, the user may use the Linux network interface assigned to that port as:
1) an independent network interface; in the CPU mode, the L2 Switch is not using the Switch function, and is called non-bridge CPU mode, as shown in fig. 3:
in this configuration mode, traffic received by all external ports is forwarded to the CPU port, but L2 forwarding is inoperative by default. Another difference from the bridge mode is that each switch port interface can be used separately to send and receive packets.
The main operation modes in this mode are:
(a1) downloading the port configuration file in the non-bridge mode into a storage module;
(a2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting, configuring IP addresses of the ports as different network segments, and up connecting Eth3 ports of a CPU;
(a3) the four ports are respectively accessed into different Remote Host computers, wherein swp0 is consistent with a Remote Host1, swp1 is consistent with a Remote Host2, swp2 is consistent with a Remote Host3, and swp3 is consistent with a Remote Host 4;
(a4) the different Remote Host ping ports can pass through.
2) Subinterfaces of the bridge interface-CPU ports with simple bridge configuration and L2 forwarding support, as shown in fig. 4.
In this configuration mode, the main operation modes of the bridged network port are:
(b1) downloading a port configuration file in a bridge CPU mode into a storage module;
(b2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting is completed, configuring IP addresses of the ports as different network segments, and up connecting Eth2 and Eth3 ports of a CPU;
(b3) configuring a Remote Host to be 192.168.0.1 connected to swp3, simultaneously configuring swp0, swp1, swp2 and swp3 ports under a bridge space, and configuring the IP of the whole bridge to be 192.168.0.2;
(b4) the Eth2 port of the CPU is configured to be 192.168.0.3, which is a data channel for data transmission, and the Eth3 of the CPU is a data channel for control command transmission, and is not configured;
(b5) any of the ports through swp0, swp1, swp2, swp3 may ping directly through the Eth2 port.
Frame injection:
by using custom flags or injected headers appended before the ethernet frame header, the driver can instruct the L2 Switch to forward the frame on a particular port and bypass the frame parser.
The frame analyzer determines the destination port, QoS classification and VLAN classification of the frame through normal frame processing, including looking up the MAC table and VLAN table.
The transmission of the tagged frame is done from the peer network endpoint device. The peer network device is specified by a device tree attribute. Upon reception, the L2 Switch will strip off the header, apply the frame update (e.g., write a timestamp on the PTP frame), and place the frame into the egress queue of the destination port. Once configured in frame injection mode, the switch ports accept only tagged frames.
And (3) frame analysis:
the L2 Switch may intercept various control frames or normal frames (unicast or multicast) and redirect them to the CPU ports. When a frame exits the CPU port, it is also extracted by custom marking or frame header, as is injection. This header needs to be stripped and decoded by the switch driver to extract the incoming switch port number of the received frame. Once configured for extraction, the switch ports only emit tagged frames.
non-CPU mode:
if one of the CPU internal ports is operating in non-CPU port mode, the decision to forward a frame to the host CPU or accept a frame depends entirely on the frame analyzer and the MAC and VLAN tables. The transmission of frames in non-CPU port mode does not carry any custom tags. Only in this mode, the peer network device port (i.e., the ENETC port) acts as a proxy for the switch port, thus requiring the user to send and receive packets to and from the switch using the peer Linux network interface.
Under the CPU mode, because the internet access and the L2 Switch of the device both support the TSN standardized protocol, the data of the field-level endpoint equipment in the industrial internet equipment is subjected to time-sensitive processing through the CPU mode, and the certainty and real-time transmission of the industrial data can be effectively realized. Under the independent network interface of the CPU mode, conventional Ethernet data of a plurality of field level devices can be configured according to the transmission priority of a user, Tags of data frames are configured, and the function of the time-sensitive network gateway can be converted into an industrial protocol; under a bridge network interface in a CPU mode, the MAC0 is accessed to a PLC controller and other devices to realize time-sensitive processing of conventional Ethernet data, the time-sensitive data processed by the CPU is transmitted upwards through swp 0-swp 3 ports, and 4 ascending ports have the functions of a switch and can realize large-scale industrial field device access.
In the non-CPU mode, the normal switch processing capability is provided.
A multi-mode deterministic data processing device and method, through realizing the configuration under different modes, make the apparatus not merely can support the switching ability of the conventional exchanger, can also possess the user-defined time sensitive characteristic configuration, realize the transmission reliability and real-time of the network data, through the modular switching mode, can realize the conversion of the traditional apparatus to the time sensitive apparatus effectively.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (8)

1. A multi-mode deterministic data processing apparatus characterized by: the system comprises a CPU, a POR module, a clock management module, a power management module, a storage module, a data interface, a debugging interface, a DDR module, a TSN Switch, a TSN network port and a DP interface, wherein the POR module, the clock management module, the power management module, the storage module, the data interface, the debugging interface, the DDR module, the TSN Switch, the TSN network port and the;
the apparatus has 5 external interfaces MAC0, swp0, swp1, swp2, swp 3; the CPU has 4 internal Ethernet controllers Eth0, Eth1, Eth2, Eth 3; eth0 interfaces MAC0 via SGMII interface; swp0, swp1, swp2 and swp3 are connected with controllers inside the TSN Switch through QSGMII interfaces, and the controllers inside the TSN Switch are connected with Eth2 and Eth3 of the CPU.
2. A multi-mode deterministic data processing apparatus according to claim 1, characterized in that: the storage module comprises NAND/NOR storage, SD storage and eMMC storage, is used for storing bootloaders, kernel, file systems and toolkits of the equipment, and provides operating system files for equipment operation.
3. A multi-mode deterministic data processing apparatus according to claim 1, characterized in that: the data interface module be used for carrying out external data exchange, it includes wired interface and wireless interface, wired interface includes USB type A, USB type C, RS232, CAN, and wireless interface includes 4G WIFI.
4. A multi-mode deterministic data processing apparatus according to claim 1, characterized in that: the CPU adopts Cortex-A72, the main frequency is 1.3GHz, 64 bits are 1MB L2 buffer memory, and ECC protection is provided; the POR module is a power-on reset configuration module and is used for initializing the function configuration of pins of the equipment and realizing the function starting of the equipment according to the pins designed in advance; the clock management module and the power supply management module are used for providing a standard clock and a power supply for normal operation of the equipment and ensuring that the power-on and power-off time sequence of the power supply meets the requirements of the equipment; the debugging interface module is a JTAG interface and is used for providing an external debugging interface for the CPU; the DDR module has a master frequency of 1.6GT/S and is used for providing data calculation processing of an external interface and a CPU; the DP interface module is mainly used for processing and converting video data.
5. A method of multi-mode deterministic data processing, characterized by: the method comprises a CPU mode and a non-CPU mode, wherein in the CPU mode, a user adds a user-defined time-sensitive network function into a conventional Ethernet message by adopting frame injection and frame analysis functions through a network equipment interface or a network bridge interface of a switch port; in the non-CPU mode, the device does not have the function of converting a conventional ethernet packet into a time-sensitive network packet, and the user needs to use the same peer port to send and receive packets.
6. A multi-mode deterministic data processing method according to claim 5, characterized in that: the CPU modes comprise a non-bridge CPU mode and a bridge CPU mode.
7. A multi-mode deterministic data processing method according to claim 6, characterized in that: the non-bridging CPU mode comprises the steps of:
(a1) downloading the port configuration file in the non-bridge mode into a storage module;
(a2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting, configuring IP addresses of the ports as different network segments, and up connecting Eth3 ports of a CPU;
(a3) the four ports are respectively accessed into different Remote Host computers, wherein swp0 is consistent with a Remote Host1, swp1 is consistent with a Remote Host2, swp2 is consistent with a Remote Host3, and swp3 is consistent with a Remote Host 4;
(a4) the different Remote Host ping ports can pass through.
8. A multi-mode deterministic data processing method according to claim 6, characterized in that: the bridge CPU mode comprises the following steps:
(b1) downloading a port configuration file in a bridge CPU mode into a storage module;
(b2) initializing and configuring through a POR module, checking device ports of swp0, swp1, swp2 and swp3 after starting is completed, configuring IP addresses of the ports as different network segments, and up connecting Eth2 and Eth3 ports of a CPU;
(b3) configuring a Remote Host to be 192.168.0.1 connected to swp3, simultaneously configuring swp0, swp1, swp2 and swp3 ports under a bridge space, and configuring the IP of the whole bridge to be 192.168.0.2;
(b4) the Eth2 port of the CPU is configured to be 192.168.0.3, which is a data channel for data transmission, and the Eth3 of the CPU is a data channel for control command transmission, and is not configured;
(b5) any of the ports through swp0, swp1, swp2, swp3 may ping directly through the Eth2 port.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114201427A (en) * 2022-02-18 2022-03-18 之江实验室 Parallel deterministic data processing device and method
CN114302411A (en) * 2021-12-27 2022-04-08 中国电信股份有限公司 Wireless local area network system and network data processing method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030231103A1 (en) * 2002-06-14 2003-12-18 Fisher Scott R. Electronic lock system and method for its use with card only mode
CN104838359A (en) * 2012-08-16 2015-08-12 微软技术许可有限责任公司 Latency sensitive software interrupt and thread scheduling
US20150331803A1 (en) * 2011-08-11 2015-11-19 The Quantum Group Inc. System and method for slice processing computer-related tasks
CN111262796A (en) * 2019-12-31 2020-06-09 南昌大学 Ethernet communication system and method based on time sensitivity

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030231103A1 (en) * 2002-06-14 2003-12-18 Fisher Scott R. Electronic lock system and method for its use with card only mode
US20150331803A1 (en) * 2011-08-11 2015-11-19 The Quantum Group Inc. System and method for slice processing computer-related tasks
CN104838359A (en) * 2012-08-16 2015-08-12 微软技术许可有限责任公司 Latency sensitive software interrupt and thread scheduling
CN111262796A (en) * 2019-12-31 2020-06-09 南昌大学 Ethernet communication system and method based on time sensitivity

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114302411A (en) * 2021-12-27 2022-04-08 中国电信股份有限公司 Wireless local area network system and network data processing method
CN114201427A (en) * 2022-02-18 2022-03-18 之江实验室 Parallel deterministic data processing device and method

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