CN113300729A - Zero intermediate frequency receiver and correction method thereof - Google Patents
Zero intermediate frequency receiver and correction method thereof Download PDFInfo
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- CN113300729A CN113300729A CN202110528464.XA CN202110528464A CN113300729A CN 113300729 A CN113300729 A CN 113300729A CN 202110528464 A CN202110528464 A CN 202110528464A CN 113300729 A CN113300729 A CN 113300729A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/30—Circuits for homodyne or synchrodyne receivers
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Abstract
The invention provides a zero intermediate frequency receiver and a correction method thereof, comprising a first passive mixer and a second passive mixer; a first error correction circuit coupled to the first passive mixer; a first transimpedance amplifier connected to the first error correction circuit; a second error correction circuit coupled to the second passive mixer; a second transimpedance amplifier connected to the second error correction circuit; the first error correction circuit and the second error correction circuit each include a common gate impedance transformation circuit; the DAC circuit is connected with the output end of the common-gate impedance transformation circuit; and a feedback circuit connected to the common gate impedance transformation circuit; the common-gate impedance transformation circuit is used for improving the impedance from each trans-impedance amplifier to the corresponding passive mixer; the DAC circuit is used for eliminating residual DC errors in the circuit; the feedback circuit is used for absorbing the common mode current generated by the DAC circuit.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a zero intermediate frequency receiver and a correction method of the zero intermediate frequency receiver.
Background
In recent years, the development of advanced processes provides more freedom and development space for mixed signal chip design; among them, a fully integrated radio transceiver solution including various correction algorithms is a trend. The direct down-conversion (zero intermediate frequency) structure is an ideal choice due to the simple structure, low cost and low power consumption, but the quadrature error and the DC error of the I, Q two paths are main non-ideal factors of the zero intermediate frequency architecture, and have been a main obstacle limiting the application for many years. The main sources of DC error for a zero intermediate frequency receiver are two parts: receiving static DC error generated by device mismatch of a channel; the local oscillator leakage returns to the dynamic DC error produced by the mixer. The static DC error amplitude is large and is the main part of the DC error and can reach more than 100 mV. The DC error produces high energy in the received spectrum, which degrades signal quality, and the DC causes the operating state of the analog circuit to change, which causes other non-linear distortions. The main causes of the static DC error are the input reference noise voltage and the input offset voltage of the transimpedance amplifier. The effective impedance of the mixer network is time-varying and as the frequency decreases, its gain factor is also time-varying. When the duty ratio of the signal and the threshold voltage of the switch act together, the switch of the mixer may be simultaneously turned on, and the input of the operational amplifier is short-circuited, so that the output DC and noise of the transimpedance amplifier become large, and the DC error and noise are increased. Therefore, it is desirable to provide a scheme to reduce static DC error and noise while ensuring that the signal is not attenuated.
Disclosure of Invention
The invention aims to provide a zero intermediate frequency receiver and a correction method thereof, which are used for reducing static DC error and noise and ensuring that signals are not attenuated.
In a first aspect, the present invention provides a zero intermediate frequency receiver comprising a first passive mixer and a second passive mixer; a first error correction circuit coupled to the first passive mixer; a first transimpedance amplifier connected to the first error correction circuit; a second error correction circuit coupled to the second passive mixer; a second transimpedance amplifier connected to the second error correction circuit; the first error correction circuit and the second error correction circuit each include a common gate impedance transformation circuit; the DAC circuit is connected with the output end of the common-gate impedance transformation circuit; and a feedback circuit connected to the common gate impedance transformation circuit; the common-gate impedance transformation circuit is used for improving the impedance from each trans-impedance amplifier to the corresponding passive mixer; the DAC circuit is used for eliminating residual DC errors in the circuit; the feedback circuit is used for absorbing the common mode current generated by the DAC circuit.
Further, the common-gate impedance transformation circuit comprises a bias voltage input end, a power input end, a first resistor, a second resistor, a third resistor, a fourth resistor, a first bias current source, a second bias current source, a third bias current source, a fourth bias current source, a first CMOS transistor and a second CMOS transistor; the grid electrode of the first CMOS tube and the grid electrode of the second CMOS tube are both connected with the bias voltage input end; the source electrode of the first CMOS tube, the first end of the first resistor and the first end of the first bias current source are connected with the first output end of the corresponding passive mixer; the source electrode of the second CMOS tube, the first end of the second resistor and the first end of the second bias current source are connected with the second output end of the corresponding passive mixer; second ends of the first bias current source and the second bias current source are grounded; the second end of the third bias current source, the first end of the third resistor and the drain electrode of the first CMOS tube are connected with the first input end of the corresponding transimpedance amplifier; the second end of the fourth bias current source, the first end of the fourth resistor and the drain electrode of the second CMOS tube are connected with the second input end of the corresponding transimpedance amplifier; the first end of the third bias current source and the first end of the fourth bias current source are both connected with the power supply input end; the second end of the first resistor and the second end of the second resistor are both connected with the output end of the feedback circuit; and the second end of the third resistor and the second end of the fourth resistor are both connected with the input end of the feedback circuit.
Further, the feedback circuit comprises an operational amplifier and a reference voltage input terminal; the inverting input end of the operational amplifier is connected with the second end of the third resistor and the second end of the fourth resistor; the non-inverting input end of the operational amplifier is connected with the reference voltage input end; and the output end of the operational amplifier is connected with the second end of the first resistor and the second end of the second resistor.
Further, the feedback circuit comprises an operational amplifier and a reference voltage input terminal; the inverting input end of the operational amplifier is connected with the second end of the third resistor and the second end of the fourth resistor; the non-inverting input end of the operational amplifier is connected with the reference voltage input end; and the output end of the operational amplifier is connected with the second end of the first resistor and the second end of the second resistor.
Further, the input voltage of the reference voltage input end is equal to the common-mode voltage of the operational amplifier in the corresponding transimpedance amplifier.
Further, the feedback circuit further comprises a fifth resistor and a first capacitor; the first end of the first capacitor is respectively connected with the second end of the first resistor and the second end of the second resistor; a first end of the fifth resistor is connected with a second end of the first capacitor; and the second end of the fifth resistor is respectively connected with the second end of the third resistor and the second end of the fourth resistor.
Further, the third resistor and the fourth resistor have a resistance of at least 40 kilo-ohms.
Further, the resistance values of the first resistor and the second resistor are at least 2 times of the feedback resistor of the operational amplifier in the corresponding transimpedance amplifier.
Further, the DAC circuit is a current steering DAC circuit.
In a second aspect, the present invention provides a calibration method for a zero-if receiver, which is applied to the zero-if receiver, and includes:
acquiring output signals of the first passive mixer/the second passive mixer;
increasing an impedance of a corresponding transimpedance amplifier looking at the first passive mixer/the second passive mixer through a common-gate impedance transformation circuit connected with the first passive mixer/the second passive mixer;
removing residual DC errors in the circuit through a DAC circuit connected with the output end of the common-gate impedance transformation circuit, and absorbing common-mode current generated by the DAC circuit through a feedback circuit connected with the common-gate impedance transformation circuit to obtain a current signal after error correction;
and converting the current signal after error correction into a voltage signal through a trans-impedance amplifier and outputting the voltage signal to a post-stage filter.
The beneficial effects that the invention can realize are as follows: the circuit provided by the invention is additionally provided with the error correction circuit between the traditional passive mixer and the transimpedance amplifier, so that the impedance from the transimpedance amplifier to the passive mixer is improved and the impedance from the passive mixer to the transimpedance amplifier is reduced through the error correction circuit; the input reference noise voltage and the input reference offset voltage of the receiving channel are reduced, and the deterioration of the input reference noise voltage and the input reference offset voltage along with the increase of the local oscillation frequency is avoided; the DC error and the noise output by the trans-impedance amplifier are reduced, and the design complexity of a local oscillation signal driving circuit is also reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of an overall structure of a conventional zero if receiver according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an overall structure of a zero if receiver according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an equivalent circuit of a zero if receiver according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an error correction circuit according to an embodiment of the present invention;
fig. 5 is a flowchart illustrating a calibration method of a zero if receiver according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, fig. 2 and fig. 3, fig. 1 is a schematic diagram illustrating an overall structure of a conventional zero-if receiver according to an embodiment of the present invention; fig. 2 is a schematic diagram of an overall structure of a zero if receiver according to an embodiment of the present invention; fig. 3 is a schematic diagram of an equivalent circuit of a zero if receiver according to an embodiment of the present invention; fig. 4 is a schematic diagram of an error correction circuit according to an embodiment of the present invention.
As shown in fig. 1, fig. 1 shows a system block diagram of a typical zero if receiver, and the existing zero if receiver includes a Low Noise Amplifier (LNA), a Mixer (Mixer1 and Mixer2), a transimpedance amplifier (TIA1 and TIA2), a low pass filter (LPF1 and LPF2), an ADC circuit (ADC1 and ADC2), a local oscillation source (LO), and the like. However, the static DC error generated by the device mismatch of the receiving channel formed by the above components can have a great influence on the error of the output signal. The applicant has found that the most significant problem affecting the output DC error and noise in a zero if receiver is the input reference noise voltage and the input offset voltage of the transimpedance amplifier. The effective impedance of the mixer network is time-varying and as the frequency decreases, its gain factor is also time-varying. When the threshold voltage of the switch in the mixer and the duty ratio of the signal act together, the switch of the mixer may be turned on simultaneously, which causes the increase of the DC and noise output by the transimpedance amplifier; even if there is no simultaneous turn-on problem with the switches of the mixer, there is still a case where the input reference noise and DC are amplified. The mixer switch and the capacitance at its input constitute a switched capacitor circuit whose equivalent impedance becomes very small at high frequencies, causing output noise and DC to be amplified. To solve this problem, the present invention provides a zero if receiver that can reduce static DC error and noise while still ensuring that the signal is not attenuated.
In one embodiment, the zero intermediate frequency receiver provided by the embodiment of the present invention includes a first passive Mixer (Mixer1) and a second passive Mixer (Mixer 2); a first error correction circuit (a) connected to the first passive Mixer (Mixer 1); a first transimpedance amplifier (TIA1) connected to the first error correction circuit (a); a second error correction circuit (B) connected to the second passive Mixer (Mixer 2); a second transimpedance amplifier (TIA2) connected to the second error correction circuit (B); the first error correction circuit (A) and the second error correction circuit (B) each include a common gate impedance conversion circuit (a); a DAC circuit (b) connected to an output terminal of the common gate impedance converting circuit (a); and a feedback circuit (c) connected to the common gate impedance transformation circuit (a); the common-gate impedance transformation circuit (a) is used for improving the impedance of each trans-impedance amplifier to the corresponding passive mixer; the DAC circuit (b) is used for eliminating residual DC errors in the circuit; the feedback circuit (c) is used for absorbing the common mode current generated by the DAC circuit.
By the circuit, the effective impedance of the input end of the transimpedance amplifier looking at the mixer is high enough, the impedance of the mixer looking at the transimpedance amplifier is low enough, the DAC circuit can eliminate residual DC errors, and the feedback circuit can absorb common-mode current generated by the DAC circuit. In this way, it is ensured that the signal is not attenuated while reducing static DC errors and noise.
Specifically, as shown in fig. 4, in one implementation, the common-gate impedance transformation circuit provided by the embodiment of the present invention includes a bias voltage input terminal (VBias), a power supply input terminal (Ibias), a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (R4), a first bias current source (T1), a second bias current source (T2), a third bias current source (T3), a fourth bias current source (T4), a first CMOS transistor (VT1), and a second CMOS transistor (VT 2); the grid electrode of the first CMOS transistor (VT1) and the grid electrode of the second CMOS transistor (VT2) are both connected with a bias voltage input end (VBias); the source electrode of the first CMOS transistor (VT1), the first end of the first resistor (R1) and the first end of the first bias current source (T1) are connected with the first output end of the corresponding passive Mixer (Mixer); the source electrode of the second CMOS transistor (VT2), the first end of the second resistor (R2) and the first end of the second bias current source (T2) are connected with the second output end of the corresponding passive Mixer (Mixer); a second terminal of the first bias current source (T1) and a second terminal of the second bias current source (T2) are both grounded; the second end of the third bias current source (T3), the first end of the third resistor (R3) and the drain electrode of the first CMOS transistor (VT1) are all connected with the first input end of the corresponding transimpedance amplifier; the second end of the fourth bias current source (T4), the first end of the fourth resistor (R4) and the drain electrode of the second CMOS transistor (VT2) are all connected with the second input end of the corresponding transimpedance amplifier; the first terminal of the third bias current source (T3) and the first terminal of the fourth bias current source (T4) are both connected to the power supply input terminal (Ibias); a second end of the first resistor (R1) and a second end of the second resistor (R2) are both connected with an output end of the feedback circuit (c); the second end of the third resistor (R3) and the second end of the fourth resistor (R4) are both connected with the input end of the feedback circuit (c).
In the implementation process, a common-gate amplifier biased in a saturation region is formed by the first CMOS transistor (VT1) and the second CMOS transistor (VT2), and a small resistance value can be obtained by increasing the transconductance of the common-gate amplifier; the input end of the transimpedance amplifier is connected to the drains of the first CMOS transistor (VT1) and the second CMOS transistor (VT2), and the impedance seen by the transimpedance amplifier is very high impedance, so that the impedance conversion function is achieved, the reference noise voltage and the input reference offset voltage input by the transimpedance amplifier can be effectively prevented from being amplified, the signal output by the passive mixer is ensured not to be attenuated, and the common-mode Voltage (VCMTIA) of the passive mixer is determined by the common-mode Voltage (VCMTIA) of the transimpedance amplifier. In order for the passive mixer switch to reach a sufficient on-resistance, the local oscillator signal needs to be sufficiently above the common mode voltage. After the common-gate amplifier is used, the common-mode voltage of the passive mixer is determined by the common-gate amplifier (VGSMCG), i.e., VCMTIA — VGSMCG. The common mode Voltage (VCMTIA) of the trans-impedance amplifier can be set in a lower voltage range by reasonably setting the bias voltage (VBias) and the source Voltage (VGSMCG), so that the mixer switch does not need to be driven by an excessively high local oscillation voltage, and the design complexity of the circuit is simplified.
In one embodiment, the feedback circuit (c) includes an operational amplifier (U1) and a reference voltage input (Vref); an inverting input terminal of the operational amplifier (U1) is connected with a second terminal of the third resistor (R3) and a second terminal of the fourth resistor (R4); the non-inverting input terminal of the operational amplifier (U1) is connected with the reference voltage input terminal (Vref); an output terminal of the operational amplifier (U1) is connected to a second terminal of the first resistor (R1) and a second terminal of the second resistor (R2).
Specifically, the input voltage of the reference voltage input end (Vref) is equal to the common-mode voltage of the operational amplifier in the corresponding transimpedance amplifier, and a feedback loop formed by the operational amplifier plays a role in: the operational amplifier loop forcibly absorbs the common-mode current generated by the DAC circuit, and stabilizes the common-mode voltage at the output end of the error correction circuit (namely the input end of the trans-impedance amplifier) at the reference voltage (Vref) of the operational amplifier by using the virtual short of the operational amplifier. The common-mode current of the DAC circuit does not flow to the trans-impedance amplifier, but is absorbed by the operational amplifier output after passing through the common-gate amplifier, so that the change of an operating point caused by the voltage drift of the input end of the trans-impedance amplifier (TIA) due to the common-mode current of the DAC circuit is avoided. Resistors R3 and R4 are high value resistors to avoid degradation of the correction circuit output impedance. The reference voltage (Vref) and the common-mode voltage of the operational amplifier in the trans-impedance amplifier (TIA) are equal.
In one embodiment, the feedback circuit (C) further comprises a fifth resistor (R5) and a first capacitor (C1); a first end of the first capacitor (C1) is respectively connected with a second end of the first resistor (R1) and a second end of the second resistor (R2); a first terminal of a fifth resistor (R5) is connected to a second terminal of the first capacitor (C1); a second terminal of the fifth resistor (R5) is connected to a second terminal of the third resistor (R3) and a second terminal of the fourth resistor (R4), respectively. The stability compensation of the loop can be carried out through the fifth resistor (R5) and the first capacitor (C1).
In one embodiment, to ensure the correction effect of the error correction circuit, the third resistor (R3) and the fourth resistor (R4) have a resistance of at least 40 kohms. The DAC circuit (b) may be a current steering DAC circuit. The resistance values of the first resistor (R1) and the second resistor (R2) are at least 2 times of the feedback resistor (Rfb) of the operational amplifier in the corresponding transimpedance amplifier.
Referring to fig. 5, fig. 5 is a flowchart illustrating a calibration method of a zero-if receiver according to an embodiment of the present invention.
In an embodiment, an embodiment of the present invention further provides an error correction method for a zero intermediate frequency receiver, which includes the following main processes:
s1, acquiring output signals of a first passive mixer/a second passive mixer;
s2, improving the impedance of a corresponding transimpedance amplifier looking at the first passive mixer/the second passive mixer through a common-grid impedance conversion circuit connected with the first passive mixer/the second passive mixer;
s3, removing residual DC errors in the circuit through a DAC circuit connected with the output end of the common-gate impedance conversion circuit, and absorbing common-mode current generated by the DAC circuit through a feedback circuit connected with the common-gate impedance conversion circuit to obtain a current signal with corrected errors;
and S4, converting the current signal after error correction into a voltage signal through the trans-impedance amplifier and outputting the voltage signal to a post-stage filter.
In summary, the embodiments of the present invention provide a zero-if receiver and a calibration method of the zero-if receiver, including a first passive mixer and a second passive mixer; a first error correction circuit coupled to the first passive mixer; a first transimpedance amplifier connected to the first error correction circuit; a second error correction circuit coupled to the second passive mixer; a second transimpedance amplifier connected to the second error correction circuit; the first error correction circuit and the second error correction circuit each include a common gate impedance transformation circuit; the DAC circuit is connected with the output end of the common-gate impedance transformation circuit; and a feedback circuit connected to the common gate impedance transformation circuit; the common-gate impedance transformation circuit is used for improving the impedance from each trans-impedance amplifier to the corresponding passive mixer; the DAC circuit is used for eliminating residual DC errors in the circuit; the feedback circuit is used for absorbing the common mode current generated by the DAC circuit. By the circuit, the DC error and the noise output by the trans-impedance amplifier are reduced; meanwhile, the common-mode voltage of the frequency mixer switch is reduced, and the amplitude requirement of the frequency mixer switch on the local oscillation signal is reduced, so that the design of the local oscillation driving circuit is simplified.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A zero intermediate frequency receiver, comprising: a first passive mixer and a second passive mixer; a first error correction circuit coupled to the first passive mixer; a first transimpedance amplifier connected to the first error correction circuit; a second error correction circuit coupled to the second passive mixer; a second transimpedance amplifier connected to the second error correction circuit; the first error correction circuit and the second error correction circuit each include a common gate impedance transformation circuit; the DAC circuit is connected with the output end of the common-gate impedance transformation circuit; and a feedback circuit connected to the common gate impedance transformation circuit; the common-gate impedance transformation circuit is used for improving the impedance from each trans-impedance amplifier to the corresponding passive mixer; the DAC circuit is used for eliminating residual DC errors in the circuit; the feedback circuit is used for absorbing the common mode current generated by the DAC circuit.
2. The zero intermediate frequency receiver according to claim 1, wherein the common gate impedance conversion circuit comprises a bias voltage input terminal, a power supply input terminal, a first resistor, a second resistor, a third resistor, a fourth resistor, a first bias current source, a second bias current source, a third bias current source, a fourth bias current source, a first CMOS transistor and a second CMOS transistor; the grid electrode of the first CMOS tube and the grid electrode of the second CMOS tube are both connected with the bias voltage input end; the source electrode of the first CMOS tube, the first end of the first resistor and the first end of the first bias current source are connected with the first output end of the corresponding passive mixer; the source electrode of the second CMOS tube, the first end of the second resistor and the first end of the second bias current source are connected with the second output end of the corresponding passive mixer; second ends of the first bias current source and the second bias current source are grounded; the second end of the third bias current source, the first end of the third resistor and the drain electrode of the first CMOS tube are connected with the first input end of the corresponding transimpedance amplifier; the second end of the fourth bias current source, the first end of the fourth resistor and the drain electrode of the second CMOS tube are connected with the second input end of the corresponding transimpedance amplifier; the first end of the third bias current source and the first end of the fourth bias current source are both connected with the power supply input end; the second end of the first resistor and the second end of the second resistor are both connected with the output end of the feedback circuit; and the second end of the third resistor and the second end of the fourth resistor are both connected with the input end of the feedback circuit.
3. The zero intermediate frequency receiver according to claim 2, characterized in that the feedback circuit comprises an operational amplifier and a reference voltage input; the inverting input end of the operational amplifier is connected with the second end of the third resistor and the second end of the fourth resistor; the non-inverting input end of the operational amplifier is connected with the reference voltage input end; and the output end of the operational amplifier is connected with the second end of the first resistor and the second end of the second resistor.
4. The zero intermediate frequency receiver according to claim 3, wherein the input voltage of the reference voltage input terminal is equal to the common mode voltage of the operational amplifier in the corresponding transimpedance amplifier.
5. The zero intermediate frequency receiver according to claim 3, wherein the feedback circuit further comprises a fifth resistor and a first capacitor; the first end of the first capacitor is respectively connected with the second end of the first resistor and the second end of the second resistor; a first end of the fifth resistor is connected with a second end of the first capacitor; and the second end of the fifth resistor is respectively connected with the second end of the third resistor and the second end of the fourth resistor.
6. The zero intermediate frequency receiver according to claim 2, wherein the third resistor and the fourth resistor have a resistance of at least 40 kohms.
7. The zero intermediate frequency receiver according to claim 2, wherein the first resistor and the second resistor have a resistance value at least 2 times that of a feedback resistor of an operational amplifier in the corresponding transimpedance amplifier.
8. The zero intermediate frequency receiver according to claim 1, characterized in that the DAC circuit is a current steering DAC circuit.
9. A calibration method for a zero intermediate frequency receiver, applied to the zero intermediate frequency receiver of any one of claims 1-8, comprising:
acquiring output signals of the first passive mixer/the second passive mixer;
increasing an impedance of a corresponding transimpedance amplifier looking at the first passive mixer/the second passive mixer through a common-gate impedance transformation circuit connected with the first passive mixer/the second passive mixer;
removing residual DC errors in the circuit through a DAC circuit connected with the output end of the common-gate impedance transformation circuit, and absorbing common-mode current generated by the DAC circuit through a feedback circuit connected with the common-gate impedance transformation circuit to obtain a current signal after error correction;
and converting the current signal after error correction into a voltage signal through a trans-impedance amplifier and outputting the voltage signal to a post-stage filter.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114553158A (en) * | 2021-12-28 | 2022-05-27 | 广州润芯信息技术有限公司 | Low-noise amplifier and down-conversion system of receiver |
| CN115940974A (en) * | 2022-10-24 | 2023-04-07 | 天津大学 | Broadband anti-blocking radio frequency receiver |
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