CN113299744B - Terminal structure, semiconductor device and manufacturing method - Google Patents
Terminal structure, semiconductor device and manufacturing method Download PDFInfo
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- CN113299744B CN113299744B CN202110651512.4A CN202110651512A CN113299744B CN 113299744 B CN113299744 B CN 113299744B CN 202110651512 A CN202110651512 A CN 202110651512A CN 113299744 B CN113299744 B CN 113299744B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 239000003989 dielectric material Substances 0.000 claims abstract description 44
- 210000000746 body region Anatomy 0.000 claims abstract description 37
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- 239000010410 layer Substances 0.000 description 58
- 230000005684 electric field Effects 0.000 description 33
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- 238000009826 distribution Methods 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 125000004429 atom Chemical group 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 125000004437 phosphorous atom Chemical group 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
The application discloses a terminal structure, a semiconductor device and a manufacturing method, wherein the terminal structure comprises a drift region of a first conduction type, the drift region is provided with a groove, a doping region of the first conduction type and a first body region of a second conduction type, and the groove comprises a first depth region, a second depth region and a third depth region; the first depth region is filled with a dielectric material, a first electrode is inserted into the dielectric material, and the second depth region is provided with a first polysilicon field plate; the first polysilicon field plate and the first electrode are connected with the second electrode, the third depth region is provided with a second polysilicon field plate, and the doped region and the second polysilicon field plate are provided with cut-off rings. According to the terminal structure, the first polycrystalline silicon field plate prevents a PN junction formed by the first body region and the drift region from being broken down in advance, the first electrode prevents the bottom corner of the first depth region from being broken down in advance, and the second polycrystalline silicon field plate prevents breakdown from occurring in the stop ring. The structure improves the voltage resistance of the terminal structure and reduces the area of the terminal structure.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a terminal structure, a semiconductor device and a manufacturing method.
Background
The power semiconductor device is one of core devices in a power electronic circuit, and is widely applied to a motor driver, an automobile, a power supply and the like. The power device comprises, in addition to an active region for current guiding, a non-active region (i.e. a termination region) located at the periphery of the active region. The terminal region is used for relieving the junction curvature effect so as to ensure the breakdown voltage of the active region, prevent the device from breaking down at the edge of the chip and ensure that the device is not influenced by the outside world under the severe working environment.
The traditional terminal structure comprises a field plate, a field limiting ring, junction terminal expansion, a transverse variable doping, a resistive long plate and the like. Conventional termination structures including field limiting rings or field plates, especially high voltage class termination structures, are oversized. The junction termination extension and lateral variation doped structure is susceptible to surface charge due to low surface concentration, although the termination structure length is small. At constant current density, the area of the active region will decrease linearly with decreasing current rating, while the width of the termination is almost unchanged, resulting in a large increase in the ratio of termination region area to total chip area for small-sized chips, thus raising the cost dramatically.
The existing deep trench terminal structure has large trench depth, extends from a drift region to a substrate region, and although the length of the terminal structure can be greatly reduced, the deep trench terminal structure has high electric field near the trench, and the breakdown occurs in the terminal region, thereby affecting the long-term reliability of the device. In addition, the trench depth is large and needs to extend to the substrate area, which further limits the application range of the terminal structure.
Disclosure of Invention
In view of this, the present application provides a termination structure, a semiconductor device and a method for manufacturing the same, so as to solve the problem that the conventional deep trench termination structure is prone to breakdown near the trench.
The terminal structure provided by the embodiment of the application comprises a drift region of a first conduction type, wherein the drift region is provided with a groove, and a doped region of the first conduction type and a first body region of a second conduction type are respectively arranged on two sides of the groove;
a first oxide layer is arranged on the surface of the groove;
the groove is a T-shaped groove and comprises a first depth area, a second depth area and a third depth area, the second depth area is positioned between the first depth area and the first body area, the third depth area is positioned between the first depth area and the doping area, and the depth of the second depth area and the depth of the third depth area are both smaller than the depth of the first depth area and larger than the junction depth of the first body area;
the first depth region is filled with a dielectric material, a first electrode is inserted into the dielectric material, the second depth region is provided with a first polysilicon field plate, and the third depth region is provided with a second polysilicon field plate;
a second electrode is arranged on the first body region and is respectively connected with the first polycrystalline silicon field plate and the first electrode;
a second oxide layer is arranged between the first body region and the second electrode, and one end, far away from the groove, of the second oxide layer is retracted relative to the first body region;
and a stop ring is arranged on the doped region and the second polysilicon field plate, and a third oxide layer is arranged between the stop ring and the second electrode. Optionally, the terminal structure further includes a second body region of the second conductivity type, and the second body region is respectively disposed adjacent to the first depth region and the second depth region through the first oxide layer.
Optionally, the depth of insertion of the first electrode is greater than the depth of the second depth zone or the third depth zone.
Optionally, the depth of the second depth zone is equal to the depth of the third depth zone.
Optionally, a substrate is disposed at the bottom of the drift region.
Optionally, the trench extends from the top to the bottom of the drift region, and the depth of the first depth region is smaller than the depth of the drift region.
Optionally, the first depth zone is close to the edge of one side of the first body zone and the distance of the first electrode is 0.2-5 um.
Optionally, the first conductivity type is N-type conductivity, and the second conductivity type is P-type conductivity;
or the first conduction type is P-type conduction, and the second conduction type is N-type conduction.
Optionally, the dielectric material is benzocyclobutene resin.
The embodiment of the application also provides a semiconductor device which is characterized by comprising the terminal structure of the embodiment.
The embodiment of the application further provides a manufacturing method of the terminal structure, which comprises the following steps:
providing a drift region of a first conductivity type;
etching a first depth region on top of the drift region;
manufacturing a first oxide layer on the surface of the first depth region;
filling a dielectric material in the first depth region;
etching a second depth region and a third depth region at the top of the drift region, wherein the second depth region and the third depth region are respectively positioned at two sides of the first depth region, the depth of the second depth region and the depth of the third depth region are both smaller than the depth of the first depth region, and the first depth region, the second depth region and the third depth region form a T-shaped groove;
manufacturing a first oxidation layer on the surfaces of the second depth area and the third depth area;
manufacturing a first polycrystalline silicon field plate in the second depth region, and manufacturing a second polycrystalline silicon field plate in the third depth region;
manufacturing a first body region of a second conduction type on one side, close to the second depth region, of the top of the drift region, wherein the junction depth of the first body region is smaller than the depth of the second depth region;
manufacturing a doped region of the first conductivity type on one side of the top of the drift region close to the third depth region;
manufacturing a second oxide layer on the first body region, and manufacturing a third oxide layer on the dielectric material, wherein one end of the second oxide layer, which is far away from the trench, is retracted relative to the first body region, and one end of the third oxide layer, which is far away from the third depth region, is retracted relative to the dielectric material;
fabricating a first electrode in the dielectric material, wherein the first electrode is inserted into the dielectric material, and the third oxide layer is located on the surface of the dielectric material between the first electrode and the third depth region;
and manufacturing a second electrode on the second oxide layer, wherein the second electrode sequentially covers the top exposed region of the first body region, the surface of the second oxide layer, the surface of the first polysilicon field plate and part of the surface of the dielectric material and is connected with the first electrode.
As described above, in the terminal structure of the embodiment of the present application, the drift region is provided with the T-shaped trench, the trench includes the first depth region, the second depth region and the third depth region, the second depth region is provided with the first oxide layer and the first polysilicon field plate, the first polysilicon field plate constitutes the primary field plate, and the primary field plate can introduce an electric field peak value at the corner of the second depth region, thereby reducing the electric field at the PN junction formed by the first body region and the drift region and preventing the PN junction from being broken down in advance;
the first depth region is provided with a first oxide layer and a dielectric material, a first electrode is inserted into the dielectric material, one side of the second depth region is provided with a first body region, a second electrode is arranged on the first body region, and the first polycrystalline silicon field plate and the first electrode are in short circuit connection through the second electrode to realize the same potential; the first electrode forms a secondary field plate, and the secondary field plate introduces an electric field peak at the edge of the first depth region approximately flush with the tail end of the first electrode, so that the electric field at the bottom corner of the first depth region is reduced, and the bottom corner of the first depth region is prevented from being broken down in advance.
The third depth region is provided with a first oxide layer and a second polysilicon field plate, one side of the third depth region is provided with a doped region, the doped region and the second polysilicon field plate are provided with a stop ring, the stop ring is connected with the second polysilicon field plate to realize the potential equality, the electric field generated by the first polysilicon field plate can be balanced, the electric field of the first depth region close to one side edge of the second depth region is reduced, the breakdown is prevented from occurring in the stop ring region, and a third oxide layer for isolating the potential is arranged between the stop ring and the second electrode. The electric field distribution on the surface of the groove is more uniform than that of the existing groove terminal structure, so that ideal plane breakdown voltage is obtained. In addition, the first oxide layer and the dielectric material improve the electric field intensity in the groove, so that the terminal size of the power device can be reduced. Compared with the traditional terminal structure, the T-shaped groove terminal structure provided by the embodiment of the application has the advantages of small size and better pressure resistance.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a terminal according to an embodiment of the present application;
FIG. 2 is a schematic diagram of the electric field distribution of the termination structure of FIG. 1;
fig. 3 is a schematic structural diagram of another terminal according to an embodiment of the present application;
fig. 4 is a schematic flowchart of a method for manufacturing a terminal structure according to an embodiment of the present application.
Detailed Description
The technical solutions of the present application are described below clearly and completely by way of examples, and it is obvious that the described examples are only a part of the examples of the present application, and not all of the examples. The following embodiments and their technical features may be combined with each other without conflict.
The embodiment of the application provides a terminal structure, as shown in fig. 1, the terminal structure includes a drift region 1 of a first conductivity type, the drift region 1 is provided with a trench 2, and two sides of the trench 2 are respectively provided with a doped region 12 of the first conductivity type and a first body region 11 of a second conductivity type. In one embodiment, the drift region 1 can be fabricated using at least one of single crystal silicon, silicon carbide, gallium arsenide, indium phosphide, and silicon germanium. In addition, the first conductivity type may be P-type conductivity and correspondingly the second conductivity type is N-type conductivity. In other embodiments, the first conductivity type may be N-type conductivity and correspondingly the second conductivity type is P-type conductivity.
Taking the first conductive type being N-type conductivity and the second conductive type being P-type conductivity as an example, the termination structure includes an N-type drift region 1, a first body region (hereinafter referred to as a first P-type region) 11 of P-type conductivity, a doped region (hereinafter referred to as an N + region) 12 of N-type conductivity, and a trench 2 are disposed on the N-type drift region 1, the trench 2 is located between the first P-type region 11 and the N + region 12, in one embodiment, the first P-type region 11 is located on the left side of the trench 2, the N + region 12 is located on the right side of the trench 2, the trench 2 separates the first P-type region 11 from the N + region 12, the entire surface of the trench 2 is provided with a first oxide layer 21, and in one embodiment, the first oxide layer 21 may be silicon dioxide.
The trench 2 is a T-shaped trench and includes a first depth region 22, a second depth region 23 and a third depth region 24, the second depth region 23 is located between the first depth region 22 and the first P-type region 11, the third depth region 24 is located between the first depth region 22 and the N + region 12, and the depths of the second depth region 23 and the third depth region 24 are smaller than the depth of the first depth region 22 and larger than the junction depth of the first P-type region 11. That is, the first depth region 22, the second depth region 23 and the third depth region 24 form a T-shaped trench, the sidewall of the trench 2 near the first P-type region 11 is stepped, and the sidewall of the trench 2 near the N + region 12 is also stepped. In the trench 2, a region above the step 231 is the second depth region 23, a region above the step 241 is the third depth region 24, and a region above the groove bottom 221 of the trench 2 is the first depth region 22.
In one embodiment, the depth of the second depth zone 23 may be 1-10 um, the depth of the third depth zone 24 may also be 1-10 um, and the depth of the first depth zone 22 may be 3-100 um on the premise that the depths of the second depth zone 23 and the third depth zone 24 are less than the depth of the first depth zone 22. In one embodiment, the thickness of the first oxide layer 21 at the surface of the first depth regions 22 may be 500-20000A. In other embodiments, the thickness of the first oxide layer 21 at the surfaces of the second and third depth regions 23, 24 may be 800-1500A. The first depth region 22 is filled with a dielectric material 3, and a first electrode 41 is inserted into the dielectric material 3. The dielectric material 3 is preferably a low dielectric constant material such as benzocyclobutene resin (BCB). The first electrode 41 may be a metal electrode, such as an aluminum electrode, a copper electrode, or the like. The second depth region 23 is provided with a first polysilicon field plate 42 and the third depth region 24 is provided with a second polysilicon field plate 45, for example, the second depth region 23 and the third depth region 24 may be filled with polysilicon material, respectively.
A second electrode 43 is disposed on the first P-type region 11, and the second electrode 43 is connected to the polysilicon field plate 42 and the first electrode 41 respectively. That is, the second electrode 43 shorts the first polysilicon field plate 42 and the first electrode 41 to achieve the same potential. The second electrode 43 may be made of the same metal material as the first electrode 41, so that the metal layers of the first electrode 41 and the second electrode 43 may be deposited in the same process.
A second oxide layer 13 is disposed between the first P-type region 11 and the second electrode 43, and an end of the second oxide layer 13 away from the trench 2 is recessed relative to the first P-type region 11, i.e. the second electrode 43 is connected to the end of the first P-type region 11 away from the trench 2. In one embodiment, one end of the second oxide layer 13 near the trench 2 extends to the opening of the trench 2 to connect with the first oxide layer 21. The second oxide layer 13 may be silicon dioxide.
A stop ring 44 is arranged on the N + region 12 and the second polysilicon field plate 45; a third oxide layer 16 is disposed between the stop ring 44 and the second electrode 43, and the stop ring 44 is separated from the second electrode 43 by the third oxide layer 16. In one embodiment, the third oxide layer 16 may be silicon dioxide, which may have a thickness of 2000-15000A and is capable of good potential isolation.
In the termination structure of the above embodiment, the electric field distribution of the internal electric field at O1, O2, O3 and O4 is shown in fig. 2. The first polysilicon field plate 42 is used as a primary field plate, and an electric field peak can be introduced at the corner O2 of the second depth region 23, so that the electric field at the PN junction O1 is effectively reduced, and the PN junction O1 is prevented from being broken down in advance. The first electrode 41 in the first depth region 22 acts as a secondary field plate, and an electric field peak is introduced at the edge O3 of the first depth region 22 that is approximately flush with the end of the first electrode 41, which effectively reduces the electric field at the corner O4 of the first depth region 22 and prevents breakdown from occurring at the corner O4 of the first depth region 22. The second polysilicon field plate 45 is short-circuited with the stop ring 44 and has the same potential, so that the electric field generated by the first polysilicon field plate 42 can be balanced, the electric field at the right edge of the first depth region 22 can be reduced, and breakdown can be prevented from occurring in the region of the stop ring 44. The electric field distribution on the surface of the trench 2 is more uniform, so that a desired planar breakdown voltage is obtained. In addition, the first oxide layer and the dielectric material increase the electric field intensity in the trench 2, so that the terminal size of the power device can be reduced. Compared with the traditional terminal structure, the T-shaped groove terminal structure with the two stages of field plates, provided by the embodiment of the application, is small in size and better in pressure resistance. It should be noted that, in the above embodiments, the T-shaped grooves are only to figure out that the depths of the second depth zone 23 and the third depth zone 24 are both smaller than the depth of the first depth zone 22, and the second depth zone 23 and the third depth zone 24 are located at both sides of the first depth zone 22, which does not mean that the depths of the second depth zone 23 and the third depth zone 24 are necessarily the same, in some embodiments, the depth of the second depth zone 23 may be greater than or less than the depth of the third depth zone 24, and preferably, the depth of the second depth zone 23 is equal to the depth of the third depth zone 24, so that the processing of the second depth zone 23 and the third depth zone 24 can be completed in one etching process.
In one embodiment, the termination structure may further include a second body region 14 of the second conductivity type, the second body region 14 being disposed adjacent to the first depth region 22 and the second depth region 23, respectively, through the first oxide layer 21. Continuing with the example where the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity, as shown in fig. 3, a second body region 14 of the second conductivity type (hereinafter referred to as a second P-type region) is located below the second depth region 23 and adjacent to the first depth region 22 on the left side of the first depth region 22, the second P-type region 14 is separated from the second depth region 23 by the first oxide layer 21, and the second P-type region 14 is separated from the first depth region 22 by the first oxide layer 21.
In the above embodiment, by adding the second P-type region 14 below the second depth region 23, the depletion region extending from the second P-type region 14 to the N-type drift region 1 is enlarged, the PN junction electric field near the step 231 is reduced, and premature breakdown at the edge PN junction (near the O1 position) of the second depth region 23 is prevented.
In one embodiment, the first electrode 41 is inserted to a depth greater than the depth of the second depth zone 23 or the third depth zone. That is, the end of the first electrode 41 is located as close to the bottom of the first depth region 22 as possible, so as to minimize the electric field at the corner O4 of the first depth region 22. As a preferred embodiment, the distance d between the edge of the first deep region 22 near the first P-type region 11 and the first electrode may be 0.2-5 um, and the electric field at the corner O4 of the first deep region 22 may also be reduced to the greatest extent.
In one embodiment, the bottom of the N-type drift region 1 is provided with a substrate. When the terminal structure is applied to a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) or a Fast Recovery Diode (FRD), the substrate is an N + type substrate; when the termination structure is applied to an Insulated Gate Bipolar Transistor (IGBT), the substrate is a P-type substrate.
In combination with the embodiment of the terminal structure in which the first conductivity type is N-type conductivity and the second conductivity type is P-type conductivity, the substrate of the first conductivity type may be an N + substrate 15, and specifically, after the other functional layers of the terminal structure are fabricated, the bottom of the N-type drift region 1 may be thinned, and then the N + substrate 15 may be formed by ion implantation. In one embodiment, the trench 2 extends from the top to the bottom of the N-type drift region 1, and the depth of the trench 2 is less than the depth of the N-type drift region 1, that is, the trench bottom 221 of the first depth region 22 is spaced from the N + substrate 15, and the first depth region 22 does not extend into the N + substrate 15.
It should be noted that, the terminal structure of the above embodiment is only exemplified by the first conductivity type being N-type conductivity and the second conductivity type being P-type conductivity, as known to those skilled in the art, the terminal structure of other embodiments with similar structures can be obtained by interchanging the N-type conductivity type and the P-type conductivity type.
The embodiment of the application also provides a semiconductor device, and the semiconductor device comprises the terminal structure in each embodiment. The Semiconductor device may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Fast Recovery Diode (FRD), or an Insulated Gate Bipolar Transistor (IGBT).
An embodiment of the present application further provides a method for manufacturing a terminal structure, please refer to fig. 4, where fig. 4 is a schematic flow chart illustrating the method for manufacturing the terminal structure according to the embodiment of the present application. In fig. 4, the method comprises the following steps:
s401, a drift region of a first conduction type is provided. In one embodiment, the drift region may be made of one of single crystal silicon, silicon carbide, gallium arsenide, indium phosphide, or silicon germanium, for example, P atoms are implanted into single crystal silicon to form a drift region with N-type conductivity, or B atoms are implanted into single crystal silicon to form a drift region with P-type conductivity. In one embodiment, the first conductivity type may be P-type conductivity and correspondingly the second conductivity type is N-type conductivity. In other embodiments, the first conductivity type may be N-type conductivity and correspondingly the second conductivity type is P-type conductivity.
Taking the first conductivity type as N-type conductivity and the second conductivity type as P-type conductivity as an example, an N-type drift region 1 is fabricated.
And S402, etching a first depth region on the top of the N-type drift region 1. In one embodiment, the first depth region 22 may be etched on top of the N-type drift region 1 by an etching liquid or a laser.
S403, forming a first oxide layer 21 on the surface of the first depth region 22. In one embodiment, the first oxide layer 21 may be formed on the surface of the first depth region 22 by epitaxial growth.
S404, filling the first depth region 22 with a dielectric material 3. In one of the embodiments, a dielectric material 3, such as a BCB material, may be deposited in the first depth region 22.
S405, etching a second depth region 23 and a third depth region 24 on the top of the N-type drift region 1, wherein the second depth region 23 and the third depth region 24 are respectively located on two sides of the first depth region 22, the depth of the second depth region 23 and the depth of the third depth region 24 are both smaller than the depth of the first depth region 22, and the first depth region 22, the second depth region 23 and the third depth region 24 form a T-shaped groove 2. In one embodiment, the second depth region 23 and the third depth region 24 may be etched simultaneously on the top of the N-type drift region 1 at both sides of the first depth region 22 by using an etching solution or laser lithography, and the etching depth is less than that of the first depth region 22, so that the first depth region 22, the second depth region 23 and the third depth region 24 form a T-shaped trench 2.
S406, manufacturing a first oxidation layer 21 on the surfaces of the second depth region 23 and the third depth region 24. In one embodiment, the first oxide layer 21 may be formed on the surfaces of the second depth region 23 and the third depth region 24 by epitaxial growth, and the first oxide layer 21 may be silicon dioxide.
And S407, respectively manufacturing a first polysilicon field plate 42 and a second polysilicon field plate 45 in the second depth region 23 and the third depth region 24. In one embodiment, a polysilicon material may be deposited in the second depth region 23 and the third depth region 24.
S408, a first body region (i.e., a first P-type region) 11 of the second conductivity type is formed on a side of the top of the N-type drift region 1 close to the second deep region 23, and a junction depth of the first P-type region 11 is smaller than a depth of the second deep region 23. In one embodiment, the first P-type region 11 is formed by first performing photolithography on the region located at the left side of the second depth region 23 at the top of the N-type drift region 1 and then implanting B atoms by means of ion implantation, wherein the junction depth of the first P-type region 11 is smaller than the depth of the second depth region 23.
S409, a doped region (i.e., N + region) 12 of the first conductivity type is formed at a side of the top of the N-type drift region 1 close to the third deep region 24. In one embodiment, the region on the top of the N-type drift region 1 and on the right side of the third depth region 24 is first subjected to photolithography, and then P atoms are implanted by means of ion implantation to form the N + region 12.
S410, a second oxide layer 13 is formed on the first P-type region 11, and a third oxide layer 16 is formed on the dielectric material 3, wherein an end of the second oxide layer 13 away from the trench 2 is recessed with respect to the first P-type region 11, and an end of the third oxide layer 16 away from the third deep region 24 is recessed with respect to the dielectric material 3. In one embodiment, a second oxide layer 13 may be deposited on the surface of the first P-type region 11, and a third oxide layer 16 may be deposited on the surface of the N + region 12 and on a surface portion of the dielectric material 3, wherein the second oxide layer 13 and the third oxide layer 16 may be silicon dioxide at the same time.
S411, fabricating a first electrode 41 in the dielectric material 3, wherein the first electrode 41 is inserted into the dielectric material 3, and the third oxide layer 16 is located on the surface of the dielectric material 3 between the first electrode 41 and the third depth region 24; a second electrode 43 is formed on the second oxide layer 13, wherein the second electrode 43 sequentially covers the top exposed region of the first P-type region 11, the surface of the second oxide layer 13, the surface of the first polysilicon field plate 42 and a portion of the surface of the dielectric material 3, and is connected to the first electrode 41. In one embodiment, an electrode trench is etched in the dielectric material 3 by laser, then metal deposition is performed on the electrode trench and the left region of the electrode trench, and photolithography is performed to obtain a first electrode 41 and a second electrode 43, wherein the first electrode 41 is inserted into the dielectric material 3 (electrode trench), and the second electrode 43 sequentially covers the top exposed region of the first P-type region 11, the surface of the second oxide layer 13, the surface of the first polysilicon field plate 42, and a portion of the surface of the dielectric material 3, and is connected to the first electrode 41.
In other embodiments, step S412 may be further included after step S411: a substrate is fabricated at the bottom of the N-type drift region 1. The N + substrate 15 may be formed by first performing thinning processing on the back surface of the N-type drift region 1 and then implanting P atoms by means of ion implantation. The groove bottom 221 of the first depth region 22 is spaced apart from the N + substrate 15, i.e., the first depth region 22 does not extend into the N + substrate 15.
Preferably, between step S405 and step S406, step S4051 may be further included: a second body region (second P-type region) 14 of the second conductivity type is formed at the bottom of the second depth region 23. In one embodiment, the second P-type region 14 is formed by first performing photolithography on the bottom of the second depth region 23 and then implanting B atoms by means of ion implantation.
In summary, in the terminal structure of the embodiment of the present application, the drift region 1 is provided with the T-shaped trench 2, the trench 2 includes the first depth region 22, the second depth region 23 and the third depth region, the second depth region 23 is provided with the first oxide layer 21 and the first polysilicon field plate 42, and the first polysilicon field plate 42 constitutes a primary field plate; the first depth region 22 is provided with a first oxide layer 21 and a dielectric material 3, a first electrode 41 is inserted into the dielectric material 3, and the first electrode 41 forms a secondary field plate; a first body region 11 is arranged on one side of the second depth region 23, a second electrode 43 is arranged on the first body region 11, and the first polysilicon field plate 42 and the first electrode 41 are short-circuited by the second electrode 43 to realize the same potential; the third depth region is provided with a first oxidation layer and a second polycrystalline silicon field plate, one side of the third depth region is provided with a doped region, a stop ring is arranged on the doped region and connected with the second polycrystalline silicon field plate to realize the potential equality, an electric field generated by the first polycrystalline silicon field plate can be balanced, the electric field of the first depth region close to one side edge of the second depth region is reduced, the breakdown is prevented from occurring in the stop ring region, and a third oxidation layer for isolating the potential is arranged between the stop ring and the second electrode.
In the T-shaped trench terminal structure of the embodiment of the application, the primary field plate can introduce an electric field peak value at the corner of the second depth region 23, so that the electric field at the PN junction formed by the first body region 11 and the drift region 1 is reduced, and the PN junction is prevented from being broken down in advance; the secondary field plate introduces an electric field peak at the edge of the first depth region 22 approximately flush with the end of the first electrode 41, which reduces the electric field at the bottom corner of the first depth region 22 and prevents the bottom corner of the first depth region 22 from being broken down in advance, and the second polysilicon field plate reduces the electric field at the edge of the first depth region near the edge of the second depth region and prevents breakdown from occurring in the stop ring region. The electric field distribution on the surface of the trench 2 is more uniform than that of the existing trench termination structure, so that an ideal planar breakdown voltage is obtained. In addition, the first oxide layer 21 and the dielectric material 3 increase the electric field strength in the trench, so that the terminal size of the power device can be reduced. Compared with the traditional terminal structure, the T-shaped groove terminal structure provided by the embodiment of the application has the advantages of small size and better pressure resistance.
In addition, the second body region 14 of the second conductivity type is added below the second depth region 23, so that a depletion region extending from the second body region 14 to the N-type drift region 1 is enlarged, the PN junction electric field near the step 231 is reduced, and premature breakdown at the edge PN junction (near the O1 position) of the second depth region 23 is prevented.
The above-mentioned embodiments are only examples of the present application, and not intended to limit the scope of the present application, and all equivalent structural changes made by using the contents of the specification and the drawings of the present application, such as mutual combination of technical features between various embodiments, or direct or indirect application to other related technical fields, are also included in the scope of the present application.
In addition, in the description of the present application, it is to be understood that the terms "upper", "lower", "left", "right", "top", "bottom", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be configured in a specific orientation, and operate, and thus, should not be construed as limiting the present application.
Claims (9)
1. A terminal structure comprises a drift region of a first conduction type, and is characterized in that the drift region is provided with a groove, and two sides of the groove are respectively provided with a doped region of the first conduction type and a first body region of a second conduction type;
a first oxide layer is arranged on the surface of the groove;
the groove is a T-shaped groove and comprises a first depth area, a second depth area and a third depth area, the second depth area is positioned between the first depth area and the first body area, the third depth area is positioned between the first depth area and the doping area, and the depth of the second depth area and the depth of the third depth area are both smaller than the depth of the first depth area and larger than the junction depth of the first body area;
the first depth region is filled with a dielectric material, a first electrode is inserted into the dielectric material, the insertion depth of the first electrode is greater than the depths of the second depth region and the third depth region, the second depth region is provided with a first polysilicon field plate, and the third depth region is provided with a second polysilicon field plate;
a second electrode is arranged on the first body region, a second oxide layer is arranged between the first body region and the second electrode, and the second electrode sequentially covers part of the top surface of the first body region, the surface of the second oxide layer, the surface of the first polysilicon field plate and part of the surface of the dielectric material and is connected with the first electrode;
and a stop ring is arranged on the surface of the doped region and the surface of the second polysilicon field plate, and a third oxide layer is arranged between the stop ring and the second electrode.
2. The termination structure of claim 1, further comprising a second body region of a second conductivity type disposed immediately adjacent to said first depth region and said second depth region, respectively, through said first oxide layer.
3. The termination structure of claim 1, wherein the depth of the second depth zone is equal to the depth of the third depth zone.
4. The termination structure of claim 1, wherein a bottom of said drift region is provided with a substrate.
5. The termination structure of claim 1, wherein the trench extends from a top to a bottom of the drift region, and wherein the depth of the first depth region is less than the depth of the drift region.
6. A termination structure according to claim 1, wherein the edge of the first depth zone on the side thereof adjacent the first body zone is spaced from the first electrode by a distance of 0.2-5 um.
7. The termination structure of claim 1, wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity;
or the first conduction type is P-type conduction, and the second conduction type is N-type conduction.
8. A semiconductor device comprising a termination structure as claimed in any one of claims 1 to 7.
9. A method for manufacturing a terminal structure is characterized by comprising the following steps:
providing a drift region of a first conductivity type;
etching a first depth region on top of the drift region;
manufacturing a first part of a first oxidation layer on the surface of the first depth region;
filling a dielectric material in the first depth region;
etching a second depth region and a third depth region at the top of the drift region, wherein the second depth region and the third depth region are respectively positioned at two sides of the first depth region, the depth of the second depth region and the depth of the third depth region are both smaller than the depth of the first depth region, and the first depth region, the second depth region and the third depth region form a T-shaped groove;
manufacturing a second part of the first oxide layer on the surfaces of the second depth area and the third depth area;
manufacturing a first polycrystalline silicon field plate in the second depth region, and manufacturing a second polycrystalline silicon field plate in the third depth region;
manufacturing a first body region of a second conduction type on one side, close to the second depth region, of the top of the drift region, wherein the junction depth of the first body region is smaller than the depth of the second depth region;
manufacturing a doped region of the first conductivity type on one side of the top of the drift region close to the third depth region;
manufacturing a second oxide layer on the first body region, and manufacturing a third oxide layer on the dielectric material, wherein one end, far away from the third depth region, of the third oxide layer is retracted relative to the dielectric material;
making a first electrode in the dielectric material, wherein the first electrode is inserted into the dielectric material, the insertion depth of the first electrode is greater than the depth of the second depth region and the third depth region, and the third oxide layer is positioned on the surface of the dielectric material between the first electrode and the third depth region;
and manufacturing a second electrode on the second oxide layer, wherein the second electrode sequentially covers the top exposed region of the first body region, the surface of the second oxide layer, the surface of the first polysilicon field plate and part of the surface of the dielectric material and is connected with the first electrode.
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