CN113299654B

CN113299654B - Three-dimensional memory device and method of fabricating the same

Info

Publication number: CN113299654B
Application number: CN202110549631.9A
Authority: CN
Inventors: 豆海清; 刘立芃; 陈韦斌; 张�浩; 钟杜; 熊峰; 曾最新
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2022-06-14
Anticipated expiration: 2041-05-20
Also published as: CN113299654A

Abstract

The present application provides a three-dimensional memory device comprising: a substrate; a stack structure formed on the substrate and including gate layers and insulating layers alternately stacked, the stack structure having a memory array region and a step region arranged in a first direction; at least one gate line gap structure extending through the step region at least along the first direction to divide the stacked structure into a plurality of division regions; and a groove structure arranged along the first direction and penetrating the stacked structure at the step region. According to the three-dimensional memory device, stress caused by the patterns of the virtual channel structure can be reduced, supporting force is improved, the conditions of grid line gap distortion and mouse engagement are reduced, and the yield and the reliability of the three-dimensional memory device are improved.

Description

Three-dimensional memory device and method of fabricating the same

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a three-dimensional memory device having reduced step region stress and improved supporting force and a method of fabricating the same.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As the feature size of semiconductor manufacturing processes becomes smaller, the storage density of memory devices becomes higher. In order to further increase the memory density, a memory device of a three-dimensional structure (i.e., a three-dimensional memory device) has been developed. The three-dimensional memory device includes a plurality of memory cells stacked in a vertical direction, can increase the integration degree by a multiple on a unit area of a wafer, and can reduce the cost.

To achieve higher memory density, the number of stacked layers in a three-dimensional memory device has also increased significantly, such as from 32 layers to 64 layers, to 96 layers or even 128 layers, and so on. However, as the number of layers of the three-dimensional memory device increases, the problem of stress in the step region becomes more and more serious. This may result in distortion of, for example, a gate line gap (Wiggling) and even a Mouse bite (Mouse bit) like defect. In the three-dimensional memory device, it is known that the distortion phenomenon of the gate line gap is related to the stress and support difference caused by the dummy channel structure pattern. In order to leave enough space for the contact channel, the dummy channel structure has the problems of asymmetrical dummy channel structures on both sides of the gate line and insufficient density of the dummy channel structures in the layout (especially near the top selection gate cut region).

Therefore, it is desirable to further improve the structure of the three-dimensional memory device to improve the yield and reliability of the three-dimensional memory device.

It should be appreciated that this background section is intended in part to provide a useful background for understanding the technology. This background section, however, may also include views, concepts or insights that are part of what is not known or understood by those of ordinary skill in the relevant art prior to the corresponding effective application date of the subject matter disclosed herein.

Disclosure of Invention

The present application provides a three-dimensional memory device that can solve, at least in part, the above-mentioned problems occurring in the related art.

An aspect of embodiments of the present application is directed to a three-dimensional memory device, which may include: a substrate; a stack structure formed on the substrate and including alternately stacked gate layers and insulating layers, the stack structure having a memory array region and a step region arranged in a first direction; at least one gate line gap structure extending through the step region at least along the first direction to divide the stacked structure into a plurality of division regions; and a groove structure extending along the first direction and penetrating the stacked structure in the step region.

In an exemplary embodiment, the three-dimensional memory device may further include a plurality of contact channels located at the stepped region, and each of the contact channels may be connected to the gate layer on each of the steps of the stepped region, respectively.

In an exemplary embodiment, the groove structure may include a first groove structure and a second groove structure, the contact passage may not be provided in a direction in which the first groove structure horizontally extends, and the second groove structure may be alternately provided in the same horizontal direction as the contact passage.

In an exemplary embodiment, an orthogonal projection of the first groove structure on the surface of the substrate may have a length greater than an orthogonal projection of the second groove structure on the surface of the substrate.

In an exemplary embodiment, the first and second groove structures may intermittently extend along the first direction.

In an exemplary embodiment, the first groove structure may continuously extend along the first direction, and the second groove structure may discontinuously extend along the first direction.

In an exemplary embodiment, the first trench structure may be disposed adjacent to the gate gap structure between two adjacent partition regions, and the second trench structure may be disposed away from the gate gap structure between two adjacent partition regions.

In an exemplary embodiment, the second trench structure may be disposed adjacent to the gate line gap structure between two adjacent partition regions, and the first trench structure may be disposed away from the gate line gap structure between two adjacent partition regions.

In an exemplary embodiment, an orthographic projection of the at least one contact via on the surface of the substrate may have a square profile.

In an exemplary embodiment, an orthographic projection of the at least one contact channel on the surface of the substrate may have a circular contour.

In an exemplary embodiment, the three-dimensional memory device may further include a plurality of channel structures that may penetrate the stacked structure located at the memory array region, wherein each channel structure may include: a channel hole penetrating the stacked structure in a direction perpendicular to the substrate, and a functional layer and a channel layer sequentially stacked from outside to inside along a sidewall of the channel hole.

In an exemplary embodiment, an orthographic projection of the at least one channel structure on the surface of the substrate may have a circular profile.

In an exemplary embodiment, an orthographic projection of the slot structure on the surface of the substrate may have a stripe-shaped profile.

In an exemplary embodiment, when viewed on a plane, the groove structures in two adjacent separation regions may be arranged symmetrically with respect to the gate line gap structure between the two adjacent separation regions.

In an exemplary embodiment, the trench structure may be a dummy channel structure, and each dummy channel structure may include: a dummy channel hole penetrating the stacked structure in a direction perpendicular to the substrate, and an oxide layer formed along a sidewall of the dummy channel hole.

In an exemplary embodiment, the three-dimensional memory device may be a three-dimensional NAND flash memory.

Another aspect of embodiments of the present application is directed to a method of fabricating a three-dimensional memory device, which may include: providing a substrate; forming a stacked structure including gate layers and insulating layers alternately stacked on a substrate, the stacked structure including a memory array region and a step region; forming a trench structure penetrating the stacked structure in the stacked structure at the step region, the trench structure extending in a first direction; and forming at least one gate line gap structure in the stacked structure, the at least one gate line gap structure extending in the first direction and dividing the stacked structure in the step region into at least two separation regions.

In an exemplary embodiment, the method may further include forming a plurality of contact channels in the stack structure located in the stepped region, each of the contact channels being connected to the gate layer on each of the steps of the stepped region, respectively.

In an exemplary embodiment, forming the groove structure may include: a first groove structure and a second groove structure are formed, in which the contact passage may not be provided in a direction in which the first groove structure horizontally extends, and the second groove structure and the contact passage may be alternately provided in the same horizontal direction.

In an exemplary embodiment, the first groove structure may continuously extend along the first direction, and the second groove structure may intermittently extend along the first direction.

In an example embodiment, the method may further include forming a plurality of channel structures penetrating the stacked structure in the stacked structure located in the memory array region.

Another aspect of embodiments of the present application is directed to a memory system that may include the above three-dimensional memory device or a three-dimensional memory device manufactured according to the above manufacturing method.

Through grid line gap distortion/mouse tooth trace stress simulation result, increase the density of virtual channel hole in the direction parallel with the gate line structure and can effectively alleviate the influence that stress release brought, the most dense hole overall arrangement is the slot form promptly, consequently in this application designs virtual channel hole into the slot form that length is inequality to through the symmetrical overall arrangement of gate line structure both sides slot structure further promote gate line distortion window.

Compared with the prior art, the beneficial effects of this application mainly appear: this application can effectively alleviate stress release to the influence of gate line through bar slot structure's design and its symmetrical arrangement on the plane about grid line gap structure, can avoid grid line gap structure to take place the defect of distortion deformation similar mouse tooth trace even appears, can further promote grid line gap structure distortion deformation's window, can increase the bench region holding power to can show the yield and the reliability that improve three-dimensional memory device.

Drawings

The above and other advantages and features of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

FIG. 1 is a cross-sectional schematic diagram illustrating a portion of a three-dimensional memory device according to one embodiment of the present application;

FIG. 2 is a schematic top view illustrating a portion of a three-dimensional memory device according to one embodiment of the present application;

FIG. 3 is a schematic top view illustrating a portion of a three-dimensional memory device according to another embodiment of the present application;

FIG. 4 is a schematic top view showing a portion of a three-dimensional memory device according to yet another embodiment of the present application; and

fig. 5 is a flowchart illustrating a method of manufacturing a three-dimensional memory device according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

It will also be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements.

Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

As used herein, "about" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have a smaller extent than the underlying or overlying structure. Further, the layer may be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness that is less than a thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes at the top and bottom surfaces or top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and a contact layer (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "three-dimensional (3D) memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND memory strings) on a laterally oriented substrate such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" means nominally perpendicular to a lateral surface of a substrate.

Flow charts are used herein to illustrate operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, various steps may be processed in reverse order or simultaneously. Meanwhile, other operations are added to or removed from these processes.

Numerous specific details of the present application, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the present application. However, as will be understood by those skilled in the art, the present application may be practiced without these specific details.

The present application may be presented in a variety of forms, some examples of which are described below.

Fig. 1 is a schematic cross-sectional view illustrating a portion of a three-dimensional memory device according to an embodiment of the present application. Fig. 2 is a schematic top view illustrating a portion of a three-dimensional memory device according to one embodiment of the present application. Fig. 1 and 2 are partial views of the three-dimensional memory device, and do not show the entire structure of the three-dimensional memory device.

As shown in fig. 1 and 2, the three-dimensional memory device 1000 according to this embodiment may include a substrate 100, a stack structure 200, a gate line gap structure 300 (including a first gate line gap structure 310 and a second gate line gap structure 320), and a trench structure 400 (including a first trench structure 410 and a second trench structure 420). Wherein, the stacked structure 200 may be formed on the substrate 100. The stack structure 200 may have a memory array region 201 and a step region 202 disposed in a first direction (e.g., a D1 direction). The gate line gap structure 300 extends through the memory array region 201 and the step region 202 in the direction D1 and through the stacked structure 200 in the direction perpendicular to the substrate 100, dividing the stacked structure 200 into a plurality of separation regions 210. The trench structure 400 is formed in the stepped region 202 and penetrates the stack structure 200 in a direction perpendicular to the substrate 100.

In this embodiment, the substrate 100 may be a semiconductor substrate. The substrate 100 may be, for example, a single crystal Silicon (Si) substrate, a single crystal Germanium (Ge) substrate, a Silicon On Insulator (SOI) substrate, or a Germanium On Insulator (GOI) substrate, etc. The substrate 100 may also be, for example, a P-type doped substrate or an N-type doped substrate, but is not limited thereto. Those skilled in the art can select suitable materials as the substrate 100 according to actual requirements. For example, in other embodiments, the material of the substrate 100 may also be a semiconductor or a compound including other elements. For example, the substrate 100 may be a gallium arsenide substrate, an indium phosphide substrate, a silicon carbide substrate, or the like. Further, the substrate 100 may include a high voltage P-type well region (HVPW), a high voltage N-type well region (HVNW), a deep N-well (DNW), and the like. In addition, other additional layers may also be present between the substrate 100 and the stacked structure 200. The well regions and additional layers described above are not shown in fig. 1 for simplicity of description.

In this embodiment mode, the stack structure 200 includes the insulating layers 2001 and the gate layers 2002 which are alternately arranged in series in a direction perpendicular to the substrate 100. The stack structure 200 having a multilayer structure may be formed by a successive alternate stacked arrangement of the insulating layers 2001 and the gate layers 2002. It is to be understood that the number and thickness of the insulating layer 2001 and the gate layer 2002 are not limited to those shown in fig. 1. In the three-dimensional memory device, the number of layers of the stacked structure 200 determines the number of memory cells in the vertical direction, the number of layers of the stacked structure 200 may be, for example, 32, 64, 96, 108, and the like, and the greater the number of layers of the stacked structure 200, the higher the integration level can be. The insulating layer 2001 and the gate layer 2002 may be provided in any number and thickness as necessary by those skilled in the art without departing from the concept of the present application. By way of example, the insulating layer 2001 may include, but is not limited to, a material of any one of silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof; and the gate layer 2002 may be of a conductive material including, but not limited to, any one of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped poly-Si (polysilicon), doped single-crystal Si, silicide, or any combination thereof.

In this embodiment, the memory array region 201 is used to form an array memory cell string for storage of information, the memory cell string being a plurality of interconnected memory cells formed in a direction perpendicular to a substrate, the memory cell string being arranged in an array in a column direction and a row direction within a substrate plane, the row direction may be a word line direction, and the column direction may be a bit line direction. The step region 202 may be located at the periphery of the memory array region 201. The step region 202 may be covered with, for example, a dielectric insulating layer and a dielectric filling layer, and a dielectric covering layer may be further formed over the entire region. In other embodiments, the stepped region 202 may not be covered with a dielectric insulating layer. A word line connection circuit is formed in the step area 202 for transmitting control information to the memory array area 201 to realize reading and writing of information in the memory array area 201.

Referring to fig. 2, the three-dimensional memory device 1000 may further include a plurality of channel structures 600 and a plurality of trench structures 400, wherein the trench structures 400 may include a first trench structure 410 and a second trench structure 420 having different lengths in a first direction D1. The channel structure 600 may extend through the stacked structure 200 in the memory array region 201. As shown in the figure, an orthographic projection of the channel structure 600 on the surface of the substrate 100 may generally have, for example, a circular profile. However, this is exemplary only and not limiting. The three-dimensional memory device 1000 implements a data storage function through the channel structure 600. The channel structure 600 contacts the gate layer 2002 from its sidewall and constitutes a memory cell structure, with a drain drawn above and connected to a bit line, and a source drawn below. Wherein each channel structure 600 may include: a channel hole penetrating the stacked structure 200 in a direction perpendicular to the substrate 100, and a blocking insulating layer, a charge trapping layer, a tunneling insulating layer, a channel layer, and a dielectric layer structure sequentially stacked from outside to inside along a sidewall of the channel hole. The structure formed by stacking the layers sequentially from outside to inside may be, for example, an Oxide-Nitride-Oxide-polysilicon (ONOP) structure. The insulating layer, the charge trapping layer and the tunneling insulating layer constitute a storage function layer to realize a storage function. An exemplary material of the blocking insulating layer and the tunneling insulating layer is silicon oxide, and an exemplary material of the charge trapping layer is silicon nitride, forming a silicon oxide-silicon nitride-silicon oxide (ONO) structure. An exemplary material of the channel layer is polysilicon. It will be appreciated that other materials may be selected for these layers. For example, the material of the barrier insulating layer may include a high-K (dielectric constant) oxide layer. The charge trapping layer may be a floating gate structure, for example comprising a polysilicon material. The material of the channel layer may include monocrystalline silicon, monocrystalline germanium, SiGe, Si: C, SiGe: C, SiGe: H, and other semiconductor materials. An exemplary material for the dielectric layer is silicon oxide. It is understood that the channel structure 600 may also include other layers known in the art.

The trench structure 400 may be formed in the step region 202, extend along the first D1 direction, and penetrate through the stacked structure 200 along a direction perpendicular to the substrate 100. As shown in the figure, the orthographic projection of the trench structures 400 on the surface of the substrate 100 may have, for example, a stripe-shaped profile to increase the arrangement density of the trench structures, increase the supporting force in the stepped region 202, and effectively alleviate the influence of stress release. The trench structure 400 may be a dummy channel structure. In this case, each dummy channel structure 400 may include: a dummy channel hole penetrating the stack structure 200 in a direction perpendicular to the substrate 100, and a dummy channel material layer formed along a sidewall of the dummy channel hole. The dummy channel structure 400 does not actually serve as a memory cell, but functions, for example, to support the stack structure 200 or to perform process variation control during fabrication, so as to ensure that various processes in the formation of the internal structure of the three-dimensional memory device 1000 can be safely and effectively performed. The dummy channel material layer penetrating through the stack structure 200 may be disposed in the dummy channel structure 400, and the dummy channel material layer is not removed when the sacrificial layer is removed, so that the dummy channel material layer can support the stack structure 200, so that the structure of the three-dimensional memory device 1000 is not easily collapsed. An exemplary material for the dummy channel material layer is silicon oxide. According to an exemplary embodiment of the present disclosure, the dummy channel structure 400 may also have a similar structure to the channel structure 600, such as an ONOP structure formed within a dummy channel hole.

As shown, the three-dimensional memory device 1000 may further include a plurality of contact vias 500, the plurality of contact vias 500 being located in the stepped region 202, and each contact via 500 may be respectively connected to the gate layer 2002 on each step of the stepped region 200 to form an electrical connection with each gate layer 2002. The plurality of contact channels 500 are generally surrounded by a plurality of slot structures 400. The contact via 500 is a structure filled with a conductive material and performing an electrical connection function. Each gate layer 2002 in the stacked layer 200 located in the step area 202 is led out through the contact channel 500, so as to be connected with a back-end interconnection line, and a path for controlling information transmission is formed. As shown in the figure, an orthographic projection of the contact passage 500 on the surface of the substrate 100 may have, for example, a square profile. However, this is merely an example and not a limitation. In another embodiment, an orthographic projection of the at least one contact via 500' on the surface of the substrate 100 may have, for example, a circular profile (see fig. 3).

In addition, the three-dimensional memory device 1000 may further include at least one gate line gap structure 300, and the gate line gap structure 300 may penetrate the stack structure 200 along a direction perpendicular to the substrate 100. The gate line gap structure 300 may extend from the memory array region 201 to the step region 202 along the direction D1 for separating the stack structure 200 into a plurality of separation regions 210. The entire region shown in fig. 2 is one separation region 210, and the stacked structure 200 may have a plurality of separation regions 210 separated by the gate slit structure 300. The gate line gap structure 300 may be filled to form a gate line separating structure, which may include a conductive wall and an insulating layer surrounding a sidewall of the conductive wall, and a bottom end of the conductive wall may be connected to the substrate 100. The conductive wall may be, for example, an Array common source structure (ACS) (not shown). For example, the array common source structure may be composed of, for example, a lower polysilicon layer and an upper tungsten metal layer. It is understood that in other embodiments, the gate gap structure 300 may extend through the stepped region 202 at least along the D1 direction for separating the stacked structure 200 in the stepped region into a plurality of separation regions 210. This is not particularly limited in the present application.

In this embodiment, in particular, the at least one gate line gap structure 300 may include a plurality of first gate line gap structures 310 and a plurality of second gate line gap structures 320 alternately arranged along a second direction different from the first direction (e.g., the D1 direction). The first gate line gap structure 310 may divide the stack structure 200 into at least two block separation regions 210. The first gate line gap structure 310 may be a boundary of the block separation region 210. The second gate slit structure 320 may be located inside the block separation region 210, dividing the block separation region 210 into at least two sub-separation regions, e.g., the

sub-separation regions

211, 212, and 213 shown in the drawing.

In this embodiment, the slot structure 400 may include a first slot structure 410 and a second slot structure 420. Here, in a direction in which the first groove structure 410 horizontally extends (e.g., a D1 direction), the contact passage 500 may not be provided, and the second groove structures 420 may be alternately disposed in the same horizontal direction (e.g., a D1 direction) as the contact passage 500.

As shown in fig. 2, the first and

second trench structures

410 and 420 may intermittently extend along an extending direction (e.g., a D1 direction) of the gate gap structure 300. An orthogonal projection length of the first groove structure 410 on the surface of the substrate 100 may be greater than an orthogonal projection length of the second groove structure 420 on the surface of the substrate 100. However, this is exemplary only and not limiting. As another example, the first groove structure 410 may continuously extend along the extending direction (e.g., the D1 direction) of the gate gap structure 300, and the second groove structure 420 may discontinuously extend along the extending direction (e.g., the D1 direction) of the gate gap structure 300.

In the present embodiment, the plurality of trench structures 400 in the adjacent two sub-divided regions (e.g., 211, 212, and 213) may be arranged to be symmetrical with respect to the second gate slit structure 320 therebetween when viewed on a plane. Specifically, the

groove structures

410 and 420 in the

sub-dividing regions

211 and 212 may be arranged to be symmetrical with respect to the second gate gap structure 320 therebetween when viewed in a plane. In addition, the

trench structures

410 and 420 in the

sub-dividing regions

212 and 213 may be arranged to be symmetrical with respect to the second gate slit structure 320 therebetween when viewed in a plane. In addition, in the

sub-dividing regions

211 and 212, the second trench structure 420 may be disposed adjacent to the gate line gap structure 300 (e.g., the second gate line gap structure 320) between the adjacent two dividing regions 210, and the first trench structure 410 may be disposed away from the gate line gap structure 300 (e.g., the second gate line gap structure 320) between the adjacent two dividing regions 210. Alternatively or additionally, for example in the

sub-partition regions

212 and 213, the first trench structure 410 may be arranged adjacent to the gate slit structure 300 (e.g., the second gate slit structure 320) between two adjacent partition regions 210, and the second trench structure 420 may be arranged away from the gate slit structure 300 (e.g., the second gate slit structure 320) between two adjacent partition regions 210. The twisted windows of the gate line gap structure can be further improved by the symmetrical arrangement of the trench structure 400 at both sides of the second gate line gap structure 320.

FIG. 3 illustrates a schematic top view of a portion of a three-dimensional memory device according to another embodiment of the present application. As shown in fig. 3, the three-dimensional memory device according to this embodiment is different from the three-dimensional memory device 1000 as described above mainly in that the trench structure 400 includes a first trench structure 410 ', a second trench structure 420 ', and a third trench structure 430 ', and the pattern of the contact channel 500 has, for example, a circular profile on the surface of the substrate. The remaining structure and arrangement are the same as those of the above-described embodiment, and therefore, a repetitive description will not be made.

Referring to fig. 3, in a direction in which the first groove structure 410 ' horizontally extends (e.g., a D1 direction), the contact passage 500 ' may not be provided, and the second groove structure 420 ', the third groove structure 430 ' may be alternately disposed along the same horizontal direction (e.g., a D1 direction) as the contact passage 500 '.

In this embodiment, the first groove structure 410' may continuously extend along the extending direction (e.g., the D1 direction) of the gate slit structure 300. The second and third groove structures 420 'and 430' may intermittently extend along an extending direction (e.g., a D1 direction) of the gate gap structure 300. The third groove structure 430 'may be disposed between adjacent two contact channels 500'. As shown, the length of the orthographic projection of the first groove structure 410 ' on the surface of the substrate may be greater than the length of the orthographic projection of the second groove structure 420 ' and the third groove structure 430 ' on the surface of the substrate.

In the present embodiment, the plurality of trench structures 400 in the adjacent two sub-divided regions (e.g., 211, 212, and 213) may be arranged to be symmetrical with respect to the second gate slit structure 320 therebetween when viewed on a plane. Specifically, the groove structures 410 ', 420 ', and 430 ' in the

sub-dividing regions

211 and 212 may be arranged to be symmetrical with respect to the second gate slit structure 320 therebetween when viewed on a plane. In addition, the groove structures 410 ', 420 ', and 430 ' in the

sub-dividing regions

212 and 213 may be arranged to be symmetrical with respect to the second gate slit structure 320 therebetween when viewed on a plane. In addition, in the

sub-dividing regions

211 and 212, the second and third trench structures 420 ' and 430 ' may be disposed adjacent to the gate line gap 300 structure (e.g., the second gate line gap structure 320) between the adjacent two dividing regions 210, and the first trench structure 410 ' may be disposed away from the gate line gap structure 300 (e.g., the second gate line gap structure 320) between the adjacent two dividing regions 210. Alternatively or additionally, for example in the

sub-dividing regions

212 and 213, the first trench structure 410 ' may be disposed adjacent to the gate gap structure 300 (e.g., the second gate gap structure 320) between two adjacent dividing regions 210, and the second trench structure 420 ' and the third trench structure 430 ' may be disposed away from the gate gap structure 300 (e.g., the second gate gap structure 320) between two adjacent dividing regions 210. The twisted windows of the gate line gap structure can be further improved by the symmetrical arrangement of the trench structure 400 at both sides of the second gate line gap structure 320.

In this embodiment, the pattern of contact channels 500 has, for example, a circular profile on the surface of the substrate. However, this is exemplary and not limiting. It should be understood that the manner in which the slot structure 400 extends and the pattern profile of the contact channels 500 can have a variety of variations. Various changes and combinations may be made to the examples in the above embodiments without departing from the spirit and scope of the invention.

FIG. 4 illustrates a schematic top view of a portion of a three-dimensional memory device according to another embodiment of the present application. As shown in fig. 4, the three-dimensional memory device according to this embodiment differs from the three-dimensional memory device 1000 as described above mainly in that the gate slit structure 300 extends through the memory array region 201 and the step region 202 in the direction D1, respectively, i.e., the gate slit structure 300 is not continuously disconnected from the memory array region 201 and the step region 202, but is disconnected at the interface region of the memory array region 201 and the step region 202. The remaining structure and arrangement are the same as those of the above-described embodiment, and therefore, a repetitive description will not be made. It should be understood that the memory array region 201 and the step region 202 may have other arrangements, for example, the gate gap structures 300 in the memory array region 201 and the step region 202 are not necessarily arranged side by side along the direction D1. It should also be understood that the manner in which the trench structures 400 extend, the pattern profile of the contact vias 500, and the arrangement of the grid gap structures 300 may vary widely. Various changes and combinations may be made to the examples in the above embodiments without departing from the spirit and scope of the invention.

According to the three-dimensional storage device of the above embodiment of the application, through the design of the strip-shaped groove structure and the symmetrical arrangement of the strip-shaped groove structure on the plane, the influence of stress release on the gate line can be effectively relieved, the defect that the gate line gap structure is distorted and deformed and even has similar mouse tooth marks can be avoided, the window of the distortion and deformation of the gate line gap structure can be further improved, the supporting force of a step area can be increased, and therefore the yield and the reliability of the three-dimensional storage device can be remarkably improved.

Fig. 5 is an exemplary flowchart of a method of manufacturing a three-dimensional memory according to an embodiment of the present application. The three-dimensional memory of the present application can be manufactured according to the manufacturing method, and therefore the drawings and the description of the three-dimensional memory of the present application described above are suitable for explaining the manufacturing method of the three-dimensional memory of this embodiment. Referring to fig. 5, the manufacturing method of this embodiment includes the steps of:

step S510: providing a substrate 100;

step S520: forming a stack structure 200 including gate layers 2002 and insulating layers 2001 which are alternately stacked on a substrate 100, the stack structure 200 including a memory array region 201 and a step region 202;

step S530: forming a trench structure 400 penetrating the stacked structure 200 in the stacked structure 200 located at the step region 202, the trench structure 400 extending in a first direction; and

step S540: at least one gate line gap structure 300 is formed in the stack structure 200, the at least one gate line gap structure 300 extending in the first direction and dividing the stack structure 200 in the step region into at least two separation regions 210.

The substrate 100, the stacked structure 200, the gate line gap structure 300, and the trench structure 400 formed in the above steps can refer to the description of fig. 1 to 3, and will not be expanded herein.

In an exemplary embodiment, the method may further include step S440: a plurality of contact vias 500 are formed in the stacked structure 200 in the stepped region 202, and each contact via 500 penetrates through the gate layer 2002 on each step of the stepped region 202.

In an exemplary embodiment, forming the trench structure 400 may include: the first and

second groove structures

410 and 420 are formed, wherein the contact channels 500 may not be disposed in a direction in which the first groove structure 410 horizontally extends, and the second groove structures 420 and the contact channels 500 may be alternately disposed in the same horizontal direction.

In an exemplary embodiment, a length of an orthographic projection of the first groove structure 410 on the surface of the substrate 100 may be greater than a length of an orthographic projection of the second groove structure 420 on the surface of the substrate 100.

In an exemplary embodiment, the first and

second groove structures

410 and 420 may intermittently extend along an extending direction of the gate gap structure 300.

In an exemplary embodiment, the first groove structure 410 may continuously extend along the extending direction of the gate gap structure 300, and the second groove structure 420 may discontinuously extend along the extending direction of the gate gap structure 300.

In an exemplary embodiment, the first groove structure 410 may be disposed adjacent to the gate line gap structure 300 between two adjacent partition regions 210, and the second groove structure 420 may be disposed away from the gate line gap structure 300 between two adjacent partition regions 210.

In an exemplary embodiment, the second trench structure 420 may be disposed adjacent to the gate line gap structure 300 between two adjacent partition regions 210, and the first trench structure 410 may be disposed away from the gate line gap structure 300 between two adjacent partition regions 210.

In an exemplary embodiment, the method may further include the steps of: in the case of a memory array: a plurality of channel structures 600 are formed through the stacked structure 200 in the stacked structure 200 of 201.

In an exemplary embodiment, forming the at least one gate line gap structure 300 may include: a first gate-and-gap structure 310 is formed at least in the stacked structure of the step region, and the first gate-and-gap structure 310 divides the stacked structure 200 into at least two block-separating regions 210.

In an exemplary embodiment, forming the at least one gate line gap structure 300 may further include: a second gate slit structure 320 is formed in the block separation region 210, and the second gate slit structure 320 divides the block separation region 210 into at least two sub-separation regions (e.g., 211, 212, and 213).

In an exemplary embodiment, the plurality of trench structures 400 in adjacent two sub-divided regions (e.g., 211, 212, and 213) may be symmetrically arranged with respect to the second gate slit structure 320.

In an exemplary embodiment, an orthographic projection of the trench structure 400 on the surface of the substrate 100 may have a stripe-shaped profile.

In an exemplary embodiment, the trench structures 400 in the adjacent two separation regions 210 may be arranged to be symmetrical with respect to the gate gap structure 300 between the adjacent two separation regions 210 when viewed on a plane.

In an exemplary embodiment, the trench structure 400 may be dummy channel structures, each of which may include: a dummy channel hole penetrating the stacked structure in a direction perpendicular to the substrate, and an oxide layer formed along a sidewall of the dummy channel hole.

According to the manufacturing method of the three-dimensional memory device, through the design of the strip-shaped grooves of the groove structures and the symmetrical arrangement of the grid line gap structures on the plane, the influence of stress release on the grid lines can be effectively relieved, the defects that the grid line gap structures are distorted and deformed and even similar to mouse tooth marks can be avoided, the distorted and deformed windows of the grid line gap structures can be further improved, the step area supporting force can be increased, and therefore the yield and the reliability of the three-dimensional memory device can be remarkably improved.

It should be understood by those skilled in the art that other configurations and functions of the three-dimensional memory device and the method for manufacturing the same according to the embodiments of the present application are known to those skilled in the art, and the detailed description of the embodiments of the present application is omitted to reduce redundancy.

At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A three-dimensional memory device, comprising:

a substrate;

a stack structure formed on the substrate and including gate layers and insulating layers alternately stacked, the stack structure having a memory array region and a step region arranged in a first direction;

at least one gate line gap structure extending through the step region at least in the first direction, dividing the stacked structure into a plurality of divided regions;

a trench structure disposed along the first direction and penetrating the stacked structure at the stepped region; and

a plurality of contact channels located in the step regions, each of the contact channels being connected to the gate layer on each of the steps of the step regions, respectively,

wherein the slot structure comprises a first slot structure and a second slot structure,

the contact channels are not provided in the direction in which the first groove structure extends horizontally,

the second groove structures are alternately arranged with the contact passages in a direction in which the second groove structures horizontally extend.

2. The three-dimensional memory device of claim 1, wherein an orthographic length of the first trench structure on the surface of the substrate is greater than an orthographic length of the second trench structure on the surface of the substrate.

3. The three-dimensional memory device of claim 1, wherein the first and second trench structures extend intermittently along the first direction.

4. The three-dimensional memory device of claim 1, wherein the first trench structure extends continuously along the first direction and the second trench structure extends discontinuously along the first direction.

5. The three-dimensional memory device of claim 1, wherein the first trench structure is disposed adjacent to the gate line gap structure between two adjacent spaced apart regions, and the second trench structure is disposed away from the gate line gap structure between two adjacent spaced apart regions.

6. The three-dimensional memory device of claim 1, wherein the second trench structure is disposed adjacent to the gate line gap structure between two adjacent spaced apart regions, and the first trench structure is disposed away from the gate line gap structure between two adjacent spaced apart regions.

7. The three-dimensional memory device of claim 1, wherein an orthographic projection of at least one of the contact vias on the surface of the substrate has a square profile.

8. The three-dimensional memory device of claim 1, wherein an orthographic projection of at least one of the contact vias on the surface of the substrate has a circular profile.

9. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device further comprises a plurality of channel structures extending through the stacked structure in the memory array region, wherein each of the channel structures comprises: the semiconductor device comprises a channel hole penetrating through the stacked structure along a direction perpendicular to the substrate, and a functional layer and a channel layer which are sequentially stacked from outside to inside along a side wall of the channel hole.

10. The three-dimensional memory device of claim 9, wherein an orthographic projection of at least one of the channel structures on the surface of the substrate has a circular profile.

11. The three-dimensional memory device of claim 1, wherein an orthographic projection of the trench structures on the surface of the substrate has a striped profile.

12. The three-dimensional memory device of claim 1, wherein the trench structures in two adjacent separation regions are arranged symmetrically with respect to the gate line gap structure between the two adjacent separation regions when viewed in plan.

13. The three-dimensional memory device of claim 1, wherein the trench structures are dummy channel structures, each of the dummy channel structures comprising: a dummy channel hole penetrating the stacked structure in a direction perpendicular to the substrate, and an oxide layer formed along a sidewall of the dummy channel hole.

14. The three-dimensional memory device of claim 1, wherein the three-dimensional memory device is a three-dimensional NAND flash memory.

15. A method of fabricating a three-dimensional memory device, comprising:

providing a substrate;

forming a stack structure including gate layers and insulating layers alternately stacked on the substrate, the stack structure including a memory array region and a step region;

forming a trench structure in the stacked structure at the step region, the trench structure extending in a first direction, through the stacked structure;

forming at least one gate line gap structure in the stacked structure, the at least one gate line gap structure extending in the first direction and dividing the stacked structure in the step region into at least two separation regions; and

forming a plurality of contact vias in the stacked structure at the step region, each of the contact vias being connected to the gate layer on each step of the step region, respectively,

wherein forming the trench structure comprises: a first trench structure and a second trench structure are formed,

16. The manufacturing method according to claim 15, wherein an orthographic length of the first groove structure on the surface of the substrate is larger than an orthographic length of the second groove structure on the surface of the substrate.

17. The method of manufacturing of claim 15, wherein the first and second slot structures extend intermittently along the first direction.

18. The method of manufacturing of claim 15, wherein the first groove structure extends continuously along the first direction and the second groove structure extends intermittently along the first direction.

19. The manufacturing method according to claim 15, wherein the first trench structure is arranged adjacent to the gate line gap structure between two adjacent separation regions, and the second trench structure is arranged away from the gate line gap structure between two adjacent separation regions.

20. The manufacturing method according to claim 15, wherein the second trench structure is arranged adjacent to the gate line gap structure between two adjacent separation regions, and the first trench structure is arranged away from the gate line gap structure between two adjacent separation regions.

21. The method of manufacturing according to claim 15, further comprising forming a plurality of channel structures through the stacked structure in the stacked structure at the memory array region.

22. The manufacturing method according to claim 15, wherein an orthographic projection of the groove structure on the surface of the substrate has a stripe-shaped profile.

23. The manufacturing method according to claim 15, wherein the groove structures in two adjacent divided regions are arranged symmetrically with respect to the gate line gap structure between the two adjacent divided regions when viewed on a plane.

24. The method of manufacturing of claim 15, wherein the trench structures are dummy channel structures, each of the dummy channel structures comprising: a dummy channel hole penetrating the stacked structure in a direction perpendicular to the substrate, and an oxide layer formed along a sidewall of the dummy channel hole.

25. A memory system comprising the three-dimensional memory device according to any one of claims 1 to 14 or the three-dimensional memory device manufactured according to the manufacturing method of any one of claims 15 to 24.