CN113297091A - SoC chip debugging method and device and SoC chip - Google Patents
SoC chip debugging method and device and SoC chip Download PDFInfo
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- CN113297091A CN113297091A CN202110664480.1A CN202110664480A CN113297091A CN 113297091 A CN113297091 A CN 113297091A CN 202110664480 A CN202110664480 A CN 202110664480A CN 113297091 A CN113297091 A CN 113297091A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/44—Program or device authentication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
Abstract
The invention provides a debugging method and a debugging device of a SoC chip and the SoC chip, wherein the method comprises the following steps: receiving an authentication request sent by a main CPU; authenticating the main CPU according to the authentication request; if the authentication is passed, sending an authentication success indication to the main CPU; receiving a sensitive debugging command sent by a main CPU; acquiring sensitive state information according to the sensitive debugging command; generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information; and sending the sensitive debugging result to the main CPU so that the main CPU can acquire the decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first check information is checked to pass. The method and the device can safely acquire the execution states of the sensitive resources and the sensitive areas of the secure firmware in the SoC chip.
Description
Technical Field
The invention relates to the technical field of system on chip, in particular to a debugging method and device of an SoC chip and the SoC chip.
Background
A System on Chip (SoC), also referred to as a System on Chip or SoC Chip. The SoC chip has a built-in secure processor, i.e., a secure CPU, in addition to an integrated general-purpose processor, i.e., a main CPU. The main CPU runs an operating system and application programs. The secure CPU runs firmware for system security control. In order to meet the actual application requirements, the SoC chip is usually further provided with sensitive resources, such as special function IPs like a cryptographic algorithm IP, to assist in achieving system-level security requirements. For security reasons, such sensitive resources are only accessible to the secure CPU (privileged module belonging to the SoC), and the firmware executed by the secure CPU (which may be referred to as secure firmware) contains control and status information related to the sensitive resources.
For a mass production SoC chip containing sensitive resources, the SoC chip is set to a safe state when it leaves the factory, and at this time, the general purpose processor (belonging to the SoC non-privileged module) does not allow to acquire the sensitive resources inside the chip and the execution state of the secure firmware sensitive area.
However, in practical applications, there is also a debugging requirement for SoC chips in a secure state. For example, a general purpose processor needs to access some sensitive resources in the chip when running some programs, such as consistency testing, problem debugging, and factory return detection. For the system on chip, the security processor belongs to a privileged module and has access operation authority of sensitive resources even in a security state. The secure processor and its firmware may open a communication interface to the general purpose processor. During specific debugging, a hardware debugging tool is used for running a debugging program on the main CPU. The hardware debugging tool is a debugging device and can access internal resources of the SoC through a hardware debugging interface of the SoC.
Therefore, when the SoC chip is debugged by using the hardware debugging tool, how to securely obtain the execution states of the sensitive resources and the sensitive areas of the secure firmware inside the SoC chip is a problem that must be solved.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and an apparatus for debugging an SoC chip, and an SoC chip, which can securely obtain the execution states of the sensitive resources and the sensitive areas of the secure firmware inside the SoC chip.
In a first aspect, the present invention provides a method for debugging an SoC chip, where the method is applied to a secure CPU of the SoC chip, and the method includes:
receiving an authentication request sent by a main CPU;
authenticating the main CPU according to the authentication request;
if the authentication is passed, sending an authentication success indication to the main CPU;
receiving a sensitive debugging command sent by a main CPU;
acquiring sensitive state information according to the sensitive debugging command;
generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information;
and sending the sensitive debugging result to a main CPU so that the main CPU can acquire decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first check information is verified.
Optionally, the authenticating the main CPU according to the authentication request includes:
generating a first public-private key pair according to the authentication request;
sending a public key of a first public-private key pair to a main CPU so that the main CPU can obtain a public key of a second public-private key pair and first authentication information, wherein the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared by a secure CPU and the outside;
receiving a public key and first authentication information of a second public-private key pair sent by a main CPU;
generating a second shared secret key according to the private key of the first public-private secret key pair and the public key of the second public-private secret key pair;
generating second authentication information from the second shared key and the shared secret;
and comparing the first authentication information with the second authentication information, if the first authentication information and the second authentication information are equal, the authentication is passed, otherwise, the authentication is not passed.
Optionally, the generating a sensitive debugging result according to the sensitive state information includes:
calculating to obtain first check information according to a second shared secret key and the sensitive state information;
and encrypting the sensitive state information by using a second shared secret key to generate encrypted sensitive state information.
Optionally, the obtaining of the first verification information by calculating according to the second shared key and the sensitive state information includes:
and calculating the HMAC of the sensitive state information according to the second shared secret key to obtain first check information.
Optionally, the method further comprises:
receiving a common debugging command sent by a main CPU;
acquiring non-sensitive state information according to the common debugging command;
and sending the non-sensitive state information to a main CPU.
In a second aspect, the present invention provides a method for debugging an SoC chip, where the method is applied to a main CPU of the SoC chip, and the method includes:
sending an authentication request to the secure CPU so that the secure CPU authenticates the main CPU;
if the main CPU passes the authentication of the safety CPU, receiving an authentication success indication sent by the safety CPU;
sending a sensitive debugging command to a secure CPU (central processing unit) so that the secure CPU can generate a sensitive debugging result, wherein the sensitive debugging result comprises encrypted sensitive state information and first verification information;
receiving a sensitive debugging result sent by a safety CPU;
and acquiring decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
Optionally, the sending an authentication request to the secure CPU so that the secure CPU authenticates the main CPU includes:
sending an authentication request to a secure CPU so that the secure CPU generates a first public and private key pair;
receiving a public key of a first public-private key pair sent by a secure CPU;
acquiring a public key and first authentication information of a second public-private key pair, wherein the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared by a secure CPU and the outside;
and sending the public key of the second public-private key pair and the first authentication information to a security CPU (central processing unit), so that the security CPU generates a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair, generates second authentication information according to the second shared key and the shared secret, compares the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
Optionally, the obtaining the public key and the first authentication information of the second public-private key pair includes:
sending the public key of the first public-private key pair to the authentication server so that the authentication server performs the following operations: generating a second public-private key pair, generating a first shared key according to a private key of the second public-private key pair and a public key of the first public-private key pair, generating first authentication information according to the first shared key and a shared secret, and sending the public key of the second public-private key pair and the first authentication information to a main CPU (central processing unit), wherein the shared secret is fixed secret information shared by a security CPU (central processing unit) and an authentication server;
and receiving the public key and the first authentication information of the second public-private key pair sent by the authentication server.
Optionally, the obtaining the decrypted sensitive status information includes:
sending the encrypted sensitive status information and the first verification information to the authentication server so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and receiving the decrypted sensitive state information sent by the authentication server.
Optionally, the method further comprises:
sending a common debugging command to the secure CPU so that the secure CPU can acquire non-sensitive state information;
and receiving non-sensitive state information sent by the safety CPU.
In a third aspect, the present invention provides a debugging apparatus for SoC chip, the apparatus being applied to a secure CPU of SoC chip, the apparatus comprising:
the first receiving module is used for receiving an authentication request sent by the main CPU;
the authentication module is used for authenticating the main CPU according to the authentication request;
the first sending module is used for sending an authentication success indication to the main CPU if the authentication passes;
the second receiving module is used for receiving the sensitive debugging command sent by the main CPU;
the first acquisition module is used for acquiring sensitive state information according to the sensitive debugging command;
the first generation module is used for generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information;
and the second sending module is used for sending the sensitive debugging result to the main CPU so that the main CPU can acquire the decrypted sensitive state information, and the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
Optionally, the authentication module comprises:
a first public-private key pair generation unit, configured to generate a first public-private key pair according to the authentication request;
a first public key sending unit, configured to send a public key of a first public-private key pair to a master CPU, so that the master CPU obtains a public key of a second public-private key pair and first authentication information, where the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared between a secure CPU and an external device;
the second public key receiving unit is used for receiving a public key of a second public-private key pair and first authentication information sent by the main CPU;
the second shared key generating unit is used for generating a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair;
a second authentication information generation unit configured to generate second authentication information from the second shared key and the shared secret;
and the comparison unit is used for comparing the first authentication information with the second authentication information, if the first authentication information and the second authentication information are equal, the authentication is passed, and otherwise, the authentication is not passed.
Optionally, the first generating module comprises:
the first verification information calculation unit is used for calculating to obtain first verification information according to a second shared secret key and the sensitive state information;
and the encryption unit is used for encrypting the sensitive state information by using a second shared secret key to generate encrypted sensitive state information.
Optionally, the first verification information calculating unit is configured to calculate an HMAC of the sensitive state information according to the second shared key, so as to obtain the first verification information.
Optionally, the apparatus further comprises:
the third receiving module is used for receiving a common debugging command sent by the main CPU;
the second acquisition module is used for acquiring non-sensitive state information according to the common debugging command;
and the third sending module is used for sending the non-sensitive state information to the main CPU.
In a fourth aspect, the present invention provides a debugging apparatus for SoC chip, the apparatus being applied to a main CPU of SoC chip, the apparatus comprising:
the fourth sending module is used for sending an authentication request to the secure CPU so that the secure CPU can authenticate the main CPU;
the fourth receiving module is used for receiving an authentication success indication sent by the safety CPU if the safety CPU passes the authentication of the main CPU;
the fifth sending module is used for sending a sensitive debugging command to the secure CPU so that the secure CPU can generate a sensitive debugging result, and the sensitive debugging result comprises encrypted sensitive state information and first check information;
the fifth receiving module is used for receiving the sensitive debugging result sent by the safety CPU;
and the third acquisition module is used for acquiring the decrypted sensitive state information, and the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
Optionally, the fourth sending module includes:
the authentication request sending unit is used for sending an authentication request to the secure CPU so that the secure CPU generates a first public and private key pair;
the first public key receiving unit is used for receiving a public key of a first public-private key pair sent by the security CPU;
a second public key obtaining unit, configured to obtain a public key of a second public-private key pair and first authentication information, where the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared between the secure CPU and the outside;
and the second public key sending unit is used for sending the public key of the second public-private key pair and the first authentication information to the security CPU so that the security CPU can generate a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair, generate second authentication information according to the second shared key and the shared secret, compare the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
Optionally, the second public key obtaining unit includes:
a first public key sending subunit, configured to send a public key of the first public-private key pair to the authentication server, so that the authentication server performs the following operations: generating a second public-private key pair, generating a first shared key according to a private key of the second public-private key pair and a public key of the first public-private key pair, generating first authentication information according to the first shared key and a shared secret, and sending the public key of the second public-private key pair and the first authentication information to a main CPU (central processing unit), wherein the shared secret is fixed secret information shared by a security CPU (central processing unit) and an authentication server;
and the second public key receiving subunit is used for receiving the public key of the second public-private key pair and the first authentication information sent by the authentication server.
Optionally, the third obtaining module includes:
an encrypted information sending unit, configured to send the encrypted sensitive status information and the first verification information to the authentication server, so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and the decryption information receiving unit is used for receiving the decrypted sensitive state information sent by the authentication server.
Optionally, the apparatus further comprises:
the sixth sending module is used for sending a common debugging command to the secure CPU so that the secure CPU can obtain the non-sensitive state information;
and the sixth receiving module is used for receiving the non-sensitive state information sent by the safety CPU.
In a fifth aspect, the present invention provides an SoC chip, including:
a secure CPU;
a first memory communicatively coupled to the secure CPU;
the first memory stores instructions executable by the secure CPU, the secure CPU implementing the method as provided in the first aspect when executing the instructions on the first memory;
a main CPU;
a second memory communicatively coupled to the main CPU;
the second memory stores instructions executable by the main CPU, which when executing the instructions on the second memory implements the method as provided in the second aspect.
According to the debugging method and device of the SoC chip and the SoC chip, the hardware debugging tool is authenticated by the identity authentication mechanism based on key agreement, after the authentication is passed, the negotiated key is used for carrying out encryption transmission on the sensitive state information, meanwhile, the verification mechanism is introduced, and only after the verification is passed, the decrypted sensitive state information can be finally obtained. The method and the device can safely acquire the execution states of the sensitive resources and the sensitive areas of the secure firmware in the SoC chip.
Drawings
Fig. 1 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention;
fig. 2 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention;
fig. 3 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention;
fig. 4 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention;
fig. 5 is an interaction flow diagram of a debugging method of an SoC chip according to an embodiment of the present invention;
FIG. 6 is a block diagram of a debugging apparatus of an SoC chip;
FIG. 7 is a block diagram of a debugging apparatus of an SoC chip;
FIG. 8 is a block diagram of a debugging apparatus of an SoC chip;
fig. 9 is a block diagram of a debugging apparatus of an SoC chip.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Fig. 1 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention. The method is applied to a secure CPU of an SoC chip, and as shown in fig. 1, the debugging method of the SoC chip may include steps S101 to S107.
In step S101, an authentication request transmitted by the main CPU is received.
In step S102, the main CPU is authenticated according to the authentication request.
The secure CPU may authenticate the main CPU in various forms, for example, in this embodiment, authenticating the main CPU includes:
first, the secure CPU generates a first public-private key pair (K1, P1) according to the authentication request, where K1 is a private key of the first public-private key pair and P1 is a public key of the first public-private key pair.
Then, the public key P1 of the first public-private key pair is sent to the main CPU, so that the main CPU obtains the public key P2 of the second public-private key pair (K2, P2) and the first authentication information Auth1, the first authentication information Auth1 is generated according to the first shared key Ks1 and the shared secret, the first shared key Ks1 is generated according to the private key K2 of the second public-private key pair and the public key P1 of the first public-private key pair, and the shared secret is fixed secret information shared by the secure CPU and the outside.
Next, the public key P2 of the second public-private key pair and the first authentication information Auth1 transmitted by the host CPU are received.
Then, a second shared key Ks2 is generated from the private key K1 of the first public-private key pair and the public key P2 of the second public-private key pair. Ks2 and Ks1 are mutually authenticated shared keys obtained based on a key agreement mechanism.
Next, the second authentication information Auth2 is generated based on the second shared key Ks2 and the shared secret. As an embodiment, a Hash value is calculated for the "shared secret + shared key Ks 2", and authentication information Auth2 is generated. Of course, the calculation mode of the authentication information Auth may be changed, but a shared secret and a shared secret are necessarily used.
And finally, comparing the first authentication information Auth1 with the second authentication information Auth2, if the first authentication information Auth1 and the second authentication information Auth2 are equal, the authentication is passed, otherwise, the authentication is not passed.
In step S103, if the authentication is passed, an authentication success indication is sent to the main CPU.
In step S104, a sensitive debug command sent by the main CPU is received.
In step S105, sensitive status information is obtained according to the sensitive debugging command.
In this embodiment, the sensitive status information includes status information of the sensitive resource and the secure firmware.
In step S106, a sensitive debugging result is generated according to the sensitive state information, where the sensitive debugging result includes the encrypted sensitive state information and the first verification information.
The first check information is subsequently used for checking when the decrypted sensitive state information is obtained, and the decrypted sensitive state information can be obtained only if the check is passed.
Specifically, based on the foregoing embodiment, the secure CPU has generated the second shared key Ks 2. Therefore, according to the sensitive state information, generating the sensitive debugging result can be realized as follows:
calculating to obtain first verification information according to the second shared secret key Ks2 and the sensitive state information; the sensitive state information is encrypted using the second shared key Ks2 to generate encrypted sensitive state information.
Further, the first check information may use HMAC of the sensitive status information. Namely, the HMAC of the unencrypted sensitive status information is calculated according to the second shared key Ks2, so as to obtain the first check information. In this embodiment, an HMAC (Hash-based Message Authentication Code) is a way to calculate a Hash value of a Message based on a key, and is often used for Message integrity check. It should be noted that, the verification information of the sensitive status information may also use other ways such as signature instead of using HMAC; the HMAC may not be calculated using the shared key, but the shared key must be involved in the calculation of the verification information.
In step S107, the sensitive debugging result is sent to the main CPU, so that the main CPU obtains the decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first check information is verified.
Fig. 2 is a flowchart of a debugging method of an SoC chip according to another embodiment of the present invention. The method is applied to a secure CPU of an SoC chip, and as shown in fig. 2, the debugging method of the SoC chip may include steps S201 to S210.
In step S201, an authentication request transmitted by the main CPU is received.
In step S202, the main CPU is authenticated according to the authentication request.
In step S203, if the authentication is passed, an authentication success indication is sent to the main CPU.
In step S204, a normal debug command sent by the main CPU is received.
In step S205, non-sensitive status information is obtained according to the normal debug command.
In step S206, the non-sensitive status information is sent to the main CPU.
In step S207, a sensitive debug command sent by the main CPU is received.
In step S208, sensitive status information is obtained according to the sensitive debugging command.
In step S209, a sensitive debugging result is generated according to the sensitive status information, where the sensitive debugging result includes the encrypted sensitive status information and the first check information.
In step S210, the sensitive debugging result is sent to the main CPU, so that the main CPU obtains the decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first check information is verified.
Compared with the foregoing embodiment, the present embodiment adds debugging of a common debugging command, and other steps are the same as those in the foregoing embodiment, and a specific implementation method may refer to the foregoing embodiment and will not be described again.
The debugging method of the SoC chip provided by the embodiment of the invention is applied to a safe CPU of the SoC chip, when debugging is carried out, firstly, an identity authentication mechanism based on key agreement authenticates a hardware debugging tool (through a main CPU), after the authentication is passed, the negotiated key is utilized to complete encryption transmission of sensitive state information, and meanwhile, a verification mechanism is introduced, and only if the verification is passed, the decrypted sensitive state information can be finally obtained. The embodiment of the invention can safely acquire the execution states of the sensitive resources and the sensitive areas of the secure firmware in the SoC chip.
Fig. 3 is a flowchart of a debugging method of an SoC chip according to an embodiment of the present invention. The method is applied to a main CPU of an SoC chip, and as shown in FIG. 3, the debugging method of the SoC chip can comprise steps S301-S305.
In step S301, an authentication request is sent to the secure CPU so that the secure CPU authenticates the main CPU.
As an embodiment, the specific authentication process is as follows:
first, the host CPU sends an authentication request to the secure CPU so that the secure CPU generates a first public-private key pair (K1, P1), where K1 is a private key of the first public-private key pair and P1 is a public key of the first public-private key pair.
Then, the public key P1 of the first public-private key pair sent by the secure CPU is received.
Then, a public key P2 of the second public-private key pair and first authentication information Auth1 are obtained, the first authentication information Auth1 is generated according to a first shared key Ks1 and a shared secret, the first shared key Ks1 is generated according to a private key K2 of the second public-private key pair and a public key P1 of the first public-private key pair, and the shared secret is fixed secret information shared by the secure CPU and the outside.
And finally, sending a public key P2 of the second public-private key pair and first authentication information Auth1 to the secure CPU, so that the secure CPU generates a second shared key Ks2 according to a private key K1 of the first public-private key pair and a public key P2 of the second public-private key pair, generates second authentication information Auth2 according to the second shared key Ks2 and the shared secret, and compares the first authentication information Auth1 with the second authentication information Auth2, wherein if the first authentication information Auth1 and the second authentication information Auth2 are equal, the authentication is passed, and otherwise, the authentication is not passed.
Further, in the above authentication process, acquiring the public key P2 of the second public-private key pair and the first authentication information Auth1 includes:
sending the public key P1 of the first public-private key pair to the authentication server, so that the authentication server performs the following operations: generating a second public-private key pair (K2, P2), wherein K2 is a private key and P2 is a public key, generating a first shared key Ks1 according to the private key K2 of the second public-private key pair and the public key P1 of the first public-private key pair, generating first authentication information Auth1 according to the first shared key Ks1 and a shared secret, and sending the public key P2 of the second public-private key pair and the first authentication information Auth1 to the main CPU, wherein the shared secret is fixed secret information shared by the secure CPU and the authentication server;
and receiving the public key P2 of the second public-private key pair and the first authentication information Auth1 sent by the authentication server.
In this embodiment, the public key P2 of the second public-private key pair and the first authentication information Auth1 are not generated by the host CPU itself, and by providing an authentication server at a remote end, the authentication server is maintained by the chip manufacturer, and the public key P2 of the second public-private key pair and the first authentication information Auth1 are generated by the authentication server and fed back to the host CPU.
In step S302, if the secure CPU passes the authentication of the main CPU, an authentication success instruction sent by the secure CPU is received.
In step S303, a sensitive debugging command is sent to the secure CPU, so that the secure CPU generates a sensitive debugging result, where the sensitive debugging result includes the encrypted sensitive state information and the first check information.
The first check information is subsequently used for checking when the decrypted sensitive state information is obtained, and the decrypted sensitive state information can be obtained only if the check is passed.
In step S304, the sensitive debugging result sent by the secure CPU is received.
In step S305, the decrypted sensitive status information is obtained, and the decrypted sensitive status information is obtained after the encrypted sensitive status information is decrypted and the first verification information is verified.
In this embodiment, the main CPU obtains the decrypted sensitive state information, and is also assisted by the authentication server provided at the remote end. As an embodiment, obtaining the decrypted sensitive status information includes:
sending the encrypted sensitive status information and the first verification information to the authentication server so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and receiving the decrypted sensitive state information sent by the authentication server.
Specifically, the authentication server decrypts the encrypted sensitive state information using the first shared key Ks1, and calculates the HMAC of the decrypted sensitive state information using the first shared key Ks1, to obtain the second check-up information. And comparing the first check information with the second check information, if the first check information and the second check information are equal, the check is passed, and the decrypted sensitive state information is sent to the main CPU, and if the check is not passed, the decrypted sensitive state information is not sent to the main CPU.
Fig. 4 is a flowchart of a debugging method of an SoC chip according to another embodiment of the present invention. The method is applied to a main CPU of an SoC chip, and as shown in FIG. 4, the debugging method of the SoC chip can comprise steps S401-S407.
In step S401, an authentication request is sent to the secure CPU so that the secure CPU authenticates the main CPU.
In step S402, if the secure CPU passes the authentication of the main CPU, an authentication success instruction sent by the secure CPU is received.
In step S403, a normal debug command is sent to the secure CPU so that the secure CPU acquires the non-sensitive status information.
In step S404, non-sensitive status information sent by the secure CPU is received.
In step S405, a sensitive debugging command is sent to the secure CPU, so that the secure CPU generates a sensitive debugging result, where the sensitive debugging result includes encrypted sensitive state information and first check information.
In step S406, the sensitive debugging result sent by the secure CPU is received.
In step S407, the decrypted sensitive status information is obtained, where the decrypted sensitive status information is obtained after the encrypted sensitive status information is decrypted and the first check information is verified.
Compared with the foregoing embodiment, the present embodiment adds debugging of a common debugging command, and other steps are the same as those in the foregoing embodiment, and a specific implementation method may refer to the foregoing embodiment and will not be described again.
The debugging method of the SoC chip provided by the embodiment of the invention is applied to a main CPU of the SoC chip, when debugging is carried out, firstly, an identity authentication mechanism based on key agreement authenticates a hardware debugging tool (through the main CPU), after the authentication is passed, the negotiated key is utilized to complete encryption transmission of sensitive state information, and meanwhile, a verification mechanism is introduced, and only if the verification is passed, the decrypted sensitive state information can be finally obtained. The embodiment of the invention can safely acquire the execution states of the sensitive resources and the sensitive areas of the secure firmware in the SoC chip.
To facilitate understanding of the overall technical solution, fig. 5 shows an overall flow of an embodiment of the overall technical solution. As shown in fig. 5, the method comprises the following steps:
1. the main CPU sends an authentication request to the secure CPU.
2. The secure CPU generates a set of random public-private key pairs, noted (K1, P1), and returns the public key P1 to the host CPU.
3. The main CPU sends the public key P1 to the authentication server to request authentication information.
4. The authentication server generates a set of random public-private key pairs, denoted (K2, P2).
5. The authentication server generates a shared key Ks1 using the private key K2 and the public key P1.
6. The authentication server is maintained by the processor SoC chip vendor, who typically knows the fixed secret information (such as root keys, etc.) built into the SoC chip, which is shared by the authentication server with the secure CPU of the processor, referred to as a shared secret. The authentication server calculates a Hash value for the "shared secret + shared key Ks 1" to generate authentication information Auth 1.
7. The authentication server returns the public key P2 to the main CPU together with the authentication information Auth 1.
8. The main CPU sends the public key P2 and the authentication information Auth1 to the secure CPU.
9. The secure CPU generates a shared key Ks2 using K1 and P2, and calculates a Hash value for "shared secret + shared key Ks 2" to generate authentication information Auth 2.
10. Auth1 and Auth2 are compared, and if the Auth1 and the Auth2 are equal, the identity authentication is passed, and an authentication success indication is returned.
11. The main CPU initiates a normal debug command.
12. The secure CPU executes the normal debug command and returns the state information T of the plaintext.
13. The main CPU initiates a sensitive debug command.
14. The secure CPU obtains state information S of a self-sensitive region and sensitive resources, firstly calculates S-HMAC of the S by using Ks2, and then encrypts the S to generate a ciphertext S-ENC.
15. And returning the S-HMAC and the S-ENC to the main CPU.
16. And the main CPU sends the ciphertexts S-ENC and S-HMAC to the authentication server.
17. The authentication server decrypts the S-ENC by using the Ks1 to generate S ', calculates the HMAC of the S' by using the Ks1 to generate S-HMAC ', compares the S-HMAC and the S-HMAC', and checks if the S-HMAC and the S-HMAC are equal.
18. The authentication server returns the decrypted sensitive state information S' to the main CPU.
Therefore, the debugging information of the whole SoC chip can be completely acquired through the steps.
On the other hand, fig. 6 is a block diagram of a debugging apparatus of an SoC chip according to an embodiment of the present invention. As shown in fig. 6, the debugging apparatus of the SoC chip includes:
a first receiving module 601, configured to receive an authentication request sent by a main CPU;
an authentication module 602, configured to authenticate the main CPU according to the authentication request;
a first sending module 603, configured to send an authentication success indication to the main CPU if the authentication passes;
a second receiving module 604, configured to receive a sensitive debugging command sent by the main CPU;
a first obtaining module 605, configured to obtain sensitive state information according to the sensitive debugging command;
a first generating module 606, configured to generate a sensitive debugging result according to the sensitive state information, where the sensitive debugging result includes encrypted sensitive state information and first verification information;
the second sending module 607 is configured to send the sensitive debugging result to the main CPU, so that the main CPU obtains the decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first check information is checked to pass.
Further, the authentication module 602 includes:
a first public-private key pair generation unit, configured to generate a first public-private key pair according to the authentication request;
the first public key sending unit is used for sending the public key of the first public-private key pair to the main CPU so that the main CPU can obtain the public key of the second public-private key pair and first authentication information, the first authentication information is generated according to a first shared secret and a shared secret, the first shared secret is generated according to the private key of the second public-private key pair and the public key of the first public-private key pair, and the shared secret is fixed secret information shared by the secure CPU and the outside;
the second public key receiving unit is used for receiving a public key of a second public-private key pair and first authentication information sent by the main CPU;
the second shared key generating unit is used for generating a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair;
a second authentication information generation unit operable to generate second authentication information based on the second shared key and the shared secret;
and the comparison unit is used for comparing the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
Further, the first generating module 606 includes:
the first verification information calculation unit is used for calculating to obtain first verification information according to the second shared secret key and the sensitive state information;
and the encryption unit is used for encrypting the sensitive state information by using the second shared secret key to generate the encrypted sensitive state information.
Further, the first verification information calculation unit is configured to calculate an HMAC of the sensitive state information according to the second shared key, so as to obtain the first verification information.
Fig. 7 is a block diagram of a debugging apparatus of an SoC chip according to an embodiment of the present invention. As shown in fig. 7, the debugging apparatus of the SoC chip includes:
a first receiving module 701, configured to receive an authentication request sent by a main CPU;
an authentication module 702, configured to authenticate the main CPU according to the authentication request;
a first sending module 703, configured to send an authentication success indication to the main CPU if the authentication passes;
a third receiving module 704, configured to receive a general debugging command sent by the main CPU;
a second obtaining module 705, configured to obtain non-sensitive state information according to the common debugging command;
a third sending module 706, configured to send the non-sensitive state information to the main CPU;
a second receiving module 707, configured to receive a sensitive debugging command sent by the main CPU;
a first obtaining module 708, configured to obtain sensitive status information according to the sensitive debugging command;
a first generating module 709, configured to generate a sensitive debugging result according to the sensitive state information, where the sensitive debugging result includes encrypted sensitive state information and first verification information;
the second sending module 710 is configured to send the sensitive debugging result to the main CPU, so that the main CPU obtains the decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first check information is verified.
The debugging device for SoC chips provided in the embodiments of the present invention is corresponding to the foregoing method embodiments applied to the secure CPU, and specific work flows and effects may refer to the foregoing method embodiments, which are not described herein again.
On the other hand, fig. 8 is a block diagram of a debugging apparatus of an SoC chip according to an embodiment of the present invention. As shown in fig. 8, the debugging apparatus of the SoC chip includes:
a fourth sending module 801, configured to send an authentication request to the secure CPU, so that the secure CPU authenticates the main CPU;
a fourth receiving module 802, configured to receive an authentication success indication sent by the secure CPU if the secure CPU passes authentication with the main CPU;
a fifth sending module 803, configured to send a sensitive debugging command to the secure CPU, so that the secure CPU generates a sensitive debugging result, where the sensitive debugging result includes encrypted sensitive state information and the first check information;
a fifth receiving module 804, configured to receive a sensitive debugging result sent by the secure CPU;
the third obtaining module 805 is configured to obtain decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first verification information is verified.
Further, the fourth sending module 801 includes:
the authentication request sending unit is used for sending an authentication request to the secure CPU so that the secure CPU generates a first public and private key pair;
the first public key receiving unit is used for receiving a public key of a first public-private key pair sent by the security CPU;
the second public key obtaining unit is used for obtaining a public key of a second public-private key pair and first authentication information, the first authentication information is generated according to a first shared secret and a shared secret, the first shared secret is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared by the secure CPU and the outside;
and the second public key sending unit is used for sending the public key of the second public-private key pair and the first authentication information to the security CPU so that the security CPU can generate a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair, generate second authentication information according to the second shared key and the shared secret, compare the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
Further, the second public key obtaining unit includes:
a first public key sending subunit, configured to send a public key of the first public-private key pair to the authentication server, so that the authentication server performs the following operations: generating a second public-private key pair, generating a first shared key according to a private key of the second public-private key pair and a public key of the first public-private key pair, generating first authentication information according to the first shared key and a shared secret, and sending the public key of the second public-private key pair and the first authentication information to a main CPU (central processing unit), wherein the shared secret is fixed secret information shared by a security CPU (central processing unit) and an authentication server;
and the second public key receiving subunit is used for receiving the public key of the second public-private key pair and the first authentication information sent by the authentication server.
Further, the third obtaining module 805 includes:
an encrypted information sending unit, configured to send the encrypted sensitive status information and the first verification information to the authentication server, so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and the decryption information receiving unit is used for receiving the decrypted sensitive state information sent by the authentication server.
On the other hand, fig. 9 is a block diagram of a debugging apparatus of an SoC chip according to an embodiment of the present invention. As shown in fig. 9, the debugging apparatus of the SoC chip includes:
a fourth sending module 901, configured to send an authentication request to the secure CPU, so that the secure CPU authenticates the main CPU;
a fourth receiving module 902, configured to receive, if the secure CPU passes authentication of the main CPU, an authentication success indication sent by the secure CPU;
a sixth sending module 903, configured to send a general debugging command to the secure CPU, so that the secure CPU obtains non-sensitive state information;
a sixth receiving module 904, configured to receive the non-sensitive state information sent by the secure CPU;
a fifth sending module 905, configured to send a sensitive debugging command to the secure CPU, so that the secure CPU generates a sensitive debugging result, where the sensitive debugging result includes encrypted sensitive state information and first check information;
a fifth receiving module 906, configured to receive a sensitive debugging result sent by the secure CPU;
the third obtaining module 907 is configured to obtain decrypted sensitive state information, where the decrypted sensitive state information is obtained after the encrypted sensitive state information is decrypted and the first verification information is verified.
The debugging device for SoC chips provided in the embodiments of the present invention is corresponding to the foregoing method embodiments applied to the main CPU, and specific work flows and effects may refer to the foregoing method embodiments, which are not described herein again.
In another aspect, an embodiment of the present invention provides an SoC chip, where the SoC chip includes:
the safety CPU and a first memory which is in communication connection with the safety CPU;
the first memory stores instructions executable by the secure CPU, and the secure CPU implements a method for debugging the SoC chip when executing the instructions on the first memory, including, for example: receiving an authentication request sent by a main CPU; authenticating the main CPU according to the authentication request; if the authentication is passed, sending an authentication success indication to the main CPU; receiving a sensitive debugging command sent by a main CPU; acquiring sensitive state information according to the sensitive debugging command; generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information; sending the sensitive debugging result to a main CPU so that the main CPU can acquire decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first check information is verified;
the main CPU and a second memory which is in communication connection with the main CPU;
the second memory stores instructions executable by the main CPU, and the main CPU implements a debugging method of the SoC chip when executing the instructions on the second memory, including, for example: sending an authentication request to the secure CPU so that the secure CPU authenticates the main CPU; if the main CPU passes the authentication of the safety CPU, receiving an authentication success indication sent by the safety CPU; sending a sensitive debugging command to a secure CPU (central processing unit) so that the secure CPU can generate a sensitive debugging result, wherein the sensitive debugging result comprises encrypted sensitive state information and first verification information; receiving a sensitive debugging result sent by a safety CPU; and acquiring decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (19)
1. A debugging method of an SoC chip is characterized in that the method is applied to a secure CPU of the SoC chip and comprises the following steps:
receiving an authentication request sent by a main CPU;
authenticating the main CPU according to the authentication request;
if the authentication is passed, sending an authentication success indication to the main CPU;
receiving a sensitive debugging command sent by a main CPU;
acquiring sensitive state information according to the sensitive debugging command;
generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information;
and sending the sensitive debugging result to a main CPU so that the main CPU can acquire decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first check information is checked to pass.
2. The method of claim 1, wherein authenticating the host CPU according to the authentication request comprises:
generating a first public-private key pair according to the authentication request;
sending a public key of a first public-private key pair to a main CPU so that the main CPU can obtain a public key of a second public-private key pair and first authentication information, wherein the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared by a secure CPU and the outside;
receiving a public key and first authentication information of a second public-private key pair sent by a main CPU;
generating a second shared secret key according to the private key of the first public-private secret key pair and the public key of the second public-private secret key pair;
generating second authentication information from the second shared key and the shared secret;
and comparing the first authentication information with the second authentication information, if the first authentication information and the second authentication information are equal, the authentication is passed, otherwise, the authentication is not passed.
3. The method of claim 2, wherein generating a sensitive debug result according to the sensitive status information comprises:
calculating to obtain first check information according to a second shared secret key and the sensitive state information;
and encrypting the sensitive state information by using a second shared secret key to generate encrypted sensitive state information.
4. The method of claim 1, further comprising:
receiving a common debugging command sent by a main CPU;
acquiring non-sensitive state information according to the common debugging command;
and sending the non-sensitive state information to a main CPU.
5. A debugging method of an SoC chip is characterized in that the method is applied to a main CPU of the SoC chip and comprises the following steps:
sending an authentication request to the secure CPU so that the secure CPU authenticates the main CPU;
if the main CPU passes the authentication of the safety CPU, receiving an authentication success indication sent by the safety CPU;
sending a sensitive debugging command to a secure CPU (central processing unit) so that the secure CPU can generate a sensitive debugging result, wherein the sensitive debugging result comprises encrypted sensitive state information and first verification information;
receiving a sensitive debugging result sent by a safety CPU;
and acquiring decrypted sensitive state information, wherein the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
6. The method of claim 5, wherein sending an authentication request to the secure CPU for the secure CPU to authenticate the host CPU comprises:
sending an authentication request to a secure CPU so that the secure CPU generates a first public and private key pair;
receiving a public key of a first public-private key pair sent by a secure CPU;
acquiring a public key and first authentication information of a second public-private key pair, wherein the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared by a secure CPU and the outside;
and sending the public key of the second public-private key pair and the first authentication information to a security CPU (central processing unit), so that the security CPU generates a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair, generates second authentication information according to the second shared key and the shared secret, compares the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
7. The method of claim 6, wherein obtaining the public key and the first authentication information of the second public-private key pair comprises:
sending the public key of the first public-private key pair to the authentication server so that the authentication server performs the following operations: generating a second public-private key pair, generating a first shared key according to a private key of the second public-private key pair and a public key of the first public-private key pair, generating first authentication information according to the first shared key and a shared secret, and sending the public key of the second public-private key pair and the first authentication information to a main CPU (central processing unit), wherein the shared secret is fixed secret information shared by a security CPU (central processing unit) and an authentication server;
and receiving the public key and the first authentication information of the second public-private key pair sent by the authentication server.
8. The method of claim 5, wherein obtaining decrypted sensitive state information comprises:
sending the encrypted sensitive status information and the first verification information to the authentication server so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and receiving the decrypted sensitive state information sent by the authentication server.
9. The method of claim 5, further comprising:
sending a common debugging command to the secure CPU so that the secure CPU can acquire non-sensitive state information;
and receiving non-sensitive state information sent by the safety CPU.
10. A debugging device of SoC chip is characterized in that the device is applied to a secure CPU of SoC chip, and the device comprises:
the first receiving module is used for receiving an authentication request sent by the main CPU;
the authentication module is used for authenticating the main CPU according to the authentication request;
the first sending module is used for sending an authentication success indication to the main CPU if the authentication passes;
the second receiving module is used for receiving the sensitive debugging command sent by the main CPU;
the first acquisition module is used for acquiring sensitive state information according to the sensitive debugging command;
the first generation module is used for generating a sensitive debugging result according to the sensitive state information, wherein the sensitive debugging result comprises encrypted sensitive state information and first check information;
and the second sending module is used for sending the sensitive debugging result to the main CPU so that the main CPU can acquire the decrypted sensitive state information, and the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
11. The apparatus of claim 10, wherein the authentication module comprises:
a first public-private key pair generation unit, configured to generate a first public-private key pair according to the authentication request;
a first public key sending unit, configured to send a public key of a first public-private key pair to a master CPU, so that the master CPU obtains a public key of a second public-private key pair and first authentication information, where the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared between a secure CPU and an external device;
the second public key receiving unit is used for receiving a public key of a second public-private key pair and first authentication information sent by the main CPU;
the second shared key generating unit is used for generating a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair;
a second authentication information generation unit configured to generate second authentication information from the second shared key and the shared secret;
and the comparison unit is used for comparing the first authentication information with the second authentication information, if the first authentication information and the second authentication information are equal, the authentication is passed, and otherwise, the authentication is not passed.
12. The apparatus of claim 11, wherein the first generating module comprises:
the first verification information calculation unit is used for calculating to obtain first verification information according to a second shared secret key and the sensitive state information;
and the encryption unit is used for encrypting the sensitive state information by using a second shared secret key to generate encrypted sensitive state information.
13. The apparatus of claim 10, further comprising:
the third receiving module is used for receiving a common debugging command sent by the main CPU;
the second acquisition module is used for acquiring non-sensitive state information according to the common debugging command;
and the third sending module is used for sending the non-sensitive state information to the main CPU.
14. A debugging device of SoC chip is characterized in that the device is applied to a main CPU of SoC chip, and the device comprises:
the fourth sending module is used for sending an authentication request to the secure CPU so that the secure CPU can authenticate the main CPU;
the fourth receiving module is used for receiving an authentication success indication sent by the safety CPU if the safety CPU passes the authentication of the main CPU;
the fifth sending module is used for sending a sensitive debugging command to the secure CPU so that the secure CPU can generate a sensitive debugging result, and the sensitive debugging result comprises encrypted sensitive state information and first check information;
the fifth receiving module is used for receiving the sensitive debugging result sent by the safety CPU;
and the third acquisition module is used for acquiring the decrypted sensitive state information, and the decrypted sensitive state information is acquired after the encrypted sensitive state information is decrypted and the first verification information is verified.
15. The apparatus of claim 14, wherein the fourth sending module comprises:
the authentication request sending unit is used for sending an authentication request to the secure CPU so that the secure CPU generates a first public and private key pair;
the first public key receiving unit is used for receiving a public key of a first public-private key pair sent by the security CPU;
a second public key obtaining unit, configured to obtain a public key of a second public-private key pair and first authentication information, where the first authentication information is generated according to a first shared key and a shared secret, the first shared key is generated according to a private key of the second public-private key pair and a public key of the first public-private key pair, and the shared secret is fixed secret information shared between the secure CPU and the outside;
and the second public key sending unit is used for sending the public key of the second public-private key pair and the first authentication information to the security CPU so that the security CPU can generate a second shared key according to the private key of the first public-private key pair and the public key of the second public-private key pair, generate second authentication information according to the second shared key and the shared secret, compare the first authentication information with the second authentication information, if the first authentication information is equal to the second authentication information, the authentication is passed, and otherwise, the authentication is not passed.
16. The apparatus according to claim 15, wherein the second public key obtaining unit includes:
a first public key sending subunit, configured to send a public key of the first public-private key pair to the authentication server, so that the authentication server performs the following operations: generating a second public-private key pair, generating a first shared key according to a private key of the second public-private key pair and a public key of the first public-private key pair, generating first authentication information according to the first shared key and a shared secret, and sending the public key of the second public-private key pair and the first authentication information to a main CPU (central processing unit), wherein the shared secret is fixed secret information shared by a security CPU (central processing unit) and an authentication server;
and the second public key receiving subunit is used for receiving the public key of the second public-private key pair and the first authentication information sent by the authentication server.
17. The apparatus of claim 14, wherein the third obtaining module comprises:
an encrypted information sending unit, configured to send the encrypted sensitive status information and the first verification information to the authentication server, so that the authentication server performs the following operations: decrypting the encrypted sensitive state information, calculating second check information of the sensitive state information, comparing the first check information with the second check information, if the first check information and the second check information are equal, passing the check, and sending the decrypted sensitive state information to the main CPU;
and the decryption information receiving unit is used for receiving the decrypted sensitive state information sent by the authentication server.
18. The apparatus of claim 14, further comprising:
the sixth sending module is used for sending a common debugging command to the secure CPU so that the secure CPU can obtain the non-sensitive state information;
and the sixth receiving module is used for receiving the non-sensitive state information sent by the safety CPU.
19. An SoC chip, comprising:
a secure CPU;
a first memory communicatively coupled to the secure CPU;
the first memory stores instructions executable by the secure CPU which, when executing the instructions on the first memory, implements the method of any of claims 1 to 4;
a main CPU;
a second memory communicatively coupled to the main CPU;
the second memory stores instructions executable by the main CPU which, when executing the instructions on the second memory, implements the method of any of claims 5 to 9.
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