CN113296356A - Method for correcting mask pattern - Google Patents
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- CN113296356A CN113296356A CN202010111822.2A CN202010111822A CN113296356A CN 113296356 A CN113296356 A CN 113296356A CN 202010111822 A CN202010111822 A CN 202010111822A CN 113296356 A CN113296356 A CN 113296356A
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- 238000000034 method Methods 0.000 title claims abstract description 52
- 230000007547 defect Effects 0.000 claims abstract description 188
- 239000000758 substrate Substances 0.000 claims abstract description 102
- 238000005457 optimization Methods 0.000 claims description 5
- 238000001900 extreme ultraviolet lithography Methods 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000010521 absorption reaction Methods 0.000 description 4
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- 238000003475 lamination Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000011478 gradient descent method Methods 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 239000011358 absorbing material Substances 0.000 description 1
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- 239000006117 anti-reflective coating Substances 0.000 description 1
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/72—Repair or correction of mask defects
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/76—Patterning of masks by imaging
Abstract
The application discloses a method for correcting a mask pattern, which comprises the following steps: providing original masks, wherein the original masks comprise a substrate and a pattern structure above the substrate, the pattern structure defines original mask patterns, and the original mask patterns comprise sub-patterns; projecting all substrate defects onto an auxiliary plane to form defect projections; defining a scribing groove area on the auxiliary plane based on the position of the defect projection, wherein the scribing groove area divides the auxiliary plane into chip areas corresponding to the sub-graphs, and the number of the defect projections in the scribing groove area is greater than that in the chip areas; projecting the sub-patterns of the original mask pattern to the corresponding chip regions to form sub-pattern projections corresponding to the chip regions on the auxiliary plane; and respectively adjusting the position of the sub-graph corresponding to each sub-graph projection in the corresponding original mask pattern based on the position of the sub-graph projection on the auxiliary plane. The method disclosed herein reduces the impact of substrate defects on the EUV lithography process.
Description
Technical Field
The present disclosure relates to the field of semiconductor manufacturing, and more particularly, to a method for correcting a mask pattern.
Background
As the resolution of lithography reaches below 10nm, Extreme Ultraviolet (EUV) lithography process is introduced, so that moore's law is continued. The EUV wavelength is about 13.5nm, which conventional lenses cannot deflect. Therefore, in the EUV lithography process, the optical path is generally formed in a reflective manner.
As an important part of the EUV lithography process, the substrate of the EUV mask is inevitably defective at the manufacturing stage. For example, an uneven substrate can cause the reflection of EUV light to deviate from the original propagation path, thereby causing mask pattern deviations when transferred to a wafer.
Therefore, a new method is needed to correct the mask pattern to reduce the impact of defects in the substrate on the EUV lithography process.
Disclosure of Invention
The following presents a simplified summary of the application in order to provide a basic understanding of some aspects of the application. It should be understood that this section is not intended to identify key or critical elements of the application, nor is it intended to be limiting as to the scope of the application. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.
In view of the above-mentioned shortcomings of the prior art, the present application provides a method of modifying a mask pattern to reduce the impact of defects in a substrate on an EUV lithography process.
The application provides a method for correcting a mask pattern, which comprises the following steps: providing one or more original masks, each original mask comprising a substrate and a pattern structure located over the substrate, the pattern structure having an original mask pattern, each original mask pattern comprising one or more sub-patterns, at least one substrate having a substrate defect; projecting all substrate defects onto an auxiliary plane to form one or more defect projections; defining a scribe line area on the secondary plane based on the location of the one or more defect projections, the scribe line area dividing the secondary plane into one or more chip areas corresponding to the one or more sub-patterns, the number of defect projections within the scribe line area being greater than the number of defect projections within the one or more chip areas; projecting all sub-patterns of the original mask pattern to the corresponding chip regions to form one or more sub-pattern projections corresponding to the one or more chip regions on the auxiliary plane; and respectively adjusting the position of one or more sub-graphics corresponding to each sub-graphic projection in the corresponding original mask pattern based on the position of the one or more sub-graphic projections on the auxiliary plane.
Optionally, the method further comprises: after forming one or more sub-pattern projections corresponding to the one or more chip regions, adjusting positions of the one or more sub-pattern projections on the auxiliary plane based on a positional relationship of the one or more sub-pattern projections and the one or more defect projections to reduce a number of defect projections overlapping the one or more sub-pattern projections.
Optionally, adjusting the position of the one or more sub-graphic projections on the auxiliary plane based on the positional relationship of the one or more sub-graphic projections and the one or more defect projections to reduce the number of defect projections overlapping the one or more sub-graphic projections comprises: establishing a defect influence degree function of each chip area based on the position relation between the sub-graph projection and the defect projection in each chip area; obtaining a new position of the sprite projected on the auxiliary plane using the defect affecting volume function; and displacing the sub-graphic projection to the new position.
Optionally, the establishing a defect influence degree function of each chip region based on the position relationship between the sub-pattern projection and the defect projection in each chip region includes: dividing each chip area into a plurality of coordinate grids; respectively determining the position association degree of each coordinate grid and the projection of the sub-graph; respectively determining the position association degree of each coordinate grid and the defect projection; determining the defect influence degree of each coordinate lattice based on the position association degree of each coordinate lattice with the sub-graph projection and the position association degree of each coordinate lattice with the defect projection; and generating a defect influence function of each chip region according to the defect influence degree of each coordinate grid.
Optionally, obtaining a new position of the sprite projection on the auxiliary plane using the defect affecting volume function comprises: obtaining a solution corresponding to the minimum value of the defect influence volume function through an optimization method; and generating a new position of the sprite projection on the auxiliary plane based on the solution.
Optionally, each coordinate lattice is a rectangle, a long side of the rectangle is 1nm to 5nm, and a short side of the rectangle is 1nm to 5 nm.
Optionally, the method further comprises: generating a corresponding new mask pattern based on the adjusted sub-pattern; and generating a new pattern structure on the corresponding substrate based on the new mask pattern to obtain a new mask.
Optionally, the width of the scribe line region is 60 μm to 70 μm.
Optionally, a projection of the defect in the scribe line region is more than 5 μm from any of the one or more chip regions.
Optionally, the one or more chip regions are all rectangular.
Optionally, the number of defect projections within the one or more chip regions is less than the number of defects in all substrates that are not covered by the pattern structure.
The technical scheme of this application has following beneficial effect:
first, by projecting all defects to the auxiliary plane and redefining the positions of the scribe line regions and the chip regions on the auxiliary plane, for example, by scribing regions with high defect density into the scribe line regions while leaving only regions with low defect density or no defects to the chip regions, it is possible to preliminarily filter most of the defects and significantly reduce the number of defects in the chip regions, thereby reducing the influence on the mask pattern corresponding to the chip regions.
Secondly, the defect projection in the scribing groove area is limited within a certain distance from the chip area, and the sub-graph projection can be allowed to translate within a certain range in the chip area, so that the number of the defect projections overlapped with the sub-graph projection is reduced, and the influence of the defect on the mask pattern corresponding to the sub-graph projection is avoided.
And thirdly, by establishing a defect influence function and finding out a solution corresponding to the minimum value by adopting a gradient descent method, the position with the least defect number overlapped with the projection of the sub-graph can be quickly and efficiently found out.
In summary, according to the technical scheme of the application, the influence of the defect in the substrate on the EUV lithography process is reduced by correcting the mask pattern in position.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals represent similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application.
FIG. 1 is a schematic diagram of the structure of an EUV mask without substrate defects;
FIG. 2 is a schematic diagram of the structure of an EUV mask with substrate defects;
FIG. 3 is a schematic plan view of an EUV mask with substrate defects;
FIG. 4A is a schematic plan view of an EUV mask showing the positional relationship of the mask pattern and substrate defects before correction;
FIG. 4B is a schematic plan view of an EUV mask showing the positional relationship of the corrected mask pattern and a substrate defect;
FIG. 5 is a schematic structural diagram of an EUV mask showing the positional relationship between the corrected mask pattern and a substrate defect;
FIG. 6 is a flow chart of a method of correcting a mask pattern according to an embodiment of the present application;
FIG. 7A is a schematic plan view of a first original mask showing the positional relationship of the original mask pattern, the chip region and the substrate defect in the first original mask before correction according to an embodiment of the present application;
FIG. 7B is a schematic plan view of a second original mask showing the positional relationship of the original mask pattern, the chip region and the substrate defect in the second original mask before correction according to an embodiment of the present application;
FIG. 7C is a schematic plan view of the original mask patterns and defects of the first and second original masks after being co-projected onto a reference plane, in accordance with an embodiment of the present application;
FIG. 7D is a schematic perspective view of the first original mask and the second original mask after the defects are co-projected onto the auxiliary plane according to an embodiment of the present application;
FIG. 8A is a schematic plan view of a defect in a substrate of a first original mask and a second original mask after being co-projected onto an auxiliary plane according to an embodiment of the present application;
FIG. 8B is a schematic plan view of an EUV mask showing the positional relationship of the corrected chip region and substrate defects according to an embodiment of the present application;
FIG. 9 is a schematic plan view of an EUV mask showing the positional relationship of the corrected mask pattern, chip region and substrate defects according to an embodiment of the present application;
FIG. 10 is a flow chart of a process of adjusting a sprite projection according to an embodiment of the present application;
FIG. 11 is a flow chart of a process of establishing a defect affecting volume function according to an embodiment of the present application;
FIG. 12A is a schematic plan view of a grid and defect projection according to an embodiment of the present application;
FIG. 12B is a schematic plan view of a grid of coordinates and a projection of a sprite according to an embodiment of the present application;
FIG. 13 is a flow chart of a process for obtaining a new position using a defect influence magnitude function according to an embodiment of the present application;
FIG. 14A is a schematic plan view of a projection of a sprite before adjustment according to an embodiment of the present application;
FIG. 14B is a schematic plan view of an adjusted sprite projection according to an embodiment of the present application;
FIG. 15A is a schematic plan view of all the sub-pattern projections corresponding to the adjusted first original mask pattern and all the sub-pattern projections corresponding to the second original mask pattern according to an embodiment of the present disclosure;
FIG. 15B is a schematic plan view of the mask pattern of the adjusted first original mask according to an embodiment of the present application;
fig. 15C is a schematic plan view of the mask pattern of the adjusted second original mask according to the embodiment of the present application.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
FIG. 1 is a schematic view of the structure of an EUV mask without substrate defects. As shown in fig. 1, the EUV mask includes: the light-reflecting film comprises a substrate 1 and a pattern structure 2 positioned above the substrate 1, wherein the substrate 1 comprises a lamination layer 3 and a protective layer 2, the lamination layer 3 and the protective layer 2 positioned above the lamination layer 3 are both made of light-reflecting materials, and the pattern structure 2 comprises an absorption layer 3 and an anti-reflection coating 4 positioned above the absorption layer 3. The absorption layer 3 is made of a light absorbing material for absorbing EUV light to prevent reflection thereof. The anti-reflection coating 4 is made of an anti-reflection material for preventing reflection of EUV light. The pattern structure 2 has a mask pattern, and more specifically, the opening portions of the absorption layer 3 and the anti-reflection coating 4 define the mask pattern.
FIG. 2 is a schematic diagram of an EUV mask with substrate defects, as shown in FIG. 2, substrate defects 5 (e.g., bumps) in the substrate 1 cause diffraction of the EUV light, thereby deviating from the original propagation path, which causes deviations in the mask pattern when transferred to a wafer. The substrate 1 of the EUV mask may have surface irregularities during the manufacturing process. If the substrate defect happens to be located in the open area of the pattern structure 2, as shown in fig. 2, it will result in unexpected diffraction of light, undesirably altering the pattern on the wafer.
FIG. 3 is a schematic plan view of an EUV mask with substrate defects. As shown in fig. 3, five substrate defects 5 are present in the substrate 1.
Fig. 4A is a schematic plan view of the EUV mask, showing the positional relationship of the mask pattern 12 and the substrate defect 5 before correction. As shown in fig. 4, among the five substrate defects 5 of the substrate 1, three substrate defects 5 overlap the mask pattern 12, which means that when EUV light is incident on the EUV mask, unwanted diffraction occurs at three positions, resulting in distortion of the mask pattern 12 during transfer to the wafer, degrading the quality of the finished product.
Fig. 4B is a schematic plan view of the EUV mask, showing the positional relationship of the corrected mask pattern 12 and the substrate defect 5. As shown in fig. 5, by translating the mask pattern 12a certain distance downwards, it is avoided to overlap the substrate defect 5, thereby avoiding the influence of the substrate defect 5 in the substrate 1 on the EUV lithography process.
FIG. 5 is a schematic structural diagram of an EUV mask, showing the positional relationship between the corrected mask pattern and a substrate defect. As shown in fig. 5, the translation of the mask pattern is such that the substrate defects 5 in the substrate 1 are not located within the openings of the pattern structure 2, but are transferred underneath the pattern structure 2. In other words, the region of the mask that is intended to reflect EUV light is now free of any defects, so that the influence of substrate defects 5 in the substrate 1 on the EUV lithography process is avoided.
The above introduces a current solution to the defects of EUV masks, i.e. changing the position of the mask pattern (defined by the absorber layer and the antireflective coating) such that the substrate defects are located below the absorber layer to avoid that incident EUV light is affected by the substrate defects. When the defect density is not high, this method can obtain good effects. However, if the local density of substrate defects is high, the above method may not hide all substrate defects under the absorber layer. In addition, for the whole manufacturing process, a plurality of EUV masks may be used, and if the substrate defects of one EUV mask cannot be hidden well, the photoetching of other subsequent EUV masks is also influenced.
In order to solve the above technical problem, an embodiment of the present invention provides a method for correcting a mask pattern, which includes the following steps with reference to fig. 6:
step S100: providing one or more original masks, each original mask comprising a substrate and a pattern structure located over the substrate, the pattern structure having an original mask pattern, each original mask pattern comprising one or more sub-patterns, at least one substrate having a substrate defect;
step S200: projecting all substrate defects onto an auxiliary plane to form one or more defect projections;
step S300: defining a scribe line area on the secondary plane based on the location of the one or more defect projections, the scribe line area dividing the secondary plane into one or more chip areas corresponding to the one or more sub-patterns, the number of defect projections within the scribe line area being greater than the number of defect projections within the one or more chip areas;
step S400: projecting all sub-patterns of the original mask pattern to the corresponding chip regions to form one or more sub-pattern projections corresponding to the one or more chip regions on the auxiliary plane;
step S500: and respectively adjusting the position of one or more sub-graphs corresponding to each sub-graph projection in the corresponding original mask pattern based on the position of the one or more sub-graph projections on the auxiliary plane.
The above steps will be described in detail with reference to fig. 7 to 15C.
As shown in fig. 7A and 7B, one or more original masks are provided.
In some embodiments, the original mask may include only one mask, or may include three or more masks, each of which may include a substrate and a pattern structure over the substrate, the pattern structure may have an original mask pattern, each of which may include one or more sub-patterns, each of which may be divided into one or more chip regions, and the one or more sub-patterns may be located in the corresponding chip region. In the present embodiment, all substrates have substrate defects. In some embodiments, at least one substrate has substrate defects.
In the present embodiment, the one or more original masks may include a first original mask 21 and a second original mask 22. The first original mask 21 includes a first substrate 211 and a pattern structure (not shown) over the first substrate 211, the pattern structure defining first original mask patterns 217, each of the first original mask patterns 217 including one or more first sub-patterns, the first original mask 21 may be divided into one or more first original chip regions 216, and the one or more first sub-patterns may be respectively located in the corresponding first original chip regions 216. As can be seen in fig. 8A, there are four substrate defects 215 on the first substrate 211, and the four substrate defects 215 are all overlapped with the original mask pattern 217. Similarly, the second original mask 22 includes a second substrate 221 and a pattern structure (not shown) located above the second substrate 221, the pattern structure defining second original mask patterns 228, each of the second original mask patterns 228 including one or more second sub-patterns, the second original mask 22 may be divided into one or more second original chip regions 226, and the one or more second sub-patterns may be respectively located in the corresponding second original chip regions 226. As can be seen in fig. 8B, there are four substrate defects 225 on the second substrate 221, three of the four substrate defects 225 overlapping the original mask pattern 228.
Fig. 7C is a schematic plan view of the original mask patterns and defects of the first original mask 21 and the second original mask 22 after being projected onto a reference plane according to an embodiment of the present application. As can be seen in fig. 7C, a portion of the defect overlaps even both the original mask pattern 217 and the original mask pattern 228. That is, these defects not only affect the process of transferring the corresponding mask pattern to the wafer, but also affect the process of transferring the subsequent mask pattern to the wafer. Therefore, it is necessary to correct all affected mask patterns to reduce the number of defects that overlap these mask patterns.
As shown in fig. 7C, both the substrate defects of the first substrate 211 and the substrate defects of the second substrate 221 are projected onto the auxiliary plane 231 to form one or more defect projections 235. The auxiliary plane 231 may be a virtual plane. In the present application, the planes of the first substrate 211 and the second substrate 221 are aligned and parallel to the auxiliary plane 231, respectively, when performing projection. In the present application, the size of the auxiliary plane 231 is the same as that of the first substrate 211 and the second substrate 221. In the present embodiment, among all five raw chip regions 236, there are four raw chip regions 236 in which the defect projection 235 exists, and only one raw chip region 236 does not have the defect projection 235. This means that the mask pattern or its sub-pattern corresponding to the original chip area 236 where the defect projection 235 exists may be affected by the defect. Therefore, it is necessary to redefine the location of the chip area to avoid the defect projection 235. The size of the auxiliary plane 231 may be the same as that of the original mask.
As shown in fig. 8A and 8B, a scribe-lane region 239 is defined on the auxiliary plane 231 based on the location of the one or more defect projections 235, the scribe-lane region 239 separating the auxiliary plane 231 into one or more chip regions 237 corresponding to one or more sub-patterns of the original mask pattern, wherein the number of defect projections 235 within the scribe-lane region 239 is greater than the number of defect projections 235 within the one or more chip regions 237-in other embodiments, the location of the scribe-lane region 239 may be selected according to the actual needs of the chip region layout.
In the present embodiment, only one chip region 237 of all five chip regions 237 has the defect projection 235, and the other four chip regions 237 do not have the defect projection 235. This means that after redefining the scribe line region 239, the number of chip regions affected by the defect projection 235 is greatly reduced, thereby reducing the effect on the mask pattern or its sub-patterns corresponding to the chip regions and improving the quality of the photolithography process.
In some embodiments, the number of defect projections 235 within one or more chip regions 237 may be less than the number of defects in all substrates that are not covered by the pattern structure. In some embodiments, there is no defect projection within at least one of the one or more chip regions 237. In some embodiments, there are no defect projections within at least two of the one or more chip regions 237. In some embodiments, there is a defect projection in only one chip region 237. In some embodiments, the number of defect projections 235 within one or more chip regions 237 is less than 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, 15%, 20%, 30%, 40%, or 50% of the number of defect projections 235 within the scribe lane region 239.
In this embodiment, one or more of the chip regions 237 are rectangular. In some embodiments, one or more of the chip regions 237 may be in the shape of a circle, an ellipse, a trapezoid, a diamond, a pentagon, a hexagon, etc., or may be in other irregular shapes.
As shown in fig. 9, both the sub-pattern of the first original mask pattern 217 and the sub-pattern of the second original mask pattern 228 are projected onto the respective corresponding chip regions 237 to form one or more sub-pattern projections 233 corresponding to the one or more chip regions 237 on the auxiliary plane 231.
As can be seen in fig. 9, the scribe line region 239 covers most of the defect projection 235, and only one defect projection 235 is still present in the chip region 237 at the upper right corner of fig. 9. The substrate defects corresponding to the defect projection 235 covered by the scribe line region 239 will no longer affect the photolithography process and will be removed by the tape-out process in the subsequent dicing process.
In the present embodiment, the width w1 of the scribe line region 239 may be 60 microns to 70 μm, and the distance between the defect projection 235 in the scribe line region 239 and any of the one or more chip regions 237 may be greater than 5 μm. The scribe line region 239 may have a central region, and the width w2 of the central region may be 40 μm to 50 μm. This arrangement may provide sufficient space for movement of the subpattern projection 233 within the chip area 237 such that the subpattern projection 233 can be translated to avoid the defect projection 235 because the size of the defect projection 235 is typically 20 nm.
In the present embodiment, after forming the one or more sub pattern projections 233 corresponding to the one or more chip regions 237, the position of the one or more sub pattern projections 233 on the auxiliary plane 231 may be adjusted based on the positional relationship of the one or more sub pattern projections 233 and the one or more defect projections 235 to reduce the number of defect projections 235 overlapping the one or more sub pattern projections 233.
As shown in fig. 10, the step S500 may include:
step S510: establishing a defect influence volume function F of each chip region 237 based on the position relationship between the subpattern projection 233 and the defect projection 235 in each chip region 237;
step S520: obtaining a new position of the sprite projection 233 on the auxiliary plane 231 using the defect affecting volume function F;
step S530: the sub-pattern projection 233 is shifted to the new position.
As shown in fig. 11, 12A and 12B, the step S510 may include:
step S511: dividing each chip region 237 into a plurality of coordinate lattices 10;
step S512: separately determining the position association P of each coordinate grid 10 with the sub-graphic projection 233k(xi，yj)；
Step S513: determining the position association degree D of each coordinate grid 10 and the defect projection 235 respectivelyk(xi，yj)；
Step S514: based on the position association degree P of each coordinate grid 10 and the sub-graph projection 233k(xi，yj) And the degree of positional association D of each coordinate grid 10 with the defect projection 235k(xi，yj) Determining the defect influence f (x) of each coordinate grid 10i，yj)；
Step S515: the defect influence degree f (x) according to each coordinate grid 10i，yj) Generation of defect influence degree of each chip region 237Function F.
In some embodiments, the order of step S512 and step S513 may be reversed.
As shown in fig. 13, the step S520 may include:
step S521: obtaining a solution corresponding to the minimum value of the defect influence degree function F by a gradient optimization method; and
step S522: a new position of the sub-graphic projection 233 on the auxiliary plane 231 is generated based on the solution.
The process from dividing the coordinate grid 10 to solving the defect influence volume function F will be described in detail below with reference to fig. 14A and 14B.
First, each chip region 237 is divided into a plurality of coordinate frames 10, and the coordinate of each coordinate frame 10 is (x)i，yj) Wherein i is a horizontal axis coordinate, j is a vertical axis coordinate, and i and j are positive integers greater than or equal to 1. For example, the coordinates (x)1，y2) Corresponding to the grid 10 located on the first column and the second row. In the present embodiment, each coordinate grid 10 is a rectangle, the long side of the rectangle is 1nm to 5nm, and the short side of the rectangle is 1nm to 5 nm.
Next, the position association degree P of each coordinate grid 10 with the sub-graphic projection 233 is determined separatelyk(xi，yj) Wherein k is the sequence number of the original mask pattern to which the sub-pattern corresponding to the sub-pattern projection 233 belongs, and k is a positive integer greater than or equal to 1. For example, P2(x1，y2) Indicating the degree of positional association of the grid of coordinates 10 located on the first column and the second row with the corresponding sprite projection 233 of the second original mask pattern in the chip area 237. Specifically, the position association degree Pk(xi，yj) The values of (c) follow the following rules: if the coordinate (x)i，yj) There is a sub-pattern projection of the corresponding sub-pattern from the k-th original mask pattern in the corresponding coordinate grid 10, then Pk(xi，yj) Has a value of 1; otherwise, Pk(xi，yj) The value of (d) is 0.
Next, the position association degree D of each coordinate grid 10 and the defect projection 235 is determined respectivelyk(xi，yj) Where k is the serial number of the original mask to which the defect corresponding to the defect projection 235 belongs. For example, D2(x1，y2) Indicating the degree of positional relationship between the coordinate grid 10 located on the first column and the second row and the defect projection 235 of the second original mask in the chip area 237. Specifically, the degree of position association Dk(xi，yj) The values of (c) follow the following rules: if the coordinate (x)i，yj) The defect projection of the corresponding defect of the k-th original mask exists in the corresponding coordinate grid 10, then Dk(xi，yj) Has a value of G ((x-x)i)/si，(y-yj)/sj) (ii) a Otherwise, Dk(xi，yj) Has a value of 0, wherein G ((x-x)i)/si，(y-yj)/sj) Is represented by a coordinate point (x)i，yj) A two-dimensional gaussian function centered; siAnd sjIs standard deviation and is used to represent half wave width; siAnd sjThe value of (b) may be set to 5nm to 20 nm. Specifically, the two-dimensional gaussian function can be referred to the following equation:
where μ is the mathematical expectation and σ2Is the variance.
Next, the degree of positional association P of each coordinate grid 10 with the sub-graphic projection 233 is based onk(xi，yj) And the degree of positional association D of each coordinate grid 10 with the defect projection 235k(xi，yj) Determining the defect influence f (x) of each coordinate grid 10i，yj). Specifically, f (x)i，yj)＝∑kPk(xi，yj)×Dk(xi，yj)。
Next, the defect influence degree f (x) according to each coordinate lattice 10i，yj) A defect affecting volume function F for each chip region 237 is generated. Specifically, F ═ Σi，jf(xi，yj)。
Next, a solution corresponding to the minimum value of the defect influence degree function F is obtained by a gradient optimization method. The smaller the value of the defect influence function F is, the smaller the relevance between the defect projection and the sub-graph projection in the current coordinate is. When the value of the defect influence degree function F reaches a smaller value, the correlation degree between the defect projection and the sprite projection in the current coordinate is minimum, which means that there will be no overlap between the two. The gradient optimizing method is that the searching is carried out along the gradient direction with the minimum change rate of a certain point function to obtain the minimum point in the direction, then the searching is carried out along the new gradient direction from the point, and the searching is carried out along the new gradient direction until a certain precision requirement is met to reach an extreme point or an optimal point. In this embodiment, the gradient optimization method may be a minimum gradient descent method. Gradient descent, also known as steepest descent, refers to iterative search to a distance point of a specified step size corresponding to a gradient (or approximate gradient) opposite to the current point on the function to find a local minimum of the function.
Next, a new position of the sub-graphic projection 233 on the auxiliary plane 231 is generated based on the solution.
Next, the sub-pattern projection 233 is shifted from the position shown in fig. 14A to the new position shown in fig. 14B. The movement can be performed in four directions, up, down, left, and right. In some embodiments, the displacement amount of the GDS document, which corresponds to the adjustment amount of the sprite projection 233, may be obtained by minimizing the value of the defect influence function F. As shown in fig. 14A and 14B, the frame 11 corresponds to the boundary of the central region of the scribe line region 239, and since there may be other defect projections in the central region of the scribe line region 239, the sub-pattern projection 233 will not overlap with other defect projections as long as it does not move out of the frame 11. In the present embodiment, the distance w3 between the boundary of the chip region 237 in each direction and the bezel 11 is about 5 μm, which means that the adjustment range of the sub-pattern projection 233 is at least 5 μm. This arrangement may provide sufficient adjustment space for the subpattern projection 233 within the chip area 237 because the size of the defect projection 235 is typically 20 nm.
In the present embodiment, since the defect projection 235 exists only in the chip region 237 located at the upper right corner, the sub-pattern projection 233 located in the chip region 237 located at the upper right corner is adjusted. In other embodiments, the position of the sub-pattern projection in all of the chip regions 237 where the defective projection 235 exists may be adjusted, or the position of the sub-pattern projection in some of the chip regions 237 where the defective projection 235 exists may be adjusted.
Fig. 15A is a schematic plan view showing all the sub-pattern projections corresponding to the adjusted first original mask pattern and all the sub-pattern projections corresponding to the second original mask pattern. As shown in fig. 15A, the position of one or more sub-patterns corresponding to each sub-pattern projection 233 in the corresponding original mask pattern is adjusted based on the position of the one or more sub-pattern projections 233 on the auxiliary plane 231.
As shown in fig. 15B, a corresponding new first mask pattern 37 is generated based on the sub-pattern of the adjusted sub-pattern mask 233. The new first mask pattern 37 does not overlap any defect 215 in the first substrate 211.
As shown in fig. 15C, a corresponding new second mask pattern 38 is generated based on the sub-pattern of the adjusted sub-pattern mask 233. The new second mask pattern 38 does not overlap any defect 225 in the second substrate 221.
Next, a new pattern structure (not shown) is generated on the first substrate 211 based on the new first mask pattern 37 to obtain a new first mask, and a new pattern structure (not shown) is generated on the second substrate 221 based on the new second mask pattern 38 to obtain a new second mask. Since the defects 5 in the first substrate 211 and the second substrate 221 do not overlap any mask pattern (i.e., are hidden under the pattern structure), the EUV light is not caused to undergo a diffraction phenomenon, thereby eliminating the adverse effect of the defects 5 on the EUV lithography process and improving the lithography precision.
In view of the above, it will be apparent to those skilled in the art upon reading the present application that the foregoing application content may be presented by way of example only, and may not be limiting. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, modifications, and variations are intended to be within the spirit and scope of the exemplary embodiments of this application.
It is to be understood that the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" or "including," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference characters denote the same elements throughout the specification.
Further, the present specification describes example embodiments with reference to idealized example cross-sectional and/or plan and/or perspective views. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.
Claims (11)
1. A method of modifying a mask pattern, comprising:
providing one or more original masks, each original mask comprising a substrate and a pattern structure located over the substrate, the pattern structure having an original mask pattern, each original mask pattern comprising one or more sub-patterns, at least one substrate having a substrate defect;
projecting all substrate defects onto an auxiliary plane to form one or more defect projections;
defining a scribe line area on the secondary plane based on the location of the one or more defect projections, the scribe line area dividing the secondary plane into one or more chip areas corresponding to the one or more sub-patterns, the number of defect projections within the scribe line area being greater than the number of defect projections within the one or more chip areas;
projecting all sub-patterns of the original mask pattern to the corresponding chip regions to form one or more sub-pattern projections corresponding to the one or more chip regions on the auxiliary plane; and
and respectively adjusting the position of one or more sub-graphs corresponding to each sub-graph projection in the corresponding original mask pattern based on the position of the one or more sub-graph projections on the auxiliary plane.
2. The method of claim 1, further comprising:
after forming one or more sub-pattern projections corresponding to the one or more chip regions, adjusting positions of the one or more sub-pattern projections on the auxiliary plane based on a positional relationship of the one or more sub-pattern projections and the one or more defect projections to reduce a number of defect projections overlapping the one or more sub-pattern projections.
3. The method of claim 2, wherein adjusting the position of the one or more sub-graphic projections on the secondary plane based on the positional relationship of the one or more sub-graphic projections to the one or more defect projections to reduce the number of defect projections that overlap the one or more sub-graphic projections comprises:
establishing a defect influence degree function of each chip area based on the position relation between the sub-graph projection and the defect projection in each chip area;
obtaining a new position of the sprite projected on the auxiliary plane using the defect affecting volume function; and
and displacing the sub-graph projection to the new position.
4. The method of claim 3, wherein establishing the defect impact function for each chip region based on the positional relationship between the sub-pattern projection and the defect projection within the each chip region comprises:
dividing each chip area into a plurality of coordinate grids;
respectively determining the position association degree of each coordinate grid and the projection of the sub-graph;
respectively determining the position association degree of each coordinate grid and the defect projection;
determining the defect influence degree of each coordinate lattice based on the position association degree of each coordinate lattice with the sub-graph projection and the position association degree of each coordinate lattice with the defect projection; and
and generating a defect influence function of each chip region according to the defect influence degree of each coordinate grid.
5. The method of claim 3, wherein obtaining a new position of the sprite projection on the auxiliary plane using the defect affecting volume function comprises:
obtaining a solution corresponding to the minimum value of the defect influence volume function through a gradient optimization method; and
generating a new location of the sprite projection on the auxiliary plane based on the solution.
6. The method of claim 4, wherein each grid is a rectangle having a long side of 1nm to 5nm and a short side of 1nm to 5 nm.
7. The method of claim 1, further comprising:
generating a corresponding new mask pattern based on the adjusted sub-pattern; and
and generating a new pattern structure on the corresponding substrate based on the new mask pattern to obtain a new mask.
8. The method of claim 1, wherein the width of the scribe lane region is 60 μ ι η to 70 μ ι η.
9. The method of claim 1, wherein a projection of the defect in the scribe-lane region is greater than 5 μm from any of the one or more chip regions.
10. The method of claim 1, wherein the one or more chip regions are each rectangular.
11. The method of claim 1, wherein the number of defect projections within the one or more chip regions is less than the number of defects in all substrates that are not covered by the pattern structure.
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