CN113296325B

CN113296325B - Display panel and display device

Info

Publication number: CN113296325B
Application number: CN202110587331.XA
Authority: CN
Inventors: 张晨阳; 李付强; 张振宇
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2023-05-12
Anticipated expiration: 2041-05-27
Also published as: CN113296325A

Abstract

The embodiment of the application provides a display panel and a display device. The display panel includes: at least one display area; the display area is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of grid signal line groups; in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and are used for outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines at the same time, so that each data signal continuously outputs design time, M is more than or equal to 2, and M is an integer. According to the embodiment of the application, the time for outputting the data signals by each data signal line can be improved, so that each data signal continuously outputs the design time, and the display of the stereoscopic image visible to naked eyes is realized.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display panels, in particular to a display panel and a display device.

Background

The refresh rate of the display panel is between 50Hz (hertz) and 60Hz (hertz), and after the refresh rate is higher than 60Hz, the human eyes cannot distinguish the continuously refreshed pictures, because the human eyes have the phenomenon of persistence of vision, and when the refresh rate of the screen is high enough, the phenomenon of persistence of pictures can be formed in the brain.

At present, the effect of stereoscopic display presented due to persistence of vision described in the application background is achieved, and the refresh rate relative to the display of a two-dimensional image is greatly increased, so that the time for which a data signal is charged into a pixel circuit is shortened, and the display of a stereoscopic image visible to naked eyes cannot be achieved.

Disclosure of Invention

The application provides a display panel and a display device aiming at the defects of the prior art, which are used for solving the technical problems that the time for filling a pixel circuit with a data signal of the display panel is short and the display of a stereoscopic image visible by naked eyes cannot be realized in the prior art.

In a first aspect, embodiments of the present application provide a display panel, including: at least one display area;

the display area is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of grid signal line groups;

in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and are used for outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines at the same time, so that each data signal continuously outputs design time, M is more than or equal to 2, and M is an integer.

In one possible implementation, the data signal lines are disposed in at least one metal layer;

the metal layer is provided with an opening for electrically connecting the data signal line with the data signal output unit.

In one possible implementation manner, the openings corresponding to the M data signal lines are arranged in a staggered manner in the M data signal lines corresponding to the M gate signal lines.

In one possible implementation, the at least one metal layer includes a first metal layer and a second metal layer;

the data signal lines in the first metal layer and the second metal layer are arranged at intervals.

In one possible implementation, the first metal layer is provided with a plurality of first openings;

the second metal layer is provided with a plurality of second openings;

the plurality of first openings are electrically connected with at least one data signal output unit through first metal wires;

the plurality of second openings are electrically connected with at least one data signal output unit through second metal wires.

In one possible implementation manner, the data signal line correspondingly connected to the pixel circuits in the same row in each display area is electrically connected to at least one data signal output unit; or alternatively, the process may be performed,

the data signal lines of each display area correspondingly connected with the pixel circuits in the same row are electrically connected with one data signal output unit through a multiplexer.

In one possible implementation, M gate signal lines are electrically connected to one gate signal output unit in the display region.

In one possible implementation, in the display area, M gate signal lines are electrically connected to one signal output terminal in the GOA circuit.

In one possible implementation, the display panel includes multiple sets of GOA circuits;

and each group of GOA circuits are electrically connected with the pixel circuits through the data signal lines correspondingly and electrically connected with one data signal output unit.

In a second aspect, embodiments of the present application provide a display device, including: the display panel of the first aspect.

The beneficial technical effects that technical scheme that this application embodiment provided brought include:

in the display area of the display panel of the embodiment of the application, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines electrically connected, the data signal line group comprises M data signal lines correspondingly arranged with the M grid signal lines, when the M grid signal lines output grid signals to the M pixel circuits simultaneously, the M data signal lines output data signals to the M pixel circuits simultaneously, so that the time for outputting the data signals by each data signal line is prolonged, the design time is continuously output by each data signal, and the display of the stereoscopic image visible by naked eyes is realized.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic structural diagram of a display area of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an arrangement of gate signal lines and data signal lines of a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an arrangement of gate signal lines and data signal lines of another display panel according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display panel according to an embodiment of the present application.

Reference numerals:

a 100-display area, 110-pixel circuits, 120-gate signal lines, 130-data signal lines;

131-first data signal line, 132-second data signal line, 133-third data signal line, 134-fourth data signal line;

140-openings, 141-first openings, 142-second openings;

150-a gate signal output unit;

160-GOA circuit, 161-GOA unit.

Detailed Description

Examples of embodiments of the present application are illustrated in the accompanying drawings, in which like or similar reference numerals refer to like or similar elements or elements having like or similar functionality throughout. Further, if detailed description of the known technology is not necessary for the illustrated features of the present application, it will be omitted. The embodiments described below by referring to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application.

It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

The inventor of the application researches and discovers that after the refresh rate of a general display panel is between 50Hz and 60Hz and the refresh rate is higher than 60Hz, human eyes cannot distinguish continuously refreshed pictures, because the human eyes have the phenomenon of persistence of vision, and when the refresh rate of a screen is high enough, the phenomenon of persistence of pictures can be formed in the brain. Our real world is a three-dimensional world, and the most common way to express three-dimensional effects is to use a two-dimensional screen to display a rotated 2D image, which can be expressed as follows:

3D effect = 2D image + rotation transform

I.e. dynamic volume scanning techniques, whose imaging space is constituted by means of a periodic movement of the display device.

The stereoscopic image is divided into a plurality of layers along the section, each image after the stereoscopic image segmentation is played on the display screen, when the screen refresh rate is high enough, the viewer can simultaneously watch the images of a plurality of depth planes by utilizing the vision persistence of human eyes and combining with the screen rotating at a high speed, and the display effect of the stereoscopic image can be presented.

The inventor of the present application further studied and found that, for example, the refresh rate of the display panel is 60Hz, i.e., one frame 16666us (microseconds), and assuming that the resolution is 1920×1080, i.e., a row scan is required for 1920 rows, the on time of one row of GATE signal lines GATE is 8us, and the data signal data output from the data signal lines can be charged into the pixel circuit within 8 us.

In order to achieve the effect of stereoscopic display presented due to persistence of vision described in the application background, assuming that the required refresh frequency is 10000Hz, one frame 50us, assuming that the number of lines is 1920 lines, the time to each line 50 us/1920=0.026 us is not enough to charge the data signal data into the pixel circuit.

The application provides a display panel and display device, aims at solving the technical problem in the prior art.

The following describes the technical solutions of the present application and how the technical solutions of the present application solve the above technical problems in detail with specific embodiments.

An embodiment of the present application provides a display panel, referring to fig. 1, which shows a schematic structural diagram of a display area 100, and the display panel includes: at least one display area 100.

The display area 100 is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of gate signal line groups.

In the display area 100, the pixel circuit column includes M pixel circuits 110, the gate signal line group includes M gate signal lines 120 electrically connected, the data signal line group includes M data signal lines 130 disposed corresponding to the M gate signal lines 120, for simultaneously outputting data signals to the pixel circuits 110 electrically connected to the M gate signal lines 120, such that each data signal continuously outputs a design time, M is greater than or equal to 2, and M is an integer. GATE represents the GATE signal line 120 and data represents the data signal line.

The pixel circuit column of the display panel of the embodiment of the application includes M pixel circuits 110, the gate signal line 120 group includes M gate signal lines 120 electrically connected, the data signal line group includes M data signal lines 130 corresponding to the M gate signal lines 120, when the M gate signal lines 120 output gate signals to the M pixel circuits simultaneously, the M data signal lines 130 output data signals to the M pixel circuits 110 simultaneously, thereby increasing the time for each data signal line 130 to output data signals, enabling each data signal to continuously output design time, and realizing display of stereoscopic images visible to naked eyes.

Alternatively, each of the data signal lines 130 outputs a data signal for a design time of 8us, and display of stereoscopic images visible to naked eyes can be achieved.

Alternatively, the display area of the entire display panel may be divided into a plurality of adjacently arranged display areas 100, and the display areas 100 shown in fig. 1 may be denoted as row display areas, each row display area including all pixel columns.

In some embodiments, referring to fig. 2, an example is shown where m=4, the data signal line 130 is disposed in at least one metal layer. The metal layer is provided with an opening 140 for electrically connecting the data signal line 130 with the data signal output unit. The opening 140 serves as an access point between the data signal and the pixel circuit 110, and the data signal line 130 outputs the data signal data outputted from the data signal output unit to the pixel circuit 110.

Optionally, referring to fig. 2, a row of rectangular frames is a space occupied by a pixel, a length and a width are equal to a pitch, and one data signal line 130 penetrates through the whole row of pixel circuits 110, each data signal line 130 is provided with a plurality of openings 140, and each opening 140 is used for electrically connecting with one gate signal line 120 in the corresponding gate signal line group, so that four data signal lines 130 are electrically connected with four gate signal lines 120 in the gate signal line group respectively.

In some embodiments, referring to fig. 2, among the M data signal lines 130 disposed corresponding to the M gate signal lines 120, the openings 140 corresponding to the M data signal lines 130 are arranged in a staggered manner.

The inventors of the present application have found through studies that, when the pitch of each pixel is greater than 150um, assuming that pitch of each pixel is 500um, the minimum pitch of metal lines is 5um, and the space of 30 data signal lines 130 is sufficient according to the prior art, wiring can be completed using only one metal layer. However, in practical applications, more data signal lines 130 are often required, and the space of one metal layer is not enough. For example, when pitch between each pixel is less than 150um, wiring cannot be spaced with the same-layer metal line. At this time, a multi-layer metal wiring mode can be adopted, and data signal lines which can be independently led out from each column of pixels are added.

Based on the above analysis, the present application provides yet another embodiment, see fig. 3, wherein the at least one metal layer comprises a first metal layer and a second metal layer. In this embodiment, m=4. The data signal lines 130 in the first metal layer and the second metal layer are all disposed at intervals.

Specifically, the data signal line 130 includes a first data signal line 131, a second data signal line 132, a third data signal line 133, and a fourth data signal line 134. The first data signal line 131 and the third data signal line 133 are provided in the first metal layer, and the second data signal line 132 and the fourth data signal line 134 are provided in the second metal layer.

Alternatively, if all the data signal lines 130 are provided in a plurality of metal layers, as long as the data signal lines 130 in each metal layer do not overlap or cross each other at the time of wiring. That is, the first data signal line 131 and the third data signal line 133 do not overlap or cross one another, and the second data signal line 132 and the fourth data signal line 134 do not overlap or cross one another.

In some embodiments, referring to fig. 3, the first metal layer is provided with a plurality of first openings 141. The second metal layer is provided with a plurality of second openings 142.

The plurality of first openings 141 are electrically connected to at least one data signal output unit through the first metal trace.

The plurality of second openings 142 are electrically connected to at least one data signal output unit through a second metal trace.

In some embodiments, the data signal line 130, to which the pixel circuits 110 of the same row are correspondingly connected, of each display area 100 is electrically connected to at least one data signal output unit; or alternatively, the process may be performed,

the data signal lines 130, which are correspondingly connected to the pixel circuits 110 of the same row in each display area 100, are electrically connected to one data signal output unit through a multiplexer.

In the embodiment of the present application, each display area 100 may employ a plurality of data signal output units, such as Date IC (Integrated Circuit ), and the data signal data is fed at the same time to reduce the data amount requirement of each data signal output unit, or may employ a multiplexer MUX and the same data signal output unit to output different data signals data by time sharing.

In some embodiments, referring to fig. 4, M gate signal lines 120 are electrically connected to one gate signal output unit 150 in the display area 100.

Alternatively, the gate signal output unit 150 simultaneously outputs the gate signals to the M gate signal lines 120, so that the switching devices connected to the gate signal lines 120 are simultaneously turned on.

Alternatively, the gate signal output unit 150 and the data signal output unit may be simultaneously located in the driving IC of the display panel.

The inventor of the present application considers that the GOA (Gate Driver on Array) circuit, i.e. the array substrate row driving circuit, is a driving method for realizing progressive scanning by using a thin film transistor (Thin Film Transistor, TFT) liquid crystal display array process to manufacture the gate scanning driving circuit on the thin film transistor array substrate.

The GOA circuit has two basic functions: the first is to output a gate scan driving signal to drive the gate signal lines 120 in the panel, turn on the TFTs in the display area 100 to charge the pixels; and the second is a shift register function, when one signal output end outputs a gate scanning driving signal, the next signal output end outputs the gate scanning driving signal through clock control and the gate scanning driving signal is transmitted in sequence.

Based on the above analysis, in some embodiments, referring to fig. 5, in the display area 100, M gate signal lines 120 are electrically connected to one signal output terminal of the GOA circuit 160. The GOA circuit 160 includes a plurality of GOA units 161, and a signal output terminal of each GOA unit 161 is electrically connected to the M gate signal lines 120, and the plurality of GOA units 161 sequentially output gate scan driving signals.

In some embodiments, the display panel includes multiple sets of GOA circuits 160; each group of GOA circuits 160 is electrically connected to a corresponding one of the data signal output units via the data signal line 130.

Optionally, the pixel circuit 110 of each display area 100 in the embodiment of the present application selects different driving circuits according to different display types, such as a 2T1C circuit of an LCD (Liquid Crystal Display ), an OLED (Organic Light-Emitting Diode) employs pulse amplitude modulation PAM, and an LED (including miniLED/micro LED) may employ pulse width modulation PWM or pulse amplitude modulation PAM or two driving circuit manners combined.

Optionally, in the embodiment of the present application, the M gate signal lines 120 are connected in series, and the number of the data signal lines 130 is increased by M times, so that 1920 rows are divided into N groups of GOAs for concurrent display, each group has an independent data signal output unit, where m×n is greater than or equal to the total number of rows.

Alternatively, as an example, one display area 100 in the embodiment of the present application corresponds to one split screen, the display panel has 1920 rows, taking m=30 and n=10 as an example, the 1920 rows are split into 10 split screens, each split screen has 192 rows, the gate signal lines 120 of each 30 rows are connected together, the gate signal lines 120 are synchronously turned on, the number of the data signal lines 130 is increased by 30 times, and the data signal lines 130 of the 30 rows are correspondingly pulled out respectively, so that the turn-on time divided into each row can be 8us at this time, and the data signal data can be filled. In practical applications, in the dynamic body scanning technology, the resolution requirement of a general screen is not high, for example, 400 rows in total, so that the number of split screens actually needed is small.

The display panel of the embodiment of the application can meet the requirement that the turn-on time of each row of gate signal lines 120 is still 8us, and meanwhile, the data signals data output by the corresponding data signal lines 130 can be charged into the pixel circuits within 8us, so that the display effect is ensured.

Based on the same inventive concept, an embodiment of the present application provides a display device including: a display panel according to any of the embodiments of the present application.

Embodiments of the present application may fulfill the requirement of displaying extremely high refresh rates, such as: 10000Hz or more, and can be applied to an ultrahigh refresh rate display device for dynamic stereoscopic display.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

(1) When the M gate signal lines 120 output gate signals to the M pixel circuits at the same time, the M data signal lines 130 output data signals to the M pixel circuits 110 at the same time, so that the time for outputting the data signals by each data signal line 130 is increased, the design time is continuously output by each data signal, and the display of stereoscopic images visible to naked eyes is realized.

(2) The data signal lines 130 in each metal layer are not overlapped or crossed when wiring, and the data signal lines which can be independently led out of each column of pixels are added, so that the data signal lines 130 are added to ensure the display effect.

(3) In this embodiment, each display area 100 may adopt a plurality of data signal output units in the same row, and meanwhile, the data signal data is fed to reduce the data amount requirement of each data signal output unit, or may adopt a multiplexer MUX and the same data signal output unit, and design and selection can be performed according to practical application requirements by outputting different data signals data in a time-sharing manner.

(4) The display panel of the embodiment of the application can meet the requirement that the on time of each row of gate signal lines 120 is still the on time required by image display, and meanwhile, the data signals data output by the corresponding data signal lines 130 can be charged into the pixel circuits in the corresponding time, so that the stereoscopic image display effect is ensured.

(5) Embodiments of the present application may fulfill the requirement of displaying extremely high refresh rates, such as: 10000Hz or more, and can be applied to an ultrahigh refresh rate display device for dynamic stereoscopic display.

Those of skill in the art will appreciate that the various operations, methods, steps in the flow, actions, schemes, and alternatives discussed in the present application may be alternated, altered, combined, or eliminated. Further, other steps, means, or steps in a process having various operations, methods, or procedures discussed in this application may be alternated, altered, rearranged, split, combined, or eliminated. Further, steps, measures, schemes in the prior art with various operations, methods, flows disclosed in the present application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

In the description of the present application, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the flowcharts of the figures may include a plurality of sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily being sequential, but may be performed in turn or alternately with other steps or at least a portion of the other steps or stages.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for a person skilled in the art, several improvements and modifications can be made without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. A display panel, comprising: at least one display area;

in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and are used for simultaneously outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines, so that each data signal continuously outputs design time, M is more than or equal to 2, and M is an integer;

the data signal line is arranged in at least one metal layer; the metal layer is provided with an opening for electrically connecting the data signal line with the data signal output unit;

the openings corresponding to the M data signal lines are arranged in a staggered manner in the M data signal lines corresponding to the M gate signal lines;

the at least one metal layer includes a first metal layer and a second metal layer; the data signal lines in the first metal layer and the second metal layer are all arranged at intervals.

2. The display panel of claim 1, wherein the first metal layer is provided with a plurality of first openings;

the second metal layer is provided with a plurality of second openings;

the second openings are electrically connected with at least one data signal output unit through second metal wires.

3. The display panel according to claim 1, wherein a data signal line to which the pixel circuits of each of the display regions are connected in correspondence in the same row is electrically connected to at least one data signal output unit; or alternatively, the process may be performed,

the data signal lines of each display area, which are correspondingly connected with the pixel circuits in the same row, are electrically connected with one data signal output unit through a multiplexer.

4. The display panel according to claim 1, wherein in the display region, the M gate signal lines are electrically connected to one gate signal output unit.

5. The display panel of claim 1, wherein in the display region, the M gate signal lines are each electrically connected to one signal output terminal of the GOA circuit.

6. The display panel of claim 5, wherein the display panel comprises multiple sets of GOA circuits;

and each group of pixel circuits electrically connected with the GOA circuit are correspondingly and electrically connected with one data signal output unit through the data signal line.

7. A display device, comprising: the display panel of any one of claims 1-6.