CN113296325A

CN113296325A - Display panel and display device

Info

Publication number: CN113296325A
Application number: CN202110587331.XA
Authority: CN
Inventors: 张晨阳; 李付强; 张振宇
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2021-05-27
Filing date: 2021-05-27
Publication date: 2021-08-24
Anticipated expiration: 2041-05-27
Also published as: CN113296325B

Abstract

The embodiment of the application provides a display panel and a display device. The display panel includes: at least one display area; the display area is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of grid signal line groups; in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and used for outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines simultaneously, so that each data signal is continuously output for a design time, M is more than or equal to 2, and M is an integer. According to the embodiment of the application, the time for each data signal line to output the data signal can be prolonged, so that each data signal continuously outputs the designed time, and the display of the stereoscopic image visible to naked eyes is realized.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display panels, in particular to a display panel and a display device.

Background

The refresh rate of the display panel is 50Hz (hertz) to 60Hz (hertz), and after the refresh rate is higher than 60Hz, the human eye cannot distinguish the continuously refreshed pictures because the human eye has the phenomenon of persistence of vision, and when the refresh rate of the screen is high enough, the phenomenon of persistence of pictures can be formed in the brain.

At present, the effect of stereoscopic display due to persistence of vision described in the application background is achieved, and the refresh rate of display with respect to a two-dimensional image is greatly increased, so that the time for charging a data signal into a pixel circuit is shortened, and thus display of a stereoscopic image visible to the naked eye cannot be achieved.

Disclosure of Invention

The application provides a display panel and a display device aiming at the defects of the prior art, and aims to solve the technical problems that in the prior art, the time for charging a data signal of the display panel into a pixel circuit is short, and the display of a stereoscopic image visible to naked eyes cannot be realized.

In a first aspect, an embodiment of the present application provides a display panel, including: at least one display area;

the display area is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of grid signal line groups;

in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and used for outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines simultaneously, so that each data signal is continuously output for a design time, M is more than or equal to 2, and M is an integer.

In one possible implementation, the data signal lines are disposed in at least one metal layer;

the metal layer is provided with an opening for electrically connecting the data signal line with the data signal output unit.

In one possible implementation manner, in the M data signal lines disposed corresponding to the M gate signal lines, the openings corresponding to the M data signal lines are arranged in a staggered manner.

In one possible implementation, the at least one metal layer includes a first metal layer and a second metal layer;

the data signal lines in the first metal layer and the second metal layer are arranged at intervals.

In one possible implementation manner, the first metal layer is provided with a plurality of first openings;

the second metal layer is provided with a plurality of second openings;

the plurality of first openings are electrically connected with the at least one data signal output unit through the first metal wiring;

the plurality of second openings are electrically connected with the at least one data signal output unit through the second metal routing.

In one possible implementation manner, the data signal lines correspondingly connected to the pixel circuits in the same row in each display area are electrically connected with at least one data signal output unit; alternatively, the first and second electrodes may be,

the data signal lines correspondingly connected with the pixel circuits of the same row in each display area are electrically connected with one data signal output unit through the multi-way gate.

In one possible implementation, M gate signal lines are electrically connected to one gate signal output unit in the display region.

In one possible implementation manner, in the display area, the M gate signal lines are all electrically connected with one signal output end in the GOA circuit.

In one possible implementation, the display panel includes a plurality of groups of GOA circuits;

and the pixel circuits electrically connected with each group of GOA circuits are correspondingly and electrically connected with one data signal output unit through data signal lines.

In a second aspect, an embodiment of the present application provides a display device, including: such as the display panel of the first aspect.

The beneficial technical effects brought by the technical scheme provided by the embodiment of the application comprise:

in the display region of the display panel of the embodiment of the application, the pixel circuit column includes M pixel circuits, the gate signal line group includes M gate signal lines electrically connected, the data signal line group includes M data signal lines correspondingly arranged with the M gate signal lines, when the M gate signal lines output gate signals to the M pixel circuits simultaneously, the M data signal lines output data signals to the M pixel circuits simultaneously, so that the time for each data signal line to output data signals is increased, each data signal continuously outputs the design time, and the display of a stereoscopic image visible to the naked eye is realized.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

fig. 1 is a schematic structural diagram of a display area of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of an arrangement of gate signal lines and data signal lines of a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of an arrangement of gate signal lines and data signal lines of another display panel according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 5 is a schematic structural diagram of another display panel provided in the embodiment of the present application.

Reference numerals:

100-display area, 110-pixel circuit, 120-gate signal line, 130-data signal line;

131-a first data signal line, 132-a second data signal line, 133-a third data signal line, 134-a fourth data signal line;

140-opening, 141-first opening, 142-second opening;

150-a gate signal output unit;

160-GOA circuit and 161-GOA unit.

Detailed Description

Reference will now be made in detail to the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar parts or parts having the same or similar functions throughout. In addition, if a detailed description of the known art is not necessary for illustrating the features of the present application, it is omitted. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.

It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.

The inventor of the present application has studied and found that, when the refresh rate of a general display panel is 50Hz to 60Hz and the refresh rate is higher than 60Hz, the human eye cannot distinguish the continuously refreshed picture, because the human eye has the phenomenon of persistence of vision, and when the refresh rate of the screen is high enough, the phenomenon of persistence of picture is formed in the brain. Our real world is a three-dimensional world, and the most common way to express three-dimensional effects is to use a two-dimensional screen to display a rotated 2D image, which can be expressed as follows:

3D-Effect 2D-image + rotational transformation

I.e. dynamic volume scanning techniques, the imaging volume of which is built up by means of a periodic movement of the display device.

The stereoscopic image is divided into a plurality of layers along the section, each image after the stereoscopic image is divided is played on the display screen, when the refresh rate of the screen is high enough, the screen rotating at high speed is matched, and by using the persistence of vision of human eyes, a viewer can simultaneously view images of a plurality of depth planes, so that the display effect of the stereoscopic image can be presented.

The inventor of the present application further studies and finds that, for example, the refresh rate of the display panel is 60Hz, i.e., 16666us (microseconds) for one frame, and assuming that the resolution is 1920 × 1080, i.e., 1920 rows of scanning is required, the on time of one row of GATE signal lines GATE is 8us, and the data signal data output by the data signal line can be charged into the pixel circuit within 8 us.

In order to realize the effect of stereoscopic display due to persistence of vision described in the application background, assuming that the refresh frequency is required to be 10000Hz, one frame is 50us, and assuming that the number of lines is also 1920 lines, the time 50us/1920 divided into each line is 0.026us, which is not enough to charge the data signal data into the pixel circuit.

The application provides a display panel and a display device, which aim to solve the technical problems in the prior art.

The following describes the technical solutions of the present application and how to solve the above technical problems with specific embodiments.

An embodiment of the present application provides a display panel, which is shown in fig. 1 and shows a schematic structural diagram of a display area 100, and the display panel includes: at least one display area 100.

The display area 100 is correspondingly provided with a plurality of pixel circuit columns, at least two data signal line groups and a plurality of gate signal line groups.

In the display area 100, the pixel circuit column includes M pixel circuits 110, the gate signal line group includes M gate signal lines 120 electrically connected to each other, and the data signal line group includes M data signal lines 130 disposed corresponding to the M gate signal lines 120 and configured to simultaneously output data signals to the pixel circuits 110 electrically connected to the M gate signal lines 120, so that each data signal is continuously output for a design time, M is greater than or equal to 2, and M is an integer. GATE denotes a GATE signal line 120, and DATA denotes a DATA signal line.

The pixel circuit column of the display panel in the embodiment of the application includes M pixel circuits 110, the gate signal line 120 sets M gate signal lines 120 electrically connected to each other, the data signal line set includes M data signal lines 130 correspondingly disposed to the M gate signal lines 120, and when the M gate signal lines 120 output gate signals to the M pixel circuits at the same time, the M data signal lines 130 output data signals to the M pixel circuits 110 at the same time, so that the time for each data signal line 130 to output data signals is increased, each data signal continues to output the design time, and the display of a stereoscopic image visible to the naked eye is realized.

Alternatively, each data signal line 130 outputs a data signal for a designed time of 8us, and display of a stereoscopic image visible to the naked eye can be achieved.

Alternatively, the display area of the whole display panel may be divided into a plurality of adjacently arranged display areas 100, and the display area 100 shown in fig. 1 may be illustrated as a row display area, each row display area including all pixel columns.

In some embodiments, referring to fig. 2, which shows an example when M-4, the data signal line 130 is disposed in at least one metal layer. The metal layer is provided with an opening 140 for electrically connecting the data signal line 130 with the data signal output unit. The opening 140 serves as an access point for the data signal and the pixel circuit 110, and the data signal line 130 outputs the data signal data output by the data signal output unit to the pixel circuit 110.

Optionally, referring to fig. 2, in the figure, a row of rectangular frames is a space occupied by one pixel, the length and the width are a pitch, one data signal line 130 penetrates through the entire row of pixel circuits 110, each data signal line 130 is provided with a plurality of openings 140, each opening 140 is used for electrically connecting one gate signal line 120 in a corresponding gate signal line group, so that the four data signal lines 130 are electrically connected with the four gate signal lines 120 in the gate signal line group respectively.

In some embodiments, referring to fig. 2, in the M data signal lines 130 disposed corresponding to the M gate signal lines 120, the openings 140 corresponding to the M data signal lines 130 are arranged in a staggered manner.

The inventor of the present application has found through research that when the pitch of each pixel is greater than 150um, assuming that the pitch of each pixel is 500um, according to the existing process level, the minimum pitch of the metal lines is 5um, the space of 30 data signal lines 130 is sufficient, and the wiring can be completed by using only one metal layer. However, in practical applications, more data signal lines 130 are often needed, and thus the space of one metal layer cannot meet the requirement. For example, when pitch between each pixel is less than 150um, it is impossible to space wiring with the same layer of metal lines. At this time, a multi-layer metal wiring mode can be adopted, and data signal lines which can be led out independently from each row of pixels are increased.

Based on the above analysis, the present application provides yet another embodiment, as shown in fig. 3, wherein the at least one metal layer comprises a first metal layer and a second metal layer. In this embodiment, M is 4. The data signal lines 130 in the first metal layer and the second metal layer are disposed at intervals.

Specifically, the data signal lines 130 include a first data signal line 131, a second data signal line 132, a third data signal line 133, and a fourth data signal line 134. The first and third data signal

lines

131 and 133 are disposed in the first metal layer, and the second and fourth data signal

lines

132 and 134 are disposed in the second metal layer.

Alternatively, if all the data signal lines 130 are disposed in a plurality of metal layers, as long as the data signal lines 130 in each metal layer do not overlap or cross each other when wired. That is, the first data signal line 131 and the third data signal line 133 do not overlap or cross each other, and the second data signal line 132 and the fourth data signal line 134 do not overlap or cross each other.

In some embodiments, referring to fig. 3, the first metal layer defines a plurality of first openings 141. The second metal layer defines a plurality of second openings 142.

The plurality of first openings 141 are electrically connected to the at least one data signal output unit through the first metal traces.

The plurality of second openings 142 are electrically connected to the at least one data signal output unit through the second metal traces.

In some embodiments, the data signal lines 130, to which the pixel circuits 110 of each display region 100 in the same row are correspondingly connected, are electrically connected to at least one data signal output unit; alternatively, the first and second electrodes may be,

the data signal lines 130, which are correspondingly connected to the pixel circuits 110 in the same row in each display area 100, are electrically connected to one data signal output unit through a multiplexer.

In the embodiment of the present invention, each display area 100 may adopt a plurality of data signal output units, such as Date ICs (Integrated circuits), in the same row, and simultaneously input the data signals data to reduce the requirement for the data amount of each data signal output unit, or adopt a multiplexer MUX and the same data signal output unit to output different columns of data signals data in a time-sharing manner.

In some embodiments, referring to fig. 4, M gate signal lines 120 are electrically connected to one gate signal output unit 150 in the display region 100.

Alternatively, the gate signal output unit 150 simultaneously outputs gate signals to the M gate signal lines 120 so that the switching devices connected to the gate signal lines 120 are simultaneously turned on.

Alternatively, the gate signal output unit 150 and the data signal output unit may be simultaneously located within the driving IC of the display panel.

The inventor of the present application considers that a gate Driver on array (goa) circuit is an array substrate row driving circuit, which is a driving method for realizing line-by-line scanning by fabricating a gate scanning driving circuit on a Thin Film Transistor (TFT) array substrate by using a TFT (Thin Film Transistor) lcd array process.

The GOA circuit has two basic functions: the first is to output a gate scanning driving signal to drive the gate signal lines 120 in the panel and turn on the TFTs in the display area 100 to charge the pixels; and the second is a shift register function, when the gate scanning driving signal output by one signal output end is finished, the gate scanning driving signal output by the next signal output end is controlled by a clock and is sequentially transmitted.

Based on the above analysis, in some embodiments, referring to fig. 5, in the display area 100, the M gate signal lines 120 are electrically connected to one signal output terminal of the GOA circuit 160. The GOA circuit 160 includes a plurality of GOA units 161, a signal output terminal of each GOA unit 161 is electrically connected to the M gate signal lines 120, and the plurality of GOA units 161 sequentially output gate scan driving signals.

In some embodiments, the display panel includes multiple sets of GOA circuits 160; the pixel circuits 110 electrically connected to each group of GOA circuits 160 are correspondingly electrically connected to a data signal output unit through the data signal lines 130.

Alternatively, the pixel circuit 110 of each Display area 100 in the embodiment of the present application selects different driving circuits according to different Display types, such as a 2T1C circuit of an LCD (Liquid Crystal Display), an OLED (Organic Light-Emitting Diode) using pulse amplitude modulation PAM, and an LED (including a miniLED/micro LED) using pulse width modulation PWM or pulse amplitude modulation PAM or a combination of the two driving circuits.

Optionally, in the embodiment of the present application, M gate signal lines 120 are connected in series, the number of the data signal lines 130 is increased to M times, 1920 rows are divided into N groups of GOAs for concurrent display, each group has a separate data signal output unit, and M × N is greater than or equal to the total number of rows.

Optionally, as an example, one display area 100 of the embodiment of the present application corresponds to one split screen, the display panel has 1920 lines, taking M as 30 and N as 10 as an example, the 1920 lines are split into 10 split screens and 192 lines per split screen, the gate signal lines 120 of each 30 lines are connected together, the gate signal lines 120 are synchronously turned on, the number of the data signal lines 130 is increased by 30 times, the data signal lines 130 of the 30 lines are correspondingly pulled out, and at this time, the on time of each line is 8us for the data signal data to be charged. In practical applications, in the dynamic volume scanning technology, the resolution requirement of a general screen is not high, for example, 400 lines in total, the number of actually required split screens is small.

The display panel of the embodiment of the application can meet the requirement that the turn-on time of each row of the gate signal lines 120 is still 8us, and simultaneously, the data signals data output by the corresponding data signal lines 130 can be charged into the pixel circuits in 8us, so that the display effect is ensured.

Based on the same inventive concept, an embodiment of the present application provides a display device, including: a display panel as in any one of the embodiments of the present application.

The embodiment of the application can meet the requirement of displaying extremely high refresh rate, for example: 10000Hz or more, and can be applied to a display device with ultra-high refresh rate of dynamic three-dimensional display.

By applying the embodiment of the application, at least the following beneficial effects can be realized:

(1) when the M gate signal lines 120 output gate signals to the M pixel circuits at the same time, the M data signal lines 130 output data signals to the M pixel circuits 110 at the same time, so that the time for each data signal line 130 to output the data signals is increased, each data signal continues to output the design time, and the display of a stereoscopic image visible to the naked eye is realized.

(2) The data signal lines 130 in the embodiment of the application are arranged in at least one metal layer, the data signal lines 130 in each metal layer are not overlapped or crossed during wiring, and data signal lines which can be led out independently from each column of pixels are added, so that the data signal lines 130 are added to ensure the display effect.

(3) In each display area 100 of the embodiment of the application, a plurality of data signal output units can be adopted in the same row, the data quantity requirement of each data signal output unit is reduced by simultaneously feeding the data signals data, a Multiplexer (MUX) and the same data signal output unit can be adopted, different columns of data signals data are output in a time-sharing mode, and design and selection can be performed according to actual application requirements.

(4) The display panel of the embodiment of the application can meet the requirement that the turn-on time of each row of gate signal lines 120 is still the turn-on time required by image display, and simultaneously, the data signals data output by the corresponding data signal lines 130 can be charged into the pixel circuits within the corresponding time, so that the display effect of the stereoscopic image is ensured.

(5) The embodiment of the application can meet the requirement of displaying extremely high refresh rate, for example: 10000Hz or more, and can be applied to a display device with ultra-high refresh rate of dynamic three-dimensional display.

Those of skill in the art will appreciate that the various operations, methods, steps in the processes, acts, or solutions discussed in this application can be interchanged, modified, combined, or eliminated. Further, other steps, measures, or schemes in various operations, methods, or flows that have been discussed in this application can be alternated, altered, rearranged, broken down, combined, or deleted. Further, steps, measures, schemes in the prior art having various operations, methods, procedures disclosed in the present application may also be alternated, modified, rearranged, decomposed, combined, or deleted.

In the description of the present application, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a particular orientation, be constructed in a particular orientation, and be operated, and thus should not be construed as limiting the present application.

The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless otherwise specified.

In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

In the description herein, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

It should be understood that, although the steps in the flowcharts of the figures are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least a portion of the steps in the flow chart of the figure may include multiple sub-steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed alternately or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

The foregoing is only a partial embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the principle of the present application, and these modifications and decorations should also be regarded as the protection scope of the present application.

Claims

1. A display panel, comprising: at least one display area;

in the display area, the pixel circuit column comprises M pixel circuits, the grid signal line group comprises M grid signal lines which are electrically connected, the data signal line group comprises M data signal lines which are correspondingly arranged with the M grid signal lines and used for outputting data signals to the pixel circuits which are electrically connected with the M grid signal lines simultaneously, so that each data signal continuously outputs the designed time, M is more than or equal to 2, and M is an integer.

2. The display panel according to claim 1, wherein the data signal line is provided in at least one metal layer;

3. The display panel according to claim 2, wherein the openings corresponding to the M data signal lines are arranged in a staggered manner among the M data signal lines provided corresponding to the M gate signal lines.

4. The display panel of claim 3, wherein the at least one metal layer comprises a first metal layer and a second metal layer;

and the data signal lines in the first metal layer and the second metal layer are arranged at intervals.

5. The display panel of claim 4, wherein the first metal layer defines a plurality of first openings;

the second metal layer is provided with a plurality of second openings;

the plurality of first openings are electrically connected with the at least one data signal output unit through a first metal wire;

the plurality of second openings are electrically connected with the at least one data signal output unit through a second metal routing.

6. The display panel according to claim 1, wherein the data signal lines to which the pixel circuits of the same row of each of the display regions are correspondingly connected are electrically connected to at least one data signal output unit; alternatively, the first and second electrodes may be,

and the data signal lines correspondingly connected with the pixel circuits in the same row of each display area are electrically connected with one data signal output unit through a multi-way gate.

7. The display panel according to claim 1, wherein the M gate signal lines are electrically connected to one gate signal output unit in the display region.

8. The display panel according to claim 1, wherein the M gate signal lines are each electrically connected to one signal output terminal in a GOA circuit in the display region.

9. The display panel according to claim 8, wherein the display panel comprises a plurality of groups of GOA circuits;

10. A display device, comprising: the display panel of any one of claims 1-9.