CN113285745B - Signal transmitting method, signal transmitting device, electronic equipment and storage medium - Google Patents
Signal transmitting method, signal transmitting device, electronic equipment and storage medium Download PDFInfo
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- CN113285745B CN113285745B CN202110587958.5A CN202110587958A CN113285745B CN 113285745 B CN113285745 B CN 113285745B CN 202110587958 A CN202110587958 A CN 202110587958A CN 113285745 B CN113285745 B CN 113285745B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0615—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal
- H04B7/0617—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of weighted versions of same signal for beam forming
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B7/00—Radio transmission systems, i.e. using radiation field
- H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
- H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas
- H04B7/06—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
- H04B7/0613—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission
- H04B7/0667—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station using simultaneous transmission of delayed versions of same signal
Abstract
The signal transmitting method, the signal transmitting device, the electronic equipment and the storage medium are applied to the technical field of signal processing, and the method comprises the following steps: responding to a received signal transmitting instruction, and acquiring input data and delay frequency; representing the input data by a first register of a first number of bits and representing the input data at the delay frequency by a second register of the first number of bits; expressing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of a target digit in the third register; expressing the value after the target digit in the third register through a fourth register with the second digit so as to carry out frequency division processing on the target value and generate a delay carrier signal; and combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmitting the delayed focusing signal through the phased array transducer. The present disclosure reduces register resources required for delayed focused transmission of signals.
Description
Technical Field
The present disclosure relates to signal processing technologies, and in particular, to a signal transmitting method and apparatus, an electronic device, and a storage medium.
Background
Phased array signal control can enable the excitation signal to carry out beam forming at a certain point in space, namely, signals are focused at a target point through time delay control of a channel. By making the signals have the same phase when arriving at a point in space, the superposition enhancement can be performed at the point, and the superposition reduction or even cancellation can be performed in the space outside the point due to the different phases.
Most of the traditional signal delay focusing methods send signals into a register, and the signals are buffered step by step according to a certain clock beat through the clock beat. When the clock beat number reaches the time corresponding to the delay data, the signal is sent out to the channel. When the delay data is thousands or even tens of thousands of clock beats, the control mode undoubtedly occupies a lot of register resources, so that the on-chip resources of the chip are in shortage and even the chip cannot work normally.
Disclosure of Invention
In view of this, embodiments of the present disclosure provide a signal transmitting method and apparatus, an electronic device, and a storage medium, which are used to solve the problem that in the related art, a register needs to be used to perform step-by-step caching on delay data to implement delay focused transmission of a signal, and excessive register resources need to be consumed.
A first aspect of the present disclosure provides a signal transmission method, including:
responding to a received signal transmitting instruction, and acquiring input data and delay frequency;
representing the input data by a first register of a first number of bits and representing the input data at the delay frequency by a second register of the first number of bits, the first number of bits being greater than a target number of bits;
representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register;
representing values behind a target digit in a third register through a fourth register of a second digit to perform frequency division processing on the target values to generate a delayed carrier signal, wherein the second digit is greater than or equal to the target digit;
and combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmitting the delayed focusing signal through a phased array transducer.
Optionally, the frequency division processing on the target value to generate a delayed carrier signal includes:
when the target value is in a target value range, determining that the signal enable is 1, and when the target value is not in the target value range, determining that the signal enable is 0;
and generating a delay carrier signal according to the delay signal enable.
Optionally, when the delayed carrier signal includes at least two cycles, the target value range includes: a target period value range corresponding to each period;
when the target value is within the target value range, determining that the signal enable is 1, and when the target value is not within the target value range, determining that the signal enable is 0, including:
when the target value is in a target period value range corresponding to any period, determining that the signal enable corresponding to any period is 1, and when the target value is not in the target period value range corresponding to any period, determining that the signal enable corresponding to any period is 0;
the generating of the delayed carrier signal according to the delayed signal enable includes:
and generating a delay carrier signal according to the signal enable corresponding to each period.
Optionally, the signal transmission instruction at least includes: a transmission distance and a data address;
the acquiring input data and delay frequency in response to receiving a signal transmission instruction comprises:
acquiring input data according to the data address;
and acquiring the delay frequency of the transmitted data according to the transmitting distance and the pulse frequency of the input data.
Optionally, the combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal includes:
and performing phase-and-phase processing on the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal.
Optionally, before the representing the input data by the first register of the first bit number and the representing the input data at the delay frequency by the second register of the first bit number, the method further comprises:
and acquiring a first digit according to the target digit, the delay times and the first anti-overflow digit.
Optionally, before the value after the target bit number in the third register is represented by the fourth register with the second bit number to perform frequency division processing on the target value and generate the delayed carrier signal, the method further includes:
and acquiring a second digit according to the target digit, the delay times and the second anti-overflow digit.
In accordance with a second aspect of the present disclosure, there is provided a signal transmitting apparatus, the apparatus comprising:
a receiving module configured to acquire input data and a delay frequency in response to receiving a signal transmission instruction;
a processing module configured to represent the input data by a first register of a first number of bits and to represent the input data at the delay frequency by a second register of the first number of bits, the first number of bits being greater than a target number of bits;
representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register;
representing a value behind a target digit in a third register through a fourth register of a second digit to perform frequency division processing on the target value to generate a delay carrier signal, wherein the second digit is greater than or equal to the target digit;
and the transmitting module is configured to combine the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmit the delayed focusing signal through the phased array transducer.
Optionally, the processing module is further configured to:
when the target value is in a target value range, determining that the signal enable is 1, and when the target value is not in the target value range, determining that the signal enable is 0;
and generating a delay carrier signal according to the delay signal enable.
Optionally, when the delayed carrier signal includes at least two cycles, the target value range includes: the value range of the target period corresponding to each period;
optionally, the processing module is further configured to:
when the target value is in a target period value range corresponding to any period, determining that the signal enable corresponding to any period is 1, and when the target value is not in the target period value range corresponding to any period, determining that the signal enable corresponding to any period is 0;
and generating a delayed carrier signal according to the signal enable corresponding to each period.
Optionally, the signal transmission instruction at least includes: a transmission distance and a data address;
the receiving module is further configured to:
acquiring input data according to the data address;
and acquiring the delay frequency of the transmitted data according to the transmitting distance and the pulse frequency of the input data.
Optionally, the transmitting module is further configured to:
and performing phase-and-phase processing on the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal.
Optionally, the processing module is further configured to: and acquiring a first digit according to the target digit, the delay times and the first anti-overflow digit.
Optionally, the processing module is further configured to:
and acquiring a second digit according to the target digit, the delay times and the second anti-overflow digit.
According to a third aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the signal transmission method of the first aspect described above.
According to a fourth aspect of the present disclosure, there is provided an electronic device, including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the signal transmission method according to the first aspect.
To the prior art, this disclosure possesses following advantage:
according to the signal transmitting method, the signal transmitting device, the electronic equipment and the storage medium, the first register and the second register are adopted to carry out delay processing on input data and store the input data in the third register, the delay excitation signal is generated according to the value of the target digit in the third register, then the excitation signal in the third register is modulated through the fourth register to obtain the delay carrier signal, finally the obtained delay excitation signal and the delay carrier signal are combined to control the phased array ring energy device to carry out delay focusing transmission, only four registers are needed to complete delay focusing transmission on the signal, and register resources needed by signal delay focusing transmission are reduced.
The foregoing description is only an overview of the technical solutions of the present disclosure, and the embodiments of the present disclosure are described below in order to make the technical means of the present disclosure more clearly understood and to make the above and other objects, features, and advantages of the present disclosure more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the disclosure. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a flowchart illustrating steps of a signal transmission method according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram illustrating an effect of a signal transmission method according to an embodiment of the disclosure;
fig. 3 is a flowchart illustrating steps of another signal transmission method provided by an embodiment of the present disclosure;
fig. 4 is a flowchart illustrating a second step of another signal transmission method according to an embodiment of the disclosure;
fig. 5 is a flowchart illustrating a third step of another signal transmission method according to an embodiment of the disclosure;
fig. 6 is a block diagram of a signal transmitting apparatus according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Fig. 1 is a schematic diagram illustrating steps of a signal transmission method provided in an embodiment of the present disclosure, where the method may include:
In the embodiment of the present disclosure, the executing body of the steps of the present disclosure may be a signal transmitting system, where the signal transmitting system at least includes a processor and a phased array transducer, and the processor is configured to control the phased array transducer to implement a signal transmitting function.
The signal transmitting instruction is an instruction for instructing delayed focusing transmission of input data, and the signal transmitting instruction can be input by a user or automatically generated by a system. Specifically, the signal transmitting system reads input data from an internal data source or an external data source according to a received signal transmitting instruction, the input data is data which needs to be transmitted in a delayed focusing mode by the phased array ring energy device, the delay frequency refers to the working frequency of the phased array ring energy device when transmitting signals to the input data, the delay frequency can be set manually or automatically by the system, and the delay frequency can be specifically set according to actual requirements and is not limited here.
And 102, representing the input data through a first register with a first digit, and representing the input data at the delay frequency through a second register with the first digit, wherein the first digit is greater than the target digit.
In the disclosed embodiment, the first register and the second register are both functional modules for storing data, and may be registers of timer status, where the stored data is represented in the form of 0 and 1. The first register is different from the second register in that the first register is used for directly representing input data, and the second register is used for representing the input data at a delay frequency. It should be noted that the bits of the first register and the second register need to be equal, that is, both are the first bits, to ensure that the bits of the two registers for performing subsequent data delay are the same, and the bits of the first register and the second register meet the requirement of performing subsequent signal frequency division, because the target bit refers to the bits for performing subsequent signal value division, it needs to ensure that the number of the registers for performing the first bits counted after the target bit at least meets the requirement of the delay times, for example: assuming that the target number of bits is 5 and that a signal needs to be transmitted through 2 elements in the phased array transducer, the transmitted signal needs to be delayed 2 times, and then the number of bits in the register can be counted 2 times after the target number of bits, and the first number can be chosen to be the target number plus 2, i.e. 7 bits.
103, representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register.
In the embodiment of the present disclosure, the third register is similar to the first register and the second register, except that the third register is used for representing a value difference between the first register and the second register. It can be understood that, since the first register is used for representing the input data and the second register is used for representing the input data at the delayed frequency, the difference between the input data and the input data at the delayed frequency is the input data after the delayed frequency, i.e. the third register is used for representing the input data after the delayed frequency, thereby completing the delayed processing on the input data. Furthermore, since the delay frequency is usually an integer multiple of the frequency of the delay excitation signal to be transmitted, the value of a certain bit in the input data after the delay frequency is the same as the value of the delay excitation signal, and therefore the certain bit can be designated as a target bit, so that the target bit of the data after the delay frequency in the third register is used as an enable value of the delay excitation signal, and the delay excitation signal is generated by controlling the phased array transducer.
Illustratively, assuming that the first bit number is 19 bits and the target bit number is 9 bits, then a counter Cnt _0[ 2 ] of the first register as 19 bits is defined for representing input data, a register Num [18 [ 0] of the second register as 19 bits is used for representing input data at a delayed frequency, and a timer Cnt _1[18 ] of the third register as 19 [18 ] is used for representing input data after the delayed frequency, then Cnt _1[18 ] = 0[18 ] -Num [18 ] can take a value of 9 bits of Cnt _1[18 ] representing a delayed excitation signal, i.e., clk _40khz = Cnt 1[8], where Cnt _1[8] is the 9 th bit of Cnt _1[18 ].
And step 104, representing a value after the target digit in the third register through a fourth register with a second digit to perform frequency division processing on the target value to generate a delayed carrier signal, wherein the second digit is greater than or equal to the target digit.
In the embodiment of the present disclosure, the fourth register is similar to the first register, the second register, and the third register, except that the fourth register is only used for representing values of a partial bit number of the input data after the delay frequency. Specifically, the value of the target digit in the third register is obtained by adding one to each rising edge counter, that is, counting after the target digit of the third register, so that the value after the target digit in the third register can be used as the value of the delayed excitation signal, and the value after the target digit is represented by the fourth register in which the second digit is greater than the target digit, so as to divide the frequency of the delayed excitation signal to obtain the delayed carrier signal. It should be noted that, because the delayed carrier signal is obtained by frequency division from the delayed excitation signal, it is necessary to ensure that the bit number of the delayed carrier signal is greater than or equal to the value bit number of the delayed excitation signal, that is, the second bit number of the fourth register needs to be greater than or equal to the target bit number of the third register.
For example, assuming that a third register is used to represent input data after a delay frequency of 20.48MHz, and a 9 th bit of the third register represents a delay excitation signal of 40KHz, a 10-counter Cnt _2, [ 9] at 40KHz can be defined as a fourth register to represent a value after the 9 th bit in the third register, that is, cnt _2, [ 9] = Cnt _1, [18 ].
And 105, combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmitting the delayed focusing signal through a phased array transducer.
Illustratively, referring to fig. 2, clk _20.48MHz represents the timing of input data at 20.48MHz, cnt _0 represents the value timing in the first register, delay represents the value timing in the second register, cnt _1 represents the value timing in the third register, clk _40KHz represents the timing of the delayed excitation signal at 40KHz, and cnt _2 represents the value timing in the fourth register.
In the embodiment of the present disclosure, the combining manner of the delayed excitation signal and the delayed carrier signal may be an and or an equal logic operation combining manner, and may be specifically set according to an actual requirement, which is not limited herein. The time delay focusing signal is transmitted by controlling different array elements in the phased array transducer, and the time delay focusing signal transmitted by each array element is obtained by converting the same input data, so that the time delay focusing signal transmitted by each array element can be focused at the same phase in space, and the time delay focusing transmission of the input data is realized.
According to the method and the device, the first register and the second register are adopted to carry out delay processing on input data and deliver the input data to the third register for storage, the delay excitation signal is generated according to the value of the target digit in the third register, then the excitation signal in the third register is modulated through the fourth register to obtain the delay carrier signal, finally the obtained delay excitation signal and the delay carrier signal are combined to control the phased array circulator to carry out delay focusing transmission, only four registers are needed to complete delay focusing transmission on the signal, and register resources needed by signal delay focusing transmission are reduced
Optionally, referring to fig. 3, the step 104 includes:
in the substep 1041, when the target value is within the target value range, it is determined that the signal enable is 1, and when the target value is not within the target value range, it is determined that the signal enable is 0.
In the embodiment of the present disclosure, since the target value is used to represent the delay excitation signal, in order to intercept a desired signal from the delay excitation signal as the delay carrier signal, it is necessary to modulate the target value by setting a target value range, that is, if the target value is in the target value range, it is determined that the signal enable of the delay carrier signal is 1, if the target value is not in the target value range, it is determined that the signal enable of the delay carrier signal is 0, and the setting of the value of the target range may be manually set according to actual requirements or may be automatically set according to a system, for example, default ranges of 0 to 100, 0 to 200, 100 to 200, and the like, may specifically be determined according to actual requirements, and is not limited here.
And a substep 1042 of enabling to generate a delayed carrier signal according to the delayed signal.
In an embodiment of the disclosure, a system generates a delayed carrier signal from the delayed signal enable by controlling a phased array transducer.
Optionally, when the delayed carrier signal includes at least two cycles, the target value range includes: referring to fig. 3, the sub-step 2041 includes:
substep 20411, determining that the signal enable corresponding to any period is 1 when the target value is in the target period value range corresponding to any period, and determining that the signal enable corresponding to any period is 0 when the target value is not in the target period value range corresponding to any period.
In the embodiment of the present disclosure, the period of the delayed carrier signal may be manually set in advance, or may be set by default, for example, the default is set to 2 periods, 3 periods, and the like, and may be specifically set according to an actual requirement, which is not limited herein. If the delayed carrier signal needs to include multiple periods, a corresponding target period value range needs to be set for each period, so that the delayed excitation signal represented by the target value is modulated according to the target period value ranges corresponding to different periods, and the signal enable corresponding to each period can be obtained.
Referring to fig. 4, the sub-step 2042 includes:
substep 20421 generates a delayed carrier signal based on the signal enable corresponding to each of the periods.
In the disclosed embodiment, the signal enables corresponding to each period can be combined to be used as the signal enable of the delayed carrier signal to control the phased array transducer to generate the delayed carrier signal.
For example, assuming that it is required to send delay carrier signals En1, en2, and En3 of 3 periods, a value range of a target period of 3 periods may be:
En1＝(Cnt_2>0)&&(Cnt_2<101)；
En2＝(Cnt_2>200)&&(Cnt_2<301)；
En3＝(Cnt_2>400)&&(Cnt_2<501)；
wherein & & represents a logical and, cnt _2 represents a target value in the fourth register, i.e., when Cnt _2 is greater than 0 and Cnt _2 is less than 101, en1 is 1, otherwise, en1 is 0; en2 and En3 work the same.
Optionally, the signal transmission instruction at least includes: a transmission distance and a data address;
referring to fig. 5, the step 101 includes:
and a substep 1011 of obtaining input data according to the data address.
Sub-step 1012, obtaining the delay frequency of the transmission data according to the transmission distance and the pulse frequency of the input data.
In the disclosed embodiment, the data address refers to the storage address of the input data, and the transmission distance refers to the distance between the phased array transducer and the target spatial position. The signal transmitting command received by the system needs to carry the data address and transmitting distance of the input data to be transmitted, and the system reads the input data according to the data address. The system calculates to obtain the delay time required by focusing according to the transmitting distance and the speed of the transmitting signal, then calculates the ratio based on the delay time and the pulse frequency of the transmitting signal to obtain the number of delay cycles, and finally multiplies the number of the delay cycles by the pulse frequency of the transmitting signal to obtain the delay frequency.
For example, assuming a pulse frequency of 40KHz, to generate a delayed excitation signal of 40KHz and a delayed carrier signal of 200Hz, 2 of 40KHz would be selected n The time is taken as the delay frequency, the number of delay cycles obtained by calculation is 512, and since the power of 9 of 2 is 512, if n is 9, the delay frequency f is 20.48MHz, that is, f =40khz × 512=20.48.
Optionally, the 104, includes: and performing phase-and-phase processing on the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal.
In the embodiment of the present disclosure, the merging process of the delayed excitation signal and the delayed carrier signal can be realized by performing and processing on the delayed excitation signal and the delayed carrier signal obtained by calculation.
Illustratively, the modulated output delayed focus signal Dout is then:
Dout＝Cnt_1[X]&(En1|En2|En3)；
wherein Cnt _1[ X ] represents the value of the target digit in the third register, i.e. the delayed excitation signal, (En 1| En2| En 3) is the delayed carrier signal of 3 different periods.
Optionally, before step 102, the method further comprises: and acquiring a first digit according to the target digit, the delay times and the overflow digits.
In the embodiment of the present disclosure, since a value after the target digit in the third register is required to be used as the delay excitation signal, it is required to ensure that the counted number of the digits after the delay excitation signal is less than or equal to the delay times, and therefore, the logarithm of 2 may be solved according to the delay times to obtain the delay digits, and the sum of the target digit and the delay digits is used as the first digit, further, the embodiment of the present disclosure adds the first anti-overflow digit into the first digit, where the first anti-overflow digit may be manually preset, may be set according to an actual system default, for example, 1, 2, 3 bits, and the like, and specifically may be set according to an actual requirement, where no limit identification is made here. The first digit of the register is determined by setting the first anti-overflow digit, so that the condition that the first register is error-reported when the number of counts is insufficient due to excessive data is avoided.
Optionally, before the step 104, the method further comprises: and acquiring a second digit according to the target digit, the delay times and the second anti-overflow digit.
In the embodiment of the present disclosure, the second number of bits is similar to the first number of bits, and in order to consider that the count number of the fourth register can satisfy the delay time, it is necessary to ensure that the technical number of registers in the second number of bits is greater than or equal to the delay time. Specifically, the logarithm of 2 can be solved according to the delay times to obtain the delay digit, the sum of the target digit and the delay digit is used as the second digit, similar to the first digit, and a second anti-overflow digit can be added to supplement the second digit, so as to avoid the situation that the fourth register has an error report when the counting number is insufficient due to excessive data.
According to the signal transmission method provided by the embodiment of the disclosure, the brain tumor image used for prediction in each modality can be obtained by obtaining the brain tumor images in at least two modalities; then, inputting the brain tumor image used for prediction in each modality into a semantic feature pyramid model corresponding to the modality for prediction, so as to obtain a brain tumor segmentation image corresponding to the brain tumor image used for prediction in each modality; finally, the brain tumor segmentation images of each modality are fused, so that the problems of information loss, low segmentation precision and the like in the process of segmenting the brain tumor image of a single modality can be avoided, the brain tumor images of multiple modalities can be fully utilized, and the accuracy and the efficiency of segmenting the brain tumor images of at least two modalities are improved.
Referring to fig. 6, an embodiment of the present disclosure provides a block diagram of a signal transmitting apparatus 20, where the signal transmitting apparatus 20 may include:
a receiving module 201 configured to obtain input data and a delay frequency in response to receiving a signal transmission instruction;
a processing module 202 configured to represent the input data by a first register of a first bit number and represent the input data at the delay frequency by a second register of the first bit number, the first bit number being greater than a target bit number;
representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register;
representing values behind a target digit in a third register through a fourth register of a second digit to perform frequency division processing on the target values to generate a delayed carrier signal, wherein the second digit is greater than or equal to the target digit;
and the transmitting module 203 is configured to combine the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmit the delayed focusing signal through the phased array transducer.
Optionally, the processing module 202 is further configured to:
when the target value is in a target value range, determining that the signal enable is 1, and when the target value is not in the target value range, determining that the signal enable is 0;
and generating a delay carrier signal according to the delay signal enable.
Optionally, when the delayed carrier signal includes at least two cycles, the target value range includes: a target period value range corresponding to each period;
optionally, the processing module 202 is further configured to:
when the target value is in a target period value range corresponding to any period, determining that the signal enable corresponding to any period is 1, and when the target value is not in the target period value range corresponding to any period, determining that the signal enable corresponding to any period is 0;
and generating a delayed carrier signal according to the signal enable corresponding to each period.
Optionally, the signal transmission instruction at least includes: a transmission distance and a data address;
the receiving module 201 is further configured to:
acquiring input data according to the data address;
and acquiring the delay frequency of the transmitted data according to the transmitting distance and the pulse frequency of the input data.
Optionally, the transmitting module 203 is further configured to:
and performing phase-and-phase processing on the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal.
Optionally, the processing module 202 is further configured to: and acquiring a first digit according to the target digit, the delay times and the first anti-overflow digit.
Optionally, the processing module 202 is further configured to:
and acquiring a second digit according to the target digit, the delay times and the second anti-overflow digit.
According to the method and the device, the first register and the second register are adopted to carry out delay processing on input data and deliver the input data to the third register for storage, the delay excitation signal is generated according to the value of the target digit in the third register, then the excitation signal in the third register is modulated through the fourth register to obtain the delay carrier signal, finally the obtained delay excitation signal and the delay carrier signal are combined and then the phased array circulator is controlled to carry out delay focusing emission, only four registers are needed to complete delay focusing emission on the signal, and register resources needed by signal delay focusing emission are reduced.
Example four
The embodiment of the present disclosure provides an electronic device, a memory and a program or an instruction stored on the memory and executable on the processor, wherein the program or the instruction realizes any one of the above signal transmission methods when executed by the processor.
According to the method and the device, the first register and the second register are adopted to carry out delay processing on input data and deliver the input data to the third register for storage, the delay excitation signal is generated according to the value of the target digit in the third register, then the excitation signal in the third register is modulated through the fourth register to obtain the delay carrier signal, finally the obtained delay excitation signal and the delay carrier signal are combined and then the phased array circulator is controlled to carry out delay focusing emission, only four registers are needed to complete delay focusing emission on the signal, and register resources needed by signal delay focusing emission are reduced.
EXAMPLE five
The disclosed embodiments provide a computer storage medium having a computer program stored thereon, the computer program, when executed by a processor, being capable of implementing the signal transmission method described above.
According to the embodiment of the disclosure, the first register and the second register are adopted to carry out delay processing on input data and store the input data in the third register, the delay excitation signal is generated according to the value of the target digit in the third register, then the excitation signal in the third register is modulated through the fourth register to obtain the delay carrier signal, finally, the obtained delay excitation signal and the delay carrier signal are combined to control the phased array circulator to carry out delay focusing transmission, only four registers are needed to complete the delay focusing transmission of the signal, and register resources required by the signal delay focusing transmission are reduced.
One skilled in the art will appreciate that the present disclosure includes apparatus related to performing one or more of the operations described in the present disclosure. These devices may be specially designed and manufactured for the required purposes, or they may comprise known devices in general-purpose computers. These devices have stored within them computer programs that are selectively activated or reconfigured. Such a computer program may be stored in a storage medium of a device (e.g., a computer) including, but not limited to, any type of disk including floppy disks, hard disks, optical disks, CD-ROMs, and magneto-optical disks, ROMs (Read-Only memories), RAMs (Random Access memories), EPROMs (Erasable Programmable Read-Only memories), EEPROMs (Electrically Erasable Programmable Read-Only memories), flash memories, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a bus. That is, a storage medium includes any medium that can store or transmit information in a form readable by a device (e.g., a computer).
It will be understood by those within the art that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. Those skilled in the art will appreciate that the computer program instructions may be implemented by a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the aspects specified in the block or blocks of the block diagrams and/or flowchart illustrations of the present disclosure.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present disclosure, and shall cover the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (10)
1. A method of signal transmission, the method comprising:
responding to a received signal transmitting instruction, and acquiring input data and delay frequency;
representing the input data by a first register of a first number of bits and representing the input data at the delay frequency by a second register of the first number of bits, the first number of bits being greater than a target number of bits; the target digit is used for representing a digit for subsequently carrying out signal value taking, and the data frequency on the target digit is the same as the frequency of the delayed excitation signal;
representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register;
representing values behind the target digit in the third register through a fourth register of a second digit to perform frequency division processing on the target values to generate a delayed carrier signal, wherein the second digit is greater than or equal to the target digit; the target value is used for representing the delayed excitation signal;
and combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmitting the delayed focusing signal through a phased array transducer.
2. The method of claim 1, wherein the frequency-dividing the target value to generate the delayed carrier signal comprises:
when the target value is in a target value range, determining that the signal enable is 1, and when the target value is not in the target value range, determining that the signal enable is 0;
and generating a delay carrier signal according to the delay signal enable.
3. The method of claim 2, wherein when the delayed carrier signal includes at least two cycles, the target range comprises: the value range of the target period corresponding to each period;
when the target value is in the target value range, determining that the signal enable is 1, and when the target value is not in the target value range, determining that the signal enable is 0, including:
when the target value is in a target period value range corresponding to any period, determining that the signal enable corresponding to any period is 1, and when the target value is not in the target period value range corresponding to any period, determining that the signal enable corresponding to any period is 0;
the enabling of the generation of the delayed carrier signal according to the delayed signal comprises the following steps:
and generating a delay carrier signal according to the signal enable corresponding to each period.
4. The method according to claim 1, characterized in that said signal transmission instructions comprise at least: a transmission distance and a data address;
the step of acquiring input data and delay frequency in response to receiving a signal transmission instruction comprises the following steps:
acquiring input data according to the data address;
and acquiring the delay frequency of the transmitted data according to the transmitting distance and the pulse frequency of the input data.
5. The method of claim 1, wherein combining the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal comprises:
and performing phase-and-phase processing on the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal.
6. The method of claim 1, wherein before the representing the input data by the first register of the first number of bits and the representing the input data at the delay frequency by the second register of the first number of bits, the method further comprises:
and acquiring a first digit according to the target digit, the delay times and the first anti-overflow digit.
7. The method of claim 1, wherein before the representing the value after the target number of bits in the third register by the fourth register of the second number of bits to divide the target value to generate the delayed carrier signal, the method further comprises:
and acquiring a second digit according to the target digit, the delay times and the second anti-overflow digit.
8. A signal transmitting apparatus, the apparatus comprising:
a receiving module configured to acquire input data and a delay frequency in response to receiving a signal transmission instruction;
a processing module configured to represent the input data by a first register of a first number of bits and to represent the input data at the delay frequency by a second register of the first number of bits, the first number of bits being greater than a target number of bits; the target digit is used for representing a digit for subsequently carrying out signal value taking, and the data frequency on the target digit is the same as the frequency of the delayed excitation signal;
representing a value difference value between the first register and the second register through a third register with a first digit, and generating a delay excitation signal according to the value of the target digit in the third register;
representing a value behind a target digit in a third register through a fourth register of a second digit to perform frequency division processing on the target value to generate a delay carrier signal, wherein the second digit is greater than or equal to the target digit; the target value is used for representing the time delay excitation signal;
and the transmitting module is configured to combine the delayed excitation signal and the delayed carrier signal to obtain a delayed focusing signal, and transmit the delayed focusing signal through the phased array transducer.
9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the signal transmission method according to any one of claims 1 to 7.
10. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the signal transmission method according to any one of claims 1 to 7 when executing the computer program.
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