CN110649937A - Ultrasonic wave emission control method, and transmission and reception control method and device - Google Patents
Ultrasonic wave emission control method, and transmission and reception control method and device Download PDFInfo
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- CN110649937A CN110649937A CN201910899536.4A CN201910899536A CN110649937A CN 110649937 A CN110649937 A CN 110649937A CN 201910899536 A CN201910899536 A CN 201910899536A CN 110649937 A CN110649937 A CN 110649937A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/401—Circuits for selecting or indicating operating mode
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B11/00—Transmission systems employing sonic, ultrasonic or infrasonic waves
Abstract
The invention relates to an ultrasonic wave emission control method, a receiving and transmitting control method and a receiving and transmitting control device. The ultrasonic wave emission control device includes a storage unit, a processing unit, and an output unit. The memory unit is configured to store a data structure comprising a body of pulse loops, the body of pulse loops comprising one or more bodies of sub-loops, each body of sub-loops comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, and each transmit row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state. The processing unit is configured to read the data structure and interpret a pulse cycle volume in the data structure as an ultrasound transmit timing sequence. The output unit is configured to output the electric signal corresponding to the ultrasonic emission time sequence.
Description
Technical Field
The present invention relates to an ultrasonic system, and more particularly, to an ultrasonic transmission control method, a transmission/reception control method, an ultrasonic transmission control apparatus, and a transmission/reception control apparatus.
Background
The ultrasonic wave can be used in the fields of distance measurement, flaw detection, imaging and the like. In some applications, it is desirable to implement any form of ultrasound transmission sequence. However, there is a contradiction between the transmission flexibility of the ultrasound sequence and the hardware resource consumption. One conventional emission control method is to allocate a large amount of hardware resources in advance, and set the operating state of each unit at each time of the ultrasonic transducer, thereby implementing an ultrasonic emission sequence of any form. Such an approach guarantees "arbitrariness", but the huge hardware resources result in high costs of the device.
In order to reduce the hardware resources used, a compromise is to preset several operating modes of the ultrasound transducer. Each mode has its own set of transmit sequence structures. Each configuration has a certain flexibility to meet a range of different needs. The requirement of hardware resources is greatly reduced in such a way, but the preset different modes have great limitations and cannot completely describe the possibly required ultrasonic transmitting and receiving sequence.
Disclosure of Invention
The technical problem to be solved by the invention is to provide an ultrasonic wave emission control method, a receiving and transmitting control method and a device, which can realize larger ultrasonic wave emission freedom.
The present invention provides an ultrasonic emission control device, which includes a storage unit, a processing unit and an output unit. The memory unit is configured to store a data structure comprising a body of pulse loops, the body of pulse loops comprising one or more bodies of sub-loops, each body of sub-loops comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, and each transmit row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state. The processing unit is configured to read the data structure and interpret a pulse cycle volume in the data structure as an ultrasound transmit timing sequence. The output unit is configured to output the electric signal corresponding to the ultrasonic emission time sequence.
In an embodiment of the invention, the flag line further comprises a flag bit indicating the start of the sub-loop body.
In one embodiment of the present invention, the body is located after the marker row.
In an embodiment of the invention, the control states include a zero level, a negative level, and a positive level.
In one embodiment of the invention, at least one of the sub-loops has another sub-loop nested within it.
In an embodiment of the invention, the data structure comprises a plurality of pulse cycle bodies, each of which corresponds to one transmit channel.
In an embodiment of the invention, the clock periods of the control states between the plurality of pulse cycle bodies are the same.
In an embodiment of the invention, the storage unit, the processing unit and the output unit are integrated in a programmable gate array, wherein the processing unit is a configurable logic unit.
The invention also provides an ultrasonic wave transceiving control device which comprises a storage unit, a processing unit and an output unit. The memory unit is configured to store a data structure comprising a body of pulse loops, the body of pulse loops comprising one or more bodies of sub-loops, each body of sub-loops comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, at least one receive row, and at least one end row, and each row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state, wherein the control state of the transmit row is a transmit control state, the control state of the receive row is a receive state, and the control state of the end row is a wait state. The processing unit is configured to read the data structure and interpret a pulse cycle body in the data structure as an ultrasound transmit receive timing sequence. The output unit is configured to output the electric signal corresponding to the ultrasonic transceiving time sequence.
In an embodiment of the invention, the flag line further comprises a flag bit indicating the start of the sub-loop body.
In one embodiment of the present invention, the body is located after the marker row.
In one embodiment of the present invention, the control states include a zero level, a negative level, a positive level, and a high impedance state.
In one embodiment of the invention, at least one of the sub-loops has another sub-loop nested within it.
In an embodiment of the invention, the data structure comprises a plurality of pulse cycle bodies, each of which corresponds to one transmit channel.
In an embodiment of the invention, the clock periods of the control states between the plurality of pulse cycle bodies are the same.
The invention also provides an ultrasonic emission control method, which comprises the following steps: a configuration data structure comprising a pulse loop body comprising one or more sub-loop bodies, each sub-loop body comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more rows, and each row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state; reading the data structure and analyzing a pulse cycle body in the data structure into an ultrasonic emission time sequence; and outputting the electric signal corresponding to the ultrasonic emission time sequence.
In an embodiment of the invention, the flag line further comprises a flag bit indicating the start of the sub-loop body.
In one embodiment of the present invention, the body is located after the marker row.
In an embodiment of the invention, the control states include a zero level, a negative level, and a positive level.
In an embodiment of the invention, the data structure comprises a plurality of pulse cycle bodies, each of which corresponds to one transmit channel.
In an embodiment of the invention, the clock periods of the control states between the plurality of pulse cycle bodies are the same.
In an embodiment of the present invention, the method is performed in a programmable gate array.
The invention also provides an ultrasonic receiving and transmitting control method, which comprises the following steps: configuring a data structure, the data structure comprising a pulse loop body comprising one or more sub-loop bodies, each sub-loop body comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, at least one receive row, and at least one end row, and each row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state, wherein the control state of the transmit row is a transmit control state, the control state of the receive row is a receive state, and the control state of the end row is a wait state; reading the data structure and analyzing a pulse cycle body in the data structure into an ultrasonic transceiving time sequence; and outputting the electric signal corresponding to the ultrasonic transceiving time sequence.
The invention also provides an ultrasonic transmitting system, which comprises the ultrasonic transmitting control device; and the ultrasonic transducer is suitable for receiving the electric signal corresponding to the ultrasonic emission time sequence and generating an ultrasonic signal according to the electric signal.
Compared with the prior art, the invention provides enough freedom degree in each sub-cycle body by constructing the pulse cycle body comprising one or more sub-cycle bodies and defines the repetition times of the control state by using the repeated oscillation signals of the ultrasonic wave emission sequence. Therefore, the invention can provide great freedom of ultrasonic emission and obviously reduce hardware resource consumption.
Drawings
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:
fig. 1 illustrates an exemplary pulse cycle body structure.
Fig. 2 illustrates another exemplary pulse cycle body configuration.
Fig. 3 illustrates another exemplary pulse cycle body configuration.
Fig. 4 is a block diagram of an ultrasound system according to an embodiment of the present invention.
Fig. 5 is an implementation example of an ultrasonic wave transmission/reception control apparatus according to an embodiment of the present invention.
Fig. 6 is a flowchart of an ultrasonic transmission/reception control method according to an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described herein, and thus the present invention is not limited to the specific embodiments disclosed below.
As used in this application and the appended claims, the terms "a," "an," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements.
The embodiment of the invention provides a universal ultrasonic wave transmitting pulse cycle body or an ultrasonic wave transceiving pulse cycle body which is used as a basic unit and can theoretically realize an ultrasonic transmitting and receiving sequence in any form. The embodiment of the invention also provides a transmitting control method, a receiving and transmitting control device and a receiving and transmitting control system based on the pulse cycle body. Details of various embodiments of the present invention will be described below.
Control circulation body
The pulse cycle body of the embodiment of the invention is a basic unit and is used for controlling the working state of the ultrasonic transducer. Each pulse cycle volume may include one or more sub-cycle volumes, which may be arranged in a time sequence according to the sequence of ultrasound wave transmissions. It is to be understood, however, that this sequence is for simplicity of implementation only and is not to be construed as a limitation of the present invention. Other sequences of the sub-loop bodies are possible when time stamps or sequence numbers representing time stamps are added to each sub-loop body. Each sub-loop body includes a row of tokens and a body that is recyclable. The body may include one or more lines of data. The tag line may include a first field and a second field. The first field may be used to indicate the number of cycles of the body. It is known through the first field that the contents in the body will be executed several times. The second field may be used to indicate the number of rows of the body. The content of the body can thus be determined from the sub-loop body by means of the second field. In one or more rows of the body, each row may include a third field and a fourth field. The third field is used to indicate the control status. This control state is, for example, a control state for the ultrasonic transducer. The fourth field is used to indicate the number of cycles of the control state. Here, each control state may have a preset clock period, and thus the duration of this control state may be determined in combination with the number of cycles and the clock period.
In the above description, "row" implies a constraint on the pulse cycle body as a data structure, in unit length. Specifically, since the memory used to store or temporarily maintain the pulse cycle body has a bit width limitation, the subcycles in the pulse cycle body are divided into a plurality of rows, including a flag row and a row in the body. However, when the data structure is not stored in memory, but transferred between different bodies, it has no typical line, but different segments that extend in time. In the context of the present invention, for ease of description, a "row" is used to refer collectively to the basic unit of the sub-loop body as it is stored and transferred.
Fig. 1 illustrates an exemplary pulse cycle body structure.
As shown in fig. 1, the pulse cycle body 100a may include a sub-cycle body 110. The sub-loop body 110 includes a label line 111 and a body 112. The body 112 may be located behind the label line 111. The body 112 includes a plurality of transmission rows 112 a. The rows, including the label row 111, may have the same bit width. This bit width may be determined by the bit width of the memory used to store the pulse cycle body. In one example, the bit width may be, for example, 36bits (bits). The first 3 bits of each row may be used to indicate a status or flag. The next 29 bits may be used to indicate the number of cycles. The last 4 bits are unused. Taking the flag row 111 as an example, the first 3 bits D31-D29 are "111" to indicate the start flag of a single sub-loop of the row, and the second 29 bits of data D28-D10 of the row are description information of the sub-loop body, which includes the first fields D28-D10 and the second fields D9-D0. The first fields D28-D10 may be used to indicate the number of cycles of the body 112, between 1-524287. Second fields D9-D0 may be used to indicate the number of rows that body 112 includes, between 1-1023.
Unlike the flag row 111, in each transmission row of the body 112, the first 3 bits D31-D29 are the third field, which represents the control state of the row; the last 29 bits D28-D10 are the fourth field, indicating the number of cycles for this row of control states. Taking the transmitting row 112a as an example, the first 3 bits D31-D29 may be "000", "010", and "100", which respectively represent transmitting control states such as 0 level (high impedance state), "positive level", and "negative level". Here, the absolute values of the positive and negative levels may be equal, for example 100V. The last 29 bits D28-D0 of the transmit row 112a represent the number of cycles of the transmit control state, respectively. The unit time of each cycle is 1/Tclk, and the duration of this transmission control state can be determined by the number of cycles. Assuming a unit time of 120MHz-18.33ns, the cycle number is at least 1 unit and at most 2291 unit time, i.e. 4.474 s. Each transmit row in the body 112 may define a transmit control state that is repeated a number of times. The emission control state may be different between rows. Thus, a combination of multiple emission control states can be defined by several rows. The cycle number of the main body defined by the second field in the mark line is combined, so that the cycle condition of the combination can be defined.
The pulse cycle body of the present embodiment can be used not only for transmission control but also for reception control at the same time.
Fig. 2 illustrates another exemplary pulse cycle body structure 100 b.
Unlike the example of fig. 1, in this example, the body 112 of the subcycle body 110 comprises, in addition to one or more transmit rows 112a, at least one receive row 112b and at least one end (duty off) row 112 c. The receive row 112b may be after the transmit row 112a and the end row 112c may be after the receive row 112 b. The third field of the reception line 112b is "110", which indicates that the line is in the reception state, and the reception data is acquired. The fourth field of the receive row defines the number of cycles of the receive state. The duration of this receive state can be determined by the number of cycles as a receive window. The third field of the end line 112c is "001", indicating that this line is in a wait state. The fourth field of the end row defines the number of cycles of the wait state. The duration of this wait state can be determined by the number of cycles. This latency is used to receive data writes into memory.
The pulse cycle body illustrated in fig. 1 and 2 includes a sub-cycle body. It is to be understood that the pulse cycle body may include a plurality of sub-cycle bodies, which are arranged in sequence. In one embodiment of the invention, the sub-loop bodies may be nested. Fig. 3 illustrates another exemplary pulse cycle body structure 100 c. Referring to fig. 3, the sub-loop body 110a may include a mark line 111, two transmission lines 112a, and a sub-loop body 110 b. The sub-loop body 110b further comprises a label line 111 and a transmit line 112 a. The first labeled row 111, D28-D10, controls the number of cycles for the two fire rows 112a and the sub-cycle block 110b, and the number of rows D9-D0, which are the rows from the next up to the last fire row 112a, are the rows of the sub-cycle block 110 a. In an embodiment of the present invention, the number of layers of the sub-loop body nest may be two layers as in fig. 3, or may be more. Through the nesting of the sub-loop bodies, more complex ultrasonic emission time sequence control can be realized.
The pulse cycle body constructed in this embodiment may correspond to one transmission channel. Multiple pulse cycle volumes may be stored in the electronic device for ultrasonic transmission of multiple transmit channels. When there are multiple pulse cycle bodies, the content may or may not be consistent between the pulse cycle bodies, however the clock period of the control state is the same.
Further details of this example may be found in reference to the foregoing description and are not further described herein. It should be noted that the bit width of the pulse cycle body, the number of bits of each field, and the values are only examples. It is well understood by those skilled in the art that these parameters may take other values.
The pulse cycle body of the present embodiment provides great flexibility for state control. Meanwhile, the structure of the ultrasonic wave generator considers the characteristic of the ultrasonic wave as a repeated oscillation signal, defines the control state, the state cycle number and the cycle number, and greatly reduces the scale of a data structure, thereby obviously reducing the waste of hardware resources and the use difficulty.
Ultrasonic wave emission control device and emission system
Fig. 3 is a block diagram of an ultrasonic transmission system according to an embodiment of the present invention. Referring to fig. 3, the ultrasonic transmission system 200 of the present embodiment may include an ultrasonic transmission control device 210 and an ultrasonic transducer 220. The ultrasonic wave emission control device 210 may include an input unit 211, a storage unit 212, a processing unit 213, and an output unit 214. The input unit 211 is configured to acquire a data structure including a pulse cycle body. For example, the input unit 211 may obtain the pulse frame from the upper computer 10 of the ultrasound transmission system 200, and parse the obtained pulse cycle body.
Table 1 below shows an exemplary transmit pulse frame structure.
TABLE 1
In table 1, the second column is data of a frame. As shown in Table 1, the fire pulse frame may include a frame header, a channel enable identification mask, and a plurality of frames. Each frame may include a frame ID, a frame length, and channel frame data. The channel enable id mask 320 may be data with 4 × 32 ═ 128 bits, which respectively corresponds to the enabling conditions of 128 channels. The frame ID may take on values between 1-128 to indicate which channel of data. The frame length may take on values between N and [1-512], indicating a memory cell corresponding to 18 kB. The channel frame data is sequence data of N x 32bits, and the data can be analyzed and stored as a pulse cycle body.
When the ultrasonic wave transmission system includes a plurality of transmission channels, the input unit 211 may update the enable information of all the transmission channels and may update the pulse cycle volume data of all the channels. The process of the ultrasonic wave emission control device 210 acquiring the pulse cycle body may be taken as one example of the configuration of the pulse cycle body thereof. Here, the legitimacy of the pulse cycle volume data is ensured by the host computer 10, and an illegal pulse design may bring an uncertain execution result.
As mentioned above, the storage unit 212 is configured to store a data structure including a pulse loop body. Here, the data structure may be the example described with reference to fig. 1, fig. 2, or fig. 3 in the foregoing embodiment, and may also be other data structures generated according to a variation of these examples. The pulse cycle body is described in detail above and will not be further described here. Here, the storage unit 212 may be a volatile memory that temporarily stores a data structure only when the ultrasonic wave transmission control device 210 is operated. The storage unit 212 may also be a non-volatile memory that permanently stores data structures after the ultrasound transmission control device 210 is deactivated.
The processing unit 213 is configured to read the aforementioned data structure and interpret the body of the pulse cycle in the data structure as an ultrasound transmit timing or an ultrasound transmit/receive timing, so as to be suitable for provision to the ultrasound transducer 220.
It will be appreciated that the complete part of the pulse cycle body may not be stored in the storage unit 212 at the same time, but instead one part is stored and processed by the processing unit 213 before another part is stored.
The output unit 214 is configured to convert the ultrasonic transmission timing into a suitable electric signal and output the signal to the ultrasonic transducer 220 to control the transmission of the latter. When a receiving function is required, the output unit 214 is configured to convert the ultrasound transceiving timing into a suitable electrical signal and output the signal to the ultrasound transducer 220 to control the transmission and reception of the latter. In some embodiments, the input unit 211 and the output unit 214 may be integrated together.
The ultrasonic wave emission control device 210 of the embodiment of the present invention is suitably implemented in a programmable gate array (FPGA). Fig. 5 is an implementation example of an ultrasonic wave emission control apparatus according to an embodiment of the present invention. Referring to fig. 5, FPGA 400 may include an Input Output Block (IOB) 410, a Configurable Logic Block (CLB) 420, a Block Random Access Memory (BRAM) 430, and a Digital Clock Manager (Digital Clock Manager) 440. The foregoing input unit 211 and output unit 214 may be implemented in IOB 410, memory unit 212 may be implemented in BRAM 330, and processing unit 212 may be implemented in CLB 420. DCM340 may provide the clocks needed for operation. The implementation example of fig. 4 is also applicable to the ultrasonic wave transmission/reception control device.
For an ultrasound system, each channel has a corresponding pulse loop body stored in the BRAM 430 pre-assigned to that channel. After the FPGA 400 initializes the allocation of the pulse cycle body memory space of all the channels, the initial content of the pulse cycle body of all the channels is all 0. The FPGA 400 can download the contents of the pulse loop body from a host computer. The download communication updates the enable information for all channels and updates the contents of the pulse cycle body for one or more channels. The FPGA 400 needs to convert the loop body logic in the BRAM 430 to which the channel with the activated enabling state belongs into gate circuit logic of the CLB 420 during execution, and execute the structure defined by the loop body and the time length of each step in real time; if an enabled active channel is encountered, and its dedicated loop body contents are all 0's, the FPGA 400 keeps that channel at a 0 level state all the time during the execution of the other channels. The flag row takes one clock cycle, and the states of D31 and D30 can be defined as 0 level states by itself. That is, there is a 0 state of one clock cycle at the entry into the subcycle body.
Since the sampled data of the receiving window also needs to occupy the resource of the BRAM 430 for the pulse cycle body with the receiving state, the duration of the receiving window needs to be designed reasonably. The receive state is followed by a wait state (duty off) for waiting for the received data to be written from BRAM 430 into an external memory (not shown). Because the amount of received data is large, the external memory of the FPGA 400 can play a role in buffering the received data and uploading the data to an upper computer. The waiting time may be determined by the following equation:
trx is the time length of a receiving window, and the unit is mus; SampleRate is the sampling rate; margin is a Margin multiple, and is taken as 2.
In one example, BRAM 430 is configured such that one channel uses 36bits × 512 — 18kB, and only 32bits of 36bits of bit width are actually used, and the other 4 bits are not used. The total number of rows is 512 rows. The bit width may be 32bits at the time of transmission.
Table 2 below is an example of a pulse cycle body for one channel.
TABLE 2
As shown in Table 2, line 1 is an explanation, beginning with line 2 is the loop body content. Line 2 is the label line for the first sub-loop body. Lines 3-4 are the main body of the first sub-loop body. Line 5 is the flag line for the second sub-loop body, and lines 6-10 are the body for the second sub-loop body. In Table 2, columns 1-4 are the control states of the circulators, and columns 1-3 are the control states of the subcyclers. For the tag row, column 4 is the number of cycles of the sub-loop body, and column 5 is the number of subsequent rows of the sub-loop body. For a row within the body, such as a transmit row or a receive row, columns 4 and 5 are merged together to represent the number of cycles for that row. For example, the valid data of the loop body is 32bits, and the number of bits actually filled is 36 bits. In Table 2, column 6 is the machine code from columns 1-5 above, and column 7 is the comment explaining the meaning of the current row.
Watch with watchIn 2, assume that the main frequency TCLK and one clock controlling the transmitting state of the ultrasonic transducer by the FPGA are 120MHz and 120MHz respectively-1＝8.333ns。
Ultrasonic wave emission control method and transmission/reception control method
Fig. 6 is a flowchart of an ultrasonic wave emission control method according to an embodiment of the present invention. Referring to fig. 5, the method for controlling ultrasonic wave emission of the present embodiment may include the steps of:
at step 501, a data structure is configured. The data structure may include a pulse loop body including one or more sub-loop bodies, each sub-loop body including a flag row and a body, the flag row including a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body including one or more transmit rows, and each transmit row including a third field indicating a control state and a fourth field indicating a number of cycles of the control state. For more details of the pulse cycle body, reference is made to the foregoing description and will not be further described herein.
Taking fig. 5 as an example, the ultrasonic wave transmission control device 200 receives the data structure or a part thereof from the host computer 10 and temporarily or permanently stores it in the storage unit 212.
At step 502, the data structure is read and the pulse cycle volume in the data structure is parsed into ultrasound transmit timing.
Taking fig. 3 as an example, the processing unit 213 reads the data structure from the storage unit 212 and analyzes the pulse cycle body therein as the ultrasonic emission timing. An example of ultrasound transmission timing is shown in table 1.
In step 503, an electrical signal corresponding to the ultrasound transmission timing sequence is output.
Taking fig. 5 as an example, the processing unit 213 converts the ultrasonic emission timing into a corresponding electrical signal through the output unit 214 and outputs the electrical signal to the ultrasonic transducer 220.
The flow of the ultrasonic transmission/reception control method is similar, except that the output to the ultrasonic transducer 220 includes receiving an electric signal corresponding to the ultrasonic transmission/reception timing of the process control.
The order of processing elements and sequences, the use of alphanumeric characters, or other designations in the present application is not intended to limit the order of the processes and methods in the present application, unless otherwise specified in the claims. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein.
This application uses specific words to describe embodiments of the application. Reference throughout this specification to "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with at least one embodiment of the present application is included in at least one embodiment of the present application. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, some features, structures, or characteristics of one or more embodiments of the present application may be combined as appropriate.
Aspects of the methods and systems of the present application may be performed entirely by hardware, entirely by software (including firmware, resident software, micro-code, etc.), or by a combination of hardware and software. The above hardware or software may be referred to as "data block," module, "" engine, "" unit, "" component, "or" system. The processor may be one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), digital signal processing devices (DAPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or a combination thereof. Furthermore, aspects of the present application may be represented as a computer product, including computer readable program code, embodied in one or more computer readable media. For example, computer-readable media can include but are not limited to magnetic storage devices (e.g., hard disk, floppy disk, magnetic strips … …), optical disks (e.g., Compact Disk (CD), Digital Versatile Disk (DVD) … …), smart cards, and flash memory devices (e.g., card, stick, key drive … …).
The computer readable medium may comprise a propagated data signal with the computer program code embodied therein, for example, on a baseband or as part of a carrier wave. The propagated signal may take any of a variety of forms, including electromagnetic, optical, and the like, or any suitable combination. The computer readable medium can be any computer readable medium that can communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device. Program code on a computer readable medium may be propagated over any suitable medium, including radio, electrical cable, fiber optic cable, radio frequency signals, or the like, or any combination of the preceding.
Additionally, the order in which elements and sequences of the processes described herein are processed, the use of alphanumeric characters, or the use of other designations, is not intended to limit the order of the processes and methods described herein, unless explicitly claimed. While various presently contemplated embodiments of the invention have been discussed in the foregoing disclosure by way of example, it is to be understood that such detail is solely for that purpose and that the appended claims are not limited to the disclosed embodiments, but, on the contrary, are intended to cover all modifications and equivalent arrangements that are within the spirit and scope of the embodiments herein. For example, although the system components described above may be implemented by hardware devices, they may also be implemented by software-only solutions, such as installing the described system on an existing server or mobile device.
Similarly, it should be noted that in the preceding description of embodiments of the application, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the embodiments. This method of disclosure, however, is not intended to require more features than are expressly recited in the claims. Indeed, the embodiments may be characterized as having less than all of the features of a single embodiment disclosed above.
Numerals describing the number of components, attributes, etc. are used in some embodiments, it being understood that such numerals used in the description of the embodiments are modified in some instances by the use of the modifier "about", "approximately" or "substantially". Unless otherwise indicated, "about", "approximately" or "substantially" indicates that the number allows a variation of ± 20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximations that may vary depending upon the desired properties of the individual embodiments. In some embodiments, the numerical parameter should take into account the specified significant digits and employ a general digit preserving approach. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the range are approximations, in the specific examples, such numerical values are set forth as precisely as possible within the scope of the application.
Although the present invention has been described with reference to the present specific embodiments, it will be appreciated by those skilled in the art that the above embodiments are merely illustrative of the present invention, and various equivalent changes and substitutions may be made without departing from the spirit of the invention, and therefore, it is intended that all changes and modifications to the above embodiments within the spirit and scope of the present invention be covered by the appended claims.
Claims (24)
1. An ultrasonic emission control apparatus comprising:
a storage unit configured to store a data structure, the data structure comprising a body of pulse loops, the body of pulse loops comprising one or more bodies of sub-loops, each body of sub-loops comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, and each transmit row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state;
a processing unit configured to read the data structure and resolve a pulse cycle body in the data structure into an ultrasonic emission time sequence; and
and the output unit is configured to output the electric signal corresponding to the ultrasonic emission time sequence.
2. The ultrasound transmission control device of claim 1, wherein the marker line further comprises a flag bit indicating the start of the subcycle body.
3. The ultrasonic emission control device of claim 1, wherein the body is located behind the marker row.
4. The ultrasonic wave emission control device according to claim 1, wherein the control state includes a zero level, a negative level, and a positive level.
5. The ultrasound transmission control device of claim 1, wherein at least one of the sub-loops has another sub-loop nested therein.
6. The ultrasound transmission control device of claim 1, wherein the data structure includes a plurality of pulse cycle volumes, each of the pulse cycle volumes corresponding to a transmission channel.
7. The ultrasonic wave emission control device according to claim 5, wherein clock cycles of the control states between the plurality of pulse cycle bodies are the same.
8. The ultrasound wave transmission control device according to claim 1, wherein the memory unit, the processing unit and the output unit are integrated in a programmable gate array, wherein the processing unit is a configurable logic unit.
9. An ultrasonic wave transmission/reception control device comprising:
a storage unit configured to store a data structure, the data structure including a pulse loop body including one or more sub loop bodies, each sub loop body including a flag row and a body, the flag row including a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body including one or more transmit rows, at least one receive row, and at least one end row, and each row including a third field indicating a control state and a fourth field indicating a number of cycles of the control state, wherein the control state of the transmit row is a transmit control state, the control state of the receive row is a receive state, and the control state of the end row is a wait state;
the processing unit is configured to read the data structure and analyze a pulse cycle body in the data structure into an ultrasonic transceiving time sequence; and
and the output unit is configured to output the electric signal corresponding to the ultrasonic transceiving time sequence.
10. The ultrasonic transceiver control device of claim 9, wherein the marker line further comprises a flag bit indicating the start of the sub-cycle body.
11. The ultrasonic wave transmission/reception control device according to claim 9, wherein the main body is located behind the marker line.
12. The ultrasonic wave transmission/reception control device according to claim 9, wherein the control states include a zero level, a negative level, a positive level, and a high impedance state.
13. The ultrasonic transmission/reception control device according to claim 9, wherein at least one of the sub-loop bodies has another sub-loop body nested therein.
14. The ultrasound transmit receive control device of claim 9 wherein said data structure comprises a plurality of pulse cycle bodies, each of said pulse cycle bodies corresponding to a transmit channel.
15. The ultrasonic transmission/reception control device according to claim 14, wherein the clock cycles of the control states between the plurality of pulse cycle bodies are the same.
16. An ultrasonic wave emission control method comprising the steps of:
a configuration data structure comprising a pulse loop body comprising one or more sub-loop bodies, each sub-loop body comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more rows, and each row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state;
reading the data structure and analyzing a pulse cycle body in the data structure into an ultrasonic emission time sequence; and
and outputting an electric signal corresponding to the ultrasonic emission time sequence.
17. The ultrasonic wave emission control method of claim 16, wherein the flag line further includes a flag bit indicating the start of the sub-loop body.
18. The ultrasonic wave emission control method according to claim 16, wherein the main body is located behind the marker line.
19. The ultrasonic wave emission control method according to claim 16, wherein the control states include a zero level, a negative level, and a positive level.
20. The ultrasonic wave emission control method of claim 16, wherein the data structure includes a plurality of pulse cycle bodies, each of the pulse cycle bodies corresponding to one of the emission channels.
21. The ultrasonic wave emission control method according to claim 20, wherein the clock cycles of the control states between the plurality of pulse cycle bodies are the same.
22. The ultrasonic wave emission control method according to claim 16, being performed in a programmable gate array.
23. An ultrasonic wave transceiving control method comprises the following steps:
configuring a data structure, the data structure comprising a pulse loop body comprising one or more sub-loop bodies, each sub-loop body comprising a flag row and a body, the flag row comprising a first field indicating a number of cycles of the body and a second field indicating a number of rows of the body, the body comprising one or more transmit rows, at least one receive row, and at least one end row, and each row comprising a third field indicating a control state and a fourth field indicating a number of cycles of the control state, wherein the control state of the transmit row is a transmit control state, the control state of the receive row is a receive state, and the control state of the end row is a wait state;
reading the data structure and analyzing a pulse cycle body in the data structure into an ultrasonic transceiving time sequence; and
and outputting the electric signal corresponding to the ultrasonic receiving and transmitting time sequence.
24. An ultrasonic transmission system comprising:
the ultrasonic emission control device according to any one of claims 1 to 8; and
and the ultrasonic transducer is suitable for receiving the electric signal corresponding to the ultrasonic emission time sequence and generating an ultrasonic signal according to the electric signal.
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| CN201910899536.4A CN110649937B (en) | 2019-09-23 | 2019-09-23 | Ultrasonic wave emission control method, and transmission and reception control method and device |
| PCT/CN2020/116568 WO2021057668A1 (en) | 2019-09-23 | 2020-09-21 | Ultrasonic emission control method, transceiving control method, and device |
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| WO2021057668A1 (en) * | 2019-09-23 | 2021-04-01 | 明格(上海)信息技术有限公司 | Ultrasonic emission control method, transceiving control method, and device |
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