CN113284868A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN113284868A
CN113284868A CN202010104828.7A CN202010104828A CN113284868A CN 113284868 A CN113284868 A CN 113284868A CN 202010104828 A CN202010104828 A CN 202010104828A CN 113284868 A CN113284868 A CN 113284868A
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China
Prior art keywords
substrate
semiconductor element
passivation layer
element according
circuit
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CN202010104828.7A
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Chinese (zh)
Inventor
朱彦瑞
吴金能
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Winbond Electronics Corp
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Winbond Electronics Corp
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Priority to CN202010104828.7A priority Critical patent/CN113284868A/en
Publication of CN113284868A publication Critical patent/CN113284868A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor element, which comprises a substrate, a passivation layer and a connecting piece. The passivation layer is disposed on the substrate. The connecting member is buried in the passivation layer. The interface of the connecting piece contacting with the passivation layer is rugged, thereby improving the structural stability of the connecting piece. A method for fabricating the semiconductor device is also provided.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to a semiconductor element and a manufacturing method thereof.
Background
In recent years, the semiconductor industry has grown rapidly due to the increasing integration of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This increase in integration is mostly due to the continuous reduction of minimum feature sizes, which allows more components to be integrated in a specific area.
In the prior art, the wire and the wire bonding pad under the wire are often pulled off the substrate due to the pulling force of the wire bonding process, which leads to a reduction in yield. Therefore, how to prevent the wire bonding pad from being pulled off the substrate and further increase the yield will become an important issue in the future.
Disclosure of Invention
The invention provides a semiconductor element and a manufacturing method thereof, wherein a connecting piece is embedded in a passivation layer, and an interface between the connecting piece and the passivation layer is uneven, so that the structural stability of the connecting piece is improved.
The invention provides a semiconductor element, which comprises a substrate, a passivation layer and a connecting piece. The passivation layer is disposed on the substrate. The connecting member is buried in the passivation layer. The interface of the connecting piece and the passivation layer is rugged.
The invention provides a semiconductor element, which comprises the following steps. A substrate is provided. A passivation layer is formed on the substrate by a first 3D printing technique. The passivation layer has an opening. The opening has uneven sidewalls. The connector is formed in the opening by a second 3D printing technique.
Based on the above, in the embodiment of the invention, the connecting piece is embedded in the passivation layer, and the interface between the connecting piece and the passivation layer is uneven, so that the structural stability of the connecting piece is improved. In this case, the adhesion between the connector and the substrate is improved, which can prevent the connector from being pulled off the substrate after the bonding process, thereby improving the yield.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIGS. 1A-1C are schematic cross-sectional views illustrating a process flow of manufacturing a semiconductor device according to an embodiment of the invention;
FIGS. 2A-2C are schematic perspective views of various embodiments of the connector shown in FIG. 1C, respectively;
FIG. 3 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention;
fig. 5 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the invention.
Detailed Description
The present invention will be described more fully with reference to the accompanying drawings of the present embodiments. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the following paragraphs will not be repeated.
Fig. 1A to 1C are schematic cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the invention. Fig. 2A-2C are perspective views of various embodiments of the connector shown in fig. 1C, respectively. Referring to fig. 1A, the present embodiment provides a method for manufacturing a semiconductor device, which includes the following steps. First, a substrate 101 is provided. In this embodiment, the substrate 101 may be a silicon substrate. Although it is not shown in fig. 1A that any element is disposed in the substrate 101, the substrate 101 of the present embodiment may have an active element (e.g., a transistor, a diode, etc.), a passive element (e.g., a capacitor, an inductor, a resistor, etc.), or a combination thereof. In other embodiments, the substrate 101 may have, for example, logic elements, memory elements, or a combination thereof therein.
Next, a passivation layer 102 is formed on the substrate 101 by a first 3D printing technique. In an embodiment, the first 3D Printing technique comprises a Jet Printing process, an Aerosol Jet Printing (Aerosol Jet Printing) process, or a combination thereof. Taking the aerosol spray printing process as an example, an aerosol jet deposition head (aerosol jet deposition head) is used to form an annular propagation nozzle consisting of an outer sheath flow (outer sheath flow) and an inner aerosol-laden carrier flow (inner aerosol-laden carrier flow). In the circular aerosol spray process, an aerosol stream of the material to be deposited (aerosol stream) is focused and deposited on the surface to be formed. The above step may be referred to as Maskless Mesoscale Material Deposition (M3D), that is, it may be deposited without the use of a mask.
In the present embodiment, as shown in fig. 1A, the first 3D printing technique includes ejecting insulating ink 204 onto the substrate 101 through a head 202 of the 3D printing apparatus. Thereafter, a curing step is performed to cure the insulating ink 204 into the passivation layer 102. In some embodiments, the curing step comprises a photo-curing step or a thermal curing step. For example, the photo-curing step may be irradiation of light having a wavelength of about 395nm to 405nm, for example, to cure the insulating ink 204 into the passivation layer 102. In one embodiment, the insulating ink 204 includes a photo-curable material, a hydrophobic material, a polymeric material, or a combination thereof. For example, the insulating ink 204 may be Polydimethylsiloxane (PDMS), polyimide, or the like.
After the curing step, the passivation layer 102 has an opening 10 as shown in fig. 1A. The opening 10 has uneven sidewalls. Specifically, in one embodiment, the opening 10 has a main body 12 and a protrusion 14. The protruding portion 14 protrudes from the body portion 12 into the passivation layer 102. In the cross-sectional direction, the protruding portion 14 has an arc surface protruding from the main body portion 12 to the passivation layer 102. The protruding portions 14a, 14b on both sides of each main body portion 12 are arranged to be staggered with each other in the Z direction to form a screw thread shape around the main body portion 12. In some embodiments, the ratio of the height 10h of the opening 10 to the width 14w of the protrusion 14 is 10:4 to 10: 1. That is, the present embodiment intentionally forms the sidewalls of the opening 10 to be rugged, thereby improving the structural stability of the subsequently formed connection 106 (shown in fig. 1C). In an alternative embodiment, since the passivation layer 102 is formed by the first 3D printing technique, the passivation layer 102 is integrally formed and continuously formed along the Z direction. To some extent, the passivation layer 102 may have an increased height and a changed shape of the sidewall of the passivation layer 102 according to actual requirements.
Referring to fig. 1B, an adhesive layer 104 is formed on the bottom surface of the opening 10 by another 3D printing technique. This 3D printing technique involves ejecting a self-assembled monolayer of ink 214 through a nozzle 212 of a 3D printing device into the opening 10. In one embodiment, the adhesive layer 104 may be a self-assembled monolayer, for example. Materials for the self-assembled monolayer include Organosilane based (organic silane based) materials, such as chlorosilane molecules. It is noted that the adhesion layer 104 may be used as a buffer layer to increase adhesion between the subsequently formed connector 106 (shown in fig. 1C) and the substrate 101 and to prevent stress of the subsequent bonding process from damaging the underlying substrate 101 or the devices in the substrate 101. In alternative embodiments, the step of forming the adhesive layer 104 may be omitted.
Referring to fig. 1C, a connection member 106 is formed in the opening 10 by a second 3D printing technique, thereby completing the chip 100. Specifically, a conductive ink 224 is ejected from a nozzle 222 of the 3D printing apparatus onto the adhesive layer 104, and a curing step is performed to form the connecting member 106. In this case, as shown in fig. 1C, the connection member 106 is buried in the passivation layer 102 and formed along the opening 10 such that the interface where the connection member 106 contacts the passivation layer 102 is rugged. In one embodiment, conductive ink 224 includes a plurality of conductive particles. The conductive particles include a plurality of metal nanoparticles, which may be, for example, silver nanoparticles, copper nanoparticles, or a combination thereof. In some embodiments, the connecting member 106 connects the conductive particles tightly together to achieve uniform conduction. Unlike the electroplating process, the conductive particles in the connection 106 of the present embodiment directly contact the passivation layer 102. That is, there is no seed or barrier layer between the connection 106 and the passivation layer 102. In addition, although fig. 1C shows the top surface of the connection member 106 lower than the top surface of the passivation layer 102, the invention is not limited thereto. In other embodiments, the top surface of the connection 106 may be flush with the top surface of the passivation layer 102.
Note that, as shown in fig. 1C, the connecting member 106 includes a main body portion M1 and a protruding portion P1. The body portion M1 has a sidewall perpendicular to the substrate 101. The protruding portion P1 protrudes outward from the side wall of the main body portion M1. In some embodiments, the ratio of the height H of body portion M1 to the width W of protrusion P1 is 10:4 to 10: 1. That is, the present embodiment intentionally forms the interface of the connection member 106 in contact with the passivation layer 102 to be rugged, thereby improving the structural stability of the connection member 106. Specifically, the protrusion P1 surrounds the side wall of the body portion M1 to form a spiral structure, as shown in fig. 2A. However, the invention is not limited thereto, and in another embodiment, the protrusion P2 may include a plurality of ring structures respectively surrounding the sidewall of the main body M1 to form another connecting element 206, as shown in fig. 2B. In other embodiments, the protrusion P3 includes a plurality of protrusion structures to be independently distributed on the sidewall of the main body portion M1 to form other connection members 306, as shown in fig. 2C. The plurality of projection structures may be tapered in cross-section (as in fig. 2C) or arcuate (not shown). The protrusions P1, P2, and P3 shown in fig. 2A to 2C may form an uneven surface in the cross-sectional direction, so as to improve the structural stability of the connectors 106, 206, and 306, and further improve the yield of the connectors 106, 206, and 306 in the subsequent bonding process.
Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the invention. In this embodiment, the semiconductor device of fig. 3 may be a package structure. Referring to fig. 3, the chip 100 (or the substrate 101) in fig. 1C may be electrically connected to the circuit substrate 300 by flip chip bonding. The flip chip bonding method is to connect the chip 100 to the circuit substrate 300 through a plurality of bumps (bump)302 between the circuit substrate 300 and the chip 100. In addition, the underfill (underfill)304 is filled into the space between the circuit substrate 300 and the chip 100 to encapsulate the bumps 302. In this case, the connecting element 106 and the bump 302 contacting each other can electrically connect the circuit board 300 and the chip 100 (or the substrate 101). That is, the connecting member 106 of the present embodiment can be used as a pad in a flip chip bonding process to bear the pressure of the flip chip bonding process. In addition, although only one chip 100 is shown in fig. 3, the invention is not limited thereto. In other embodiments, the number and types of the chips 100 may be adjusted as required.
Fig. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the invention. In this embodiment, the semiconductor element of fig. 4 may be a package structure. Referring to fig. 4, the chip 100 (or the substrate 101) in fig. 1C may be electrically connected to the circuit substrate 300 by wire bonding. The wire bonding method is to connect the circuit substrate 300 and the chip 100 through a plurality of conductive wires 312. In addition, the upper surfaces of the chip 100 and the circuit substrate 300 are covered by an encapsulating body (encapsulating body) 314, and the conductive lines 312 are encapsulated. In this case, the connecting member 106 and the conductive line 312 contacting each other may electrically connect the circuit board 300 and the chip 100 (or the substrate 101). It should be noted that, since the interface between the connecting element 106 and the passivation layer 102 is uneven, the structural stability of the connecting element 106 can be improved, so as to prevent the connecting element 106 from being pulled off the substrate 101 due to the pulling force of the wire bonding process, thereby improving the yield. That is, the connecting element 106 of the present embodiment can be used as a wire bonding pad in a wire bonding process to bear the pulling force of the wire bonding process.
In addition to the connection element 106 serving as a pad in the bonding process, in an alternative embodiment, the connection element 106 may also serve as a via (conductive via) in the circuit structure. For a detailed description, refer to the following paragraphs.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the invention. Here, the line layer shown in the embodiment may be a redistribution layer (RDL), but the invention is not limited thereto. In other embodiments, the circuit layer may also be an interconnect in a back-end-of-line process, a circuit structure in a circuit board, or the like.
Referring to fig. 5, the semiconductor device 500 of the third embodiment includes a substrate 101, a pad 112, a dielectric layer 114, a first circuit layer 116, a passivation layer 102, an adhesive layer 104, a connector 106, and a second circuit layer 118.
In detail, the pads 112 are disposed on the substrate 101. In one embodiment, the material of the pad 112 includes a metal material, such as copper, aluminum, gold, silver, nickel, palladium, or a combination thereof. The dielectric layer 114 covers the sidewalls and a portion of the top surface of the pad 112 and exposes another portion of the top surface 112t of the pad 112. In one embodiment, the material of the dielectric layer 114 includes a dielectric material, which may be, for example, silicon oxide, silicon nitride, silicon oxynitride, polyimide, or a combination thereof. In another embodiment, the dielectric layer 114 may be a single layer structure, a double layer structure, or a multi-layer structure. The first circuit layer 116 covers a portion of the top surface 112t of the pad 112 and extends from the pad 112 to cover a portion of the top surface of the dielectric layer 114. In one embodiment, the first circuit layer 116 includes a plurality of conductive particles in contact with each other, and may be formed by a 3D printing technique. The conductive particles include a plurality of metal nanoparticles, which may be, for example, silver nanoparticles, copper nanoparticles, or a combination thereof.
As shown in fig. 5, the passivation layer 102 is disposed on the first circuit layer 116 and covers a portion of the top surface of the dielectric layer 114 and a portion of the top surface of the first circuit layer 116. The connection member 106 is buried in the passivation layer 102 and has an uneven sidewall. The adhesive layer 104 may be selectively disposed between the connector 106 and the first circuit layer 116 to increase the adhesion between the connector 106 and the first circuit layer 116. In addition, the first circuit layer 116 is disposed between the connecting member 106 and the substrate 101, and the connecting member 106 and the pad 112 are offset (offset). In this case, the electrical signal generated by the device under the pad 112 can be transmitted to the connector 106 through the pad 112 and the first circuit layer 116. The materials and formation methods of the passivation layer 102, the adhesion layer 104 and the connecting element 106 are described in detail in the above paragraphs, and thus are not described herein again.
As shown in fig. 5, the second circuit layer 118 is disposed on the passivation layer 102 and the connection member 106. In one embodiment, the second circuit layer 118 includes a plurality of conductive particles in contact with each other, and may be formed in a 3D printing technique. The conductive particles include a plurality of metal nanoparticles, which may be, for example, silver nanoparticles, copper nanoparticles, or a combination thereof. In this case, the connecting member 106 can be used as a via hole to electrically connect the first circuit layer 116 and the second circuit layer 118. In some embodiments, since the connection member 106 and the second circuit layer 118 are both formed by a 3D printing technology, the connection member 106 and the second circuit layer 118 are electrically connected by a plurality of conductive particles contacting each other. That is, the connector 106 is in direct contact with the second circuit layer 118 without a distinct interface therebetween. In addition, in the present embodiment, the interface between the connection member 106 and the passivation layer 102 is uneven, which can improve the structural stability of the connection member 106 and increase the mechanical strength of the semiconductor device 500.
In summary, the connecting member is embedded in the passivation layer, and the interface between the connecting member and the passivation layer is uneven, so that the structural stability of the connecting member is improved, and the yield of the connecting member in the subsequent bonding process is improved. In addition, the adhesion layer can be selectively arranged between the connecting piece and the substrate so as to improve the adhesion between the connecting piece and the substrate, further avoid the stress of the bonding process from damaging elements in the substrate and prevent the connecting piece from being pulled out of the substrate. In addition, the connecting piece can be formed by a 3D printing technology, so that the connecting piece is integrally formed, and the mechanical strength of the connecting piece is further increased.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims (20)

1. A semiconductor component, comprising:
a passivation layer disposed on the substrate; and
a connection member buried in the passivation layer, wherein an interface of the connection member contacting the passivation layer is rugged.
2. The semiconductor element according to claim 1, wherein the connection member comprises:
a body portion having a sidewall perpendicular to the substrate; and
a protrusion protruding outward from the sidewall of the body portion.
3. The semiconductor element according to claim 2, wherein the protruding portion surrounds the side wall of the main body portion to constitute a spiral structure.
4. The semiconductor element according to claim 2, wherein the protruding portion includes a plurality of ring-shaped structures to surround the side walls of the main body portion, respectively.
5. The semiconductor element according to claim 2, wherein the protruding portion includes a plurality of protruding structures so as to be distributed on the side wall of the body portion.
6. The semiconductor element according to claim 2, wherein a ratio of a height of the body portion to a width of the protruding portion is 10:4 to 10: 1.
7. The semiconductor device as claimed in claim 1, further comprising a circuit substrate, wherein the substrate is connected to the circuit substrate by wire bonding or flip chip bonding, and the connecting member electrically connects the substrate and the circuit substrate.
8. The semiconductor element according to claim 1, further comprising:
a first circuit layer disposed between the substrate and the connector; and
and the second circuit layer is configured on the connecting piece, wherein the connecting piece is electrically connected with the first circuit layer and the second circuit layer.
9. The semiconductor device as claimed in claim 1, further comprising an adhesive layer disposed between the connector and the substrate.
10. The semiconductor element according to claim 1, wherein the connection member is constituted by a plurality of conductive particles which are in contact with each other.
11. The semiconductor component of claim 10, wherein the plurality of conductive particles comprises a plurality of metal nanoparticles comprising silver nanoparticles, copper nanoparticles, or a combination thereof.
12. A method for manufacturing a semiconductor device includes:
providing a substrate;
forming a passivation layer on the substrate by a first 3D printing technique, wherein the passivation layer has an opening with rugged sidewalls; and
forming a connector in the opening by a second 3D printing technique.
13. The method for manufacturing a semiconductor element according to claim 12, wherein the opening has a main body portion and a protruding portion, the protruding portion protruding from the main body portion into the passivation layer.
14. The method for manufacturing a semiconductor element, according to claim 13, wherein a ratio of a height of the opening to a width of the protruding portion is 10:4 to 10: 1.
15. The method of manufacturing a semiconductor element according to claim 12, wherein forming the connection member by the second 3D printing technique includes using a conductive ink including a plurality of metal nanoparticles including silver nanoparticles, copper nanoparticles, or a combination thereof.
16. The method for manufacturing a semiconductor element according to claim 15, wherein the plurality of metal nanoparticles directly contact the passivation layer.
17. The manufacturing method of a semiconductor element according to claim 12, wherein a material of the passivation layer comprises a hydrophobic material.
18. The method as claimed in claim 12, further comprising wire bonding or flip chip bonding the substrate to a circuit substrate, wherein the connecting member electrically connects the substrate and the circuit substrate.
19. The manufacturing method of a semiconductor element according to claim 12, further comprising:
forming a first circuit layer between the substrate and the connector; and
and forming a second circuit layer on the connecting piece, wherein the connecting piece is electrically connected with the first circuit layer and the second circuit layer.
20. The method for manufacturing a semiconductor device according to claim 12, further comprising forming an adhesive layer between the connector and the substrate.
CN202010104828.7A 2020-02-20 2020-02-20 Semiconductor device and method for manufacturing the same Pending CN113284868A (en)

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US20140027922A1 (en) * 2012-07-24 2014-01-30 Invensas Corporation Via in substrate with deposited layer
TW201626539A (en) * 2014-10-15 2016-07-16 台灣積體電路製造股份有限公司 Semiconductor package structure and manufacturing method thereof
CN106206409A (en) * 2015-05-08 2016-12-07 华邦电子股份有限公司 Stacking electronic installation and manufacture method thereof
CN107846790A (en) * 2016-09-19 2018-03-27 苏州纳格光电科技有限公司 The preparation method of multi-layer flexible circuit board

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120308332A1 (en) * 2011-06-02 2012-12-06 A. Raymond Et Cie Spiral fastener
US20140027922A1 (en) * 2012-07-24 2014-01-30 Invensas Corporation Via in substrate with deposited layer
TW201626539A (en) * 2014-10-15 2016-07-16 台灣積體電路製造股份有限公司 Semiconductor package structure and manufacturing method thereof
CN106206409A (en) * 2015-05-08 2016-12-07 华邦电子股份有限公司 Stacking electronic installation and manufacture method thereof
CN107846790A (en) * 2016-09-19 2018-03-27 苏州纳格光电科技有限公司 The preparation method of multi-layer flexible circuit board

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