CN113271567A

CN113271567A - Information sending and receiving method, device and terminal

Info

Publication number: CN113271567A
Application number: CN202010093721.7A
Authority: CN
Inventors: 任晓涛; 赵锐
Original assignee: Datang Mobile Communications Equipment Co Ltd
Current assignee: Datang Mobile Communications Equipment Co Ltd
Priority date: 2020-02-14
Filing date: 2020-02-14
Publication date: 2021-08-17
Also published as: TWI820369B; TW202131652A; WO2021159827A1

Abstract

The invention discloses an information sending and receiving method, a device and a terminal, wherein the sending method comprises the following steps: sending a through link synchronization signal block S-SSB, wherein the S-SSB comprises a physical through link broadcast channel PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined based on at least one of the first information and the second information. The terminal of the embodiment of the invention determines the scrambling sequence of the PSBCH according to at least one of the first information and the second information, and scrambles the PSBCH by adopting the corresponding scrambling sequence, thereby reducing the mutual interference between different PSBCH channels in a direct link, improving the decoding success rate of the PSBCH and reducing the synchronous time delay of the terminal.

Description

Information sending and receiving method, device and terminal

Technical Field

The present invention relates to the field of communications technologies, and in particular, to an information sending method, an information receiving method, an information sending device, an information receiving device, and a terminal.

Background

In Long Time Evolution (LTE) Vehicle and Everything (V2X) technology, a direct link (Sidelink, or called side link, etc.)At most 3 synchronization subframes, or User Equipment (UE), are configured every 160ms, and the transmission and reception of the Sidelink synchronization signal and the broadcast information are performed on the synchronization subframes, and the UE does not perform beam scanning when transmitting and receiving the synchronization signal and the broadcast information on the synchronization subframes. With the development of car networking technology, in the fifth generation (5)^thGeneration, 5G) New Radio (NR) system, in order to meet the requirements of New application scenarios, the 5G NR supports a larger bandwidth, flexible subcarrier spacing configuration, and transmission of Synchronization signals and broadcast information in the form of Synchronization Signal and broadcast channel Block (SSB) beam scanning or beam repetition. This brings new challenges to the design of the NR V2X physical layer structure, and the transmission and reception of the synchronization signals and broadcast information performed by the UE on the synchronization subframe need to be redesigned, and flexible subcarrier spacing configuration and SSB beam scanning or beam repetition mechanism need to be introduced to meet the requirement of NR V2X. However, after a direct link Synchronization Signal and PBCH Block (S-SSB) is introduced into NR V2X, how to scramble a Physical direct link Broadcast Channel (PSBCH) transmitted on a direct link becomes an urgent problem to be solved.

Disclosure of Invention

The embodiment of the invention provides an information sending and receiving method, an information sending and receiving device and a terminal, which can solve the scrambling problem of PSBCH in an NR V2X system.

The embodiment of the invention provides the following technical scheme:

the embodiment of the invention provides an information sending method which is applied to a terminal and comprises the following steps:

sending a through link synchronization signal block, S-SSB, the S-SSB comprising a physical through link broadcast channel, PSBCH, scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block;

at least some bits of the slot number.

Optionally, at least one of the first information and the second information is carried by a PSBCH payload, or at least one of the first information and the second information is carried by a PSBCH demodulation reference signal, DMRS.

Optionally, the information sending method further includes:

and initializing the scrambling sequence according to the through link synchronous signal identification number SL-SSID.

Optionally, the PSBCH is scrambled by a scrambling sequence, including:

scrambling the PSBCH through a first scrambling sequence;

alternatively, the first and second electrodes may be,

scrambling the PSBCH through a second scrambling sequence;

alternatively, the first and second electrodes may be,

scrambling the PSBCH through a first scrambling sequence, and scrambling the PSBCH through a second scrambling sequence;

wherein the first scrambling sequence is determined based on the first information and the second scrambling sequence is determined based on the second information.

Optionally, the PSBCH is scrambled by a first scrambling sequence, including:

scrambling the PSBCH load bit sequence through a first scrambling sequence; the PSBCH payload bit sequence is generated after the payload in the PSBCH is interleaved.

Optionally, the PSBCH is scrambled by a second scrambling sequence, including:

scrambling the PSBCH sequence through a second scrambling sequence; wherein, the PSBCH sequence is generated after the load in the PSBCH is interleaved and rate-matched.

Optionally, the PSBCH is scrambled by a first scrambling sequence, including:

and selecting one sequence from the first candidate sequence set as a first scrambling sequence according to the first information, and scrambling the PSBCH by the first scrambling sequence.

Optionally, the number N1 of candidate sequences in the first candidate sequence set is 2^M1And M1 is the number of bits in the first information.

Optionally, each sequence in the first set of candidate sequences is a part of the first sequence, or a subsequence of the first sequence.

Optionally, the PSBCH is scrambled by a second scrambling sequence, including:

and selecting one sequence from the second candidate sequence set as a second scrambling sequence according to the second information, and scrambling the PSBCH by the second scrambling sequence.

Optionally, the number N2 of candidate sequences in the second candidate sequence set is 2^M2And M2 is the number of bits in the second information.

Optionally, each sequence in the second set of candidate sequences is a part of the second sequence, or a subsequence of the second sequence.

Optionally, at least some bits of the DFN are 2 nd and 3 rd bits of a least significant bit of the DFN.

Optionally, at least some of the bits of the S-SSB index number are the 2 or 3 least significant bits of the S-SSB index number.

Optionally, at least a portion of the bits of the slot number are the 2 or 3 least significant bits of the slot number.

Optionally, the timeslot number is a timeslot number within a system radio frame or a direct radio frame.

Optionally, in the process of scrambling the PSBCH, at least one of at least partial bits of the DFN, at least partial bits of the S-SSB index number, and at least partial bits of the slot number in the first information is not scrambled.

The embodiment of the invention also provides an information receiving method which is applied to a terminal and comprises the following steps:

receiving a through link synchronization signal block S-SSB, the S-SSB comprising a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

Optionally, the information receiving method further includes:

and descrambling the PSBCH in the S-SSB through the scrambling sequence.

An embodiment of the present invention further provides a terminal, including: the transceiver, the processor, the memorizer, store the procedure that the processor can be run on the memorizer; the processor controls the transceiver to implement when executing the program: transmitting a through link synchronization signal block S-SSB, the S-SSB including a PSBCH scrambled by a scrambling sequence; the scrambling sequence is determined according to at least one of first information and second information, and the at least one of the first information and the second information comprises at least one of the following information:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

Optionally, the processor is configured to: and initializing the scrambling sequence according to the through link synchronous signal identification number SL-SSID.

Optionally, the processor is specifically configured to: scrambling the PSBCH through a first scrambling sequence;

or, scrambling the PSBCH through a second scrambling sequence;

or, the PSBCH is scrambled through the first scrambling sequence, and then the PSBCH is scrambled through the second scrambling sequence;

Optionally, the processor is configured to: scrambling the PSBCH load bit sequence through a first scrambling sequence; the PSBCH payload bit sequence is generated after the payload in the PSBCH is interleaved.

Optionally, the processor is configured to: scrambling the PSBCH sequence through a second scrambling sequence; wherein, the PSBCH sequence is generated after the load in the PSBCH is interleaved and rate-matched.

Optionally, the processor is specifically configured to: selecting a sequence from the first set of candidate sequences as a first scrambling sequence based on the first information,

the PSBCH is scrambled by a first scrambling sequence.

Optionally, the processor is specifically configured to:

The embodiment of the invention also provides an information sending device, which is applied to a terminal and comprises:

a sending module, configured to send a direct link synchronization signal block S-SSB, where the S-SSB includes a physical direct link broadcast channel PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

An embodiment of the present invention further provides a terminal, including: the transceiver, the processor, the memorizer, store the procedure that the processor can be run on the memorizer; the processor controls the transceiver to implement when executing the program: receiving a through link synchronization signal block S-SSB, the S-SSB comprising a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

Optionally, the processor is configured to: and descrambling the PSBCH in the S-SSB through the scrambling sequence.

The embodiment of the invention also provides an information receiving device, which is applied to a terminal and comprises:

the receiving module is used for receiving a through link synchronization signal block S-SSB, and the S-SSB comprises a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

Embodiments of the present invention also provide a processor-readable storage medium storing processor-executable instructions for causing a processor to perform the information transmitting method as described above or to perform the information receiving method as described above.

The embodiment of the invention has the beneficial effects that:

in the above embodiment of the present invention, the scrambling sequence of the PSBCH is determined according to at least one of the first information and the second information, and the PSBCH is scrambled by using the corresponding scrambling sequence, so that mutual interference between different PSBCH channels in the direct link can be reduced, the decoding success rate of the PSBCH is improved, and thus the synchronization delay of the terminal can be reduced.

Drawings

Fig. 1 is a flowchart illustrating an information sending method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram illustrating a procedure of scrambling PSBCH by a first scrambling sequence according to an embodiment of the present invention;

FIG. 3 is a flowchart illustrating a PSBCH scrambling process by a first scrambling sequence and a PSBCH scrambling process by a second scrambling sequence according to an embodiment of the present invention;

FIG. 4 is a schematic diagram illustrating a procedure of scrambling PSBCH by a second scrambling sequence according to an embodiment of the present invention;

fig. 5 is a block diagram of a terminal at a transmitting side of an embodiment of the present invention;

fig. 6 is a schematic block diagram of a terminal on the transmitting side according to an embodiment of the present invention;

fig. 7 is a flowchart illustrating an information receiving method according to an embodiment of the present invention;

fig. 8 is a block diagram of a terminal of a receiving side of an embodiment of the present invention;

fig. 9 is a schematic block diagram of a receiving-side terminal according to an embodiment of the present invention.

Detailed Description

Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The terms "a", "an", "the" and the like are all generic and used to denote the same type of object, not to denote the number of objects. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. In the description and in the claims "and/or" means at least one of the connected objects.

In the 5G NR V2X system, terminals communicate directly with each other using a PC5 port (Sidelink). Before the service data transmission, synchronization is established between two terminals which need to communicate first at port PC5 (Sidelink). The method for establishing synchronization is that one terminal A sends synchronization and broadcast signals, the other terminal B receives the synchronization and broadcast signals sent by the terminal A, once the terminal B successfully receives and demodulates, the two terminals can establish synchronization, and preparation is made for the next step of direct communication. Since the 5G NR supports a larger bandwidth, flexible subcarrier spacing configuration, and the synchronization signal and broadcast information are transmitted in the form of SSB beam scanning or beam repetition, which brings new challenges to the design of the physical layer structure of NR V2X, the original UE needs to redesign the transmission and reception of the synchronization signal and broadcast information on the synchronization subframe, and needs to introduce a flexible subcarrier spacing configuration and SSB beam scanning or beam repetition mechanism to meet the requirement of NR V2X. After the S-SSB is introduced into the NR V2X, how to scramble the PSBCH becomes an urgent problem to be solved. The embodiment of the invention provides a PSBCH scrambling method to solve the PSBCH scrambling problem. The following examples are provided to further illustrate the invention.

First embodiment

As shown in fig. 1, an embodiment of the present invention provides an information sending method, which is applied to a terminal, and the method includes, but is not limited to the following steps:

step 11: transmitting a through-link synchronization signal block, S-SSB, the S-SSB containing a physical through-link broadcast channel, PSBCH, scrambled by a scrambling sequence. Wherein the scrambling sequence is determined according to at least one of the first information and the second information.

Optionally, at least one of the first information and the second information comprises at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number. The first scrambling sequence and the second scrambling sequence are related to target information carried by the S-SSB (e.g., PSBCH), such as timing information in the PSBCH, and optionally, the scrambling sequences may be determined according to the timing information carried in the PSBCH. It is worth pointing out that the information carried in PSBCH, in addition to timing information, may also include: time domain configuration information (such as subframe configuration information), frequency domain configuration information (such as bandwidth information, subcarrier spacing information, and the like), coverage indication information (such as synchronization cluster information), and the like. That is, the first information and/or the second information may be information carried by the S-SSB, for example, at least one of the first information and the second information is carried by a PSBCH payload, or at least one of the first information and the second information is carried by a PSBCH Demodulation Reference Signal (DMRS). Here, a first scrambling sequence determined according to the first information is used for a first scrambling process of the PSBCH, a second scrambling sequence determined according to the second information is used for a second scrambling process of the PSBCH, and the first scrambling process and the second scrambling process are different scrambling processes, for example, the first scrambling is scrambling after interleaving of a PSBCH payload bit sequence, and the second scrambling is scrambling after rate matching of the PSBCH sequence.

In NR V2X, the PSBCH is contained in the S-SSB, that is, the S-SSB contains the PSBCH, and step 12 can also be understood as transmitting the S-SSB containing the scrambled PSBCH.

Thus, the terminal uses the scrambling sequence to carry out the scrambling process on the PSBCH, the S-SSB comprises the PSBCH, and the S-SSB is sent after the scrambling is finished, so that the sending of the PSBCH can be finished. Because the scrambling sequence is determined according to the information carried in the S-SSB, the mutual interference between different PSBCHs can be reduced, the decoding success rate of the PSBCH can be improved, and the synchronous time delay in the direct link communication can be reduced.

In an alternative embodiment, step 11 may be preceded by: one sequence is selected from at least one candidate sequence as a PSBCH scrambled scrambling sequence according to the value of at least part of bits in information carried by the S-SSB (such as timing information carried in PSBCH).

Optionally, the number of candidate sequences is related to the number of at least some of the bits. Optionally, the candidate sequences corresponding to different values of at least some bits are different. For example, the correspondence between the value of at least a part of bits in the timing information and the candidate sequence may be predefined or preconfigured, and the terminal may select a plurality of candidate sequences according to the value of at least a part of bitsA scrambling sequence is selected for scrambling among the sequences. Assuming that the number of candidate sequences is N, in one embodiment, N is related to the number of bits of at least some bits, e.g., N-2^MAnd M is the number of at least some bits, which are referred to herein as bits associated with the selected scrambling sequence. For example, if the number of bits of at least some bits is 2, the number of candidate sequences is 4, and accordingly, the terminal selects a scrambling sequence for scrambling PSBCH from the 4 candidate sequences according to the value of the 2 bits. For another example, if the number of bits of at least some of the bits is 3, the number of candidate sequences is 8, and accordingly, the terminal selects a scrambling sequence for scrambling PSBCH from among the 8 candidate sequences according to the value of the 3 bits.

The selection or determination of the scrambling sequence is described above, and the initialization of the scrambling sequence is further described below. It is noted that the initialization method can be applied in combination with the selection or determination method described above, or can be applied separately. Optionally, the initialization sequence of the scrambling sequence is derived from a Sidelink-Synchronization Signal identification number (SL-SSID).

Specifically, before step 11, the information sending method according to the embodiment of the present invention may further include: initializing a scrambling sequence through SL-SSID; wherein different SL-SSIDs correspond to different scrambling sequences.

Specifically, the scrambling sequence is initialized by SL-SSID to: calculating C from SL-SSID_initAccording to C_initAn initialization scrambling sequence is performed.

In some embodiments, the process of scrambling the PSBCH by the scrambling sequence includes at least one of:

scrambling the PSBCH through a first scrambling sequence;

and scrambling the PSBCH through a second scrambling sequence.

Wherein the first scrambling sequence is associated with first information and the second scrambling sequence is associated with second information. The first information and the second information may have the same or different contents. Optionally, at least a part of bits of the target information (such as timing information carried by PSBCH) related to selecting the first scrambling sequence is the first information, and at least a part of bits of the target information related to selecting the second scrambling sequence is the second information. That is, at least a portion of the bits corresponding to the first scrambling sequence and the second scrambling sequence may be the same or different.

That is, the PSBCH is scrambled by the scrambling sequence, including:

scrambling the PSBCH through a first scrambling sequence; or, scrambling the PSBCH through a second scrambling sequence; or, the PSBCH is scrambled through the first scrambling sequence, and then the PSBCH is scrambled through the second scrambling sequence;

Specifically, the process of scrambling the PSBCH by the scrambling sequence may include:

selecting a first scrambling sequence from at least one candidate sequence according to the value of the first information, and scrambling the PSBCH according to the first scrambling sequence;

or selecting a second scrambling sequence from at least one candidate sequence according to the value of the second information, and scrambling the PSBCH according to the second scrambling sequence;

or selecting a first scrambling sequence from at least one candidate sequence according to the value of the first information, scrambling the PSBCH according to the first scrambling sequence, selecting a second scrambling sequence from at least one candidate sequence according to the value of the second information, and scrambling the PSBCH according to the second scrambling sequence.

In an optional embodiment of the present invention, the step of scrambling the PSBCH according to the first scrambling sequence comprises:

scrambling the PSBCH load bit sequence through a first scrambling sequence; the PSBCH payload bit sequence is generated by interleaving the payload (such as the PSBCH of the broadcast message) in the PSBCH. That is, the first scrambling occurs after the interleaving of the PSBCH payload bit sequence.

In an optional embodiment of the present invention, the step of scrambling the PSBCH according to the second scrambling sequence comprises: scrambling the PSBCH sequence through a second scrambling sequence; wherein, the PSBCH sequence is generated after interleaving and rate matching of the load (such as the PSBCH of the broadcast message) in the PSBCH. That is, the second scrambling occurs after the PSBCH sequence rate matching.

In the embodiment of the present invention, the first information and/or the second information may be carried by a DMRS of a PSBCH, that is, the terminal may obtain the first information and/or the second information by detecting the DMRS of the PSBCH. Specifically, the terminal acquires the first information and/or the second information by blindly detecting a DMRS sequence of the PSBCH. For example, the terminal may obtain the second signal by detecting the DMRS of the PSBCH.

As an alternative embodiment, the PSBCH is scrambled by the first scrambling sequence, which includes: and according to the first information, selecting one sequence from the first candidate sequence set as a first scrambling sequence, and scrambling the PSBCH by the first scrambling sequence.

As an alternative embodiment, the PSBCH is scrambled by the second scrambling sequence, which includes:

It is to be noted that the first candidate sequence set may be the same as or different from the second candidate sequence set, and this is not particularly limited in the embodiment of the present invention. Similarly, the first sequence and the second sequence may be the same or different, and the first sequence and/or the second sequence may be pseudo-random sequences. In addition, N, M, N1, M1, N2 and M2 mentioned in the embodiment of the invention are all positive integers.

To further increase the flexibility, in the above embodiment of the present invention, step 11 may include: according to the system configuration, the scrambling mode of the PSBCH is determined, and different scrambling modes can be selected by different system configurations.

For example, according to the system configuration, it is determined to scramble the PSBCH at least once, and when it is determined to scramble the PSBCH multiple times, the scrambling method used in each scrambling process may be the same or different. Therefore, the scrambling mode of the PSBCH is flexibly determined according to the system configuration, the flexibility of PSBCH scrambling flow configuration is improved, the method is suitable for different scenes, and the success rate of PSBCH decoding is improved.

Optionally, according to the system configuration, the step of determining to scramble the PSBCH at least once includes one of:

in a first system configuration case, the PSBCH is scrambled according to a first scrambling sequence. Optionally, in case of a first system configuration, a first scrambling sequence is selected from the at least one candidate sequence according to a value of the first information, and the PSBCH is scrambled according to the first scrambling sequence.

In a second system configuration case, the PSBCH is scrambled according to the first scrambling sequence and the PSBCH is scrambled according to the second scrambling sequence. Optionally, in a case of a second system configuration, a first scrambling sequence is selected from the at least one candidate sequence according to a value of the first information, the PSBCH is scrambled according to the first scrambling sequence, a second scrambling sequence is selected from the at least one candidate sequence according to a value of the second information, and the PSBCH is scrambled according to the second scrambling sequence.

In a third system configuration case, the PSBCH is scrambled according to a second scrambling sequence. Optionally, in case of a third system configuration, a second scrambling sequence is selected from the at least one candidate sequence according to a value of the second information, and the PSBCH is scrambled according to the second scrambling sequence.

Taking the system configuration of the operating frequency band including the PSBCH as an example, the terminal may determine to scramble the PSBCH according to the operating frequency band of the PSBCH. For example, when the operating Frequency band of the PSBCH is Frequency band 1(Frequency Range1, FR1), only beam repetition is needed, and beam scanning is not needed, all transmitted S-SSBs in the case of beam repetition can be subjected to PSBCH decoding after combining, and for convenience of combining, the PSBCH is scrambled according to the first scrambling sequence. For another example, when the operating Frequency band of the PSBCH is Frequency band 1(Frequency Range2, FR2), beam scanning is required, the PSBCH needs to be scrambled according to the first scrambling sequence, and then scrambled according to the second scrambling sequence.

In order to improve flexibility, different system configurations adopt different lengths of scrambling sequences for scrambling. Taking the system configuration as an example of an operating frequency band including the PSBCH, when the operating frequency band of the PSBCH is FR1, the length of the scrambling sequence for scrambling the PSBCH is M1, and when the operating frequency band of the PSBCH is FR2, the length of the scrambling sequence for scrambling the PSBCH is M2.

The first information and/or the second information in the above scrambling process, such as the first information related to the first scrambling process and the second information related to the second scrambling process, will be further described below. The first information and/or the second information comprises at least one of: at least partial bits of a Direct Frame Number (DFN); at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number.

At least some of the embodiments of the present invention may refer to part or all. For example, at least some of the bits of the DFN are the 2 nd and 3 rd bits of the least significant bit of the DFN. At least some of the bits of the S-SSB index number are the 2 or 3 least significant bits of the S-SSB index number. At least some of the bits of the slot number are the 2 or 3 least significant bits of the slot number. The timeslot number referred to herein may be a timeslot number within a system radio Frame (sysstem Frame, SF) or a Direct radio Frame (DF).

In some embodiments of the present invention, in scrambling the PSBCH according to the first scrambling sequence, specific bits are not scrambled, such as at least one of at least partial bits of the DFN, at least partial bits of the S-SSB index number, and at least partial bits of the slot number in the first information. Specifically, the first information and/or bits indicating the S-SSB index number are not scrambled in the first scrambling process. Optionally, in the process of scrambling the PSBCH according to the first scrambling sequence, the bits indicating the 2 nd and 3 rd bits of the least significant bit of the DFN and/or the bits indicating the S-SSB index number in the first information are not scrambled in the first scrambling process.

The different scrambling modes in the PSBCH scrambling method according to the embodiment of the present invention are introduced above, and the following will describe them in detail with reference to specific examples.

Example one:

and scrambling the PSBCH through a first scrambling sequence, and transmitting the scrambled PSBCH. Specifically, a first scrambling sequence is selected from candidate sequences according to the value of at least part of bits in the first information; scrambling the PSBCH load bit sequence by the first scrambling sequence; the PSBCH load bit sequence is generated after the PBSCH load of the broadcast message in the PBSCH is interleaved.

As shown in fig. 2, the terminal generates a broadcast message, generates a PSBCH payload, performs interleaving processing to obtain a PSBCH payload bit sequence, and scrambles the PSBCH payload bit sequence by using a first scrambling sequence. After scrambling, adding Cyclic Redundancy Check (CRC) and performing Polar coding, then performing rate matching, and performing QPSK modulation and resource mapping on the PSBCH sequence after rate matching, thereby transmitting the S-SSB containing the PSBCH.

The first information in this example includes at least one of:

at least some bits of the DFN, such as bits 2 and 3 of the least significant bit of the DFN.

At least a portion of bits of the S-SSB index number, such as a portion of bits or all of bits of the S-SSB index number;

at least some bits of the slot number, such as some or all bits of the slot number.

The candidate sequence is associated with first information, and the first scrambling process will be described below with reference to different first information as an example.

In the first mode, when the first information refers to the 2 nd bit and the 3 rd bit of the DFN least significant bit, one of the four candidate sequences (or referred to as candidate subsequences) is selected as a first scrambling sequence according to the value of the two bits, and the PSBCH payload bit sequence is scrambled using the first scrambling sequence.

Assuming that the DFN is 10 bits, such as 1101011101, starting from the rightmost side, the rightmost 1 st bit is the least significant bit 1, the rightmost 2 nd bit is the least significant bit 2, and so on, as shown in table 1.

Table 1: least significant bit schematic table of Direct Frame Number (DFN)

When the first information refers to the 2 nd and 3 rd bits of the DFN least significant bits, selecting one subsequence from the four candidate subsequences as a first scrambling sequence according to the values (1,0) of the 2 nd and 3 rd bits of the DFN least significant bits, and scrambling the PSBCH payload bit sequence using the first scrambling sequence, which refers to:

load bit sequence a of PSBCH₀,a₁,a₂,a₃,...,a_A-1Scrambled into a bit sequence a'₀,a'₁,a'₂,a'₃,...,a'_A-1Wherein a'_i＝(a_i+s_i) mod2 and i ═ 0, 1. A is the total number of bits of the PSBCH payload.

s₀,s₁,s₂,s₃,...,s_A-1Produced according to the following procedure:

i＝0；

j＝0；

while i<A

if a_ibelongs to the bits representing the S-SSB index number; or 2 nd and 3 rd bits representing the least significant bit of the DFN

s_i＝0；

else

s_i＝c(j+vM)；

j＝j+1；

end if

i＝i+1；

end while

Wherein C (i) is a pseudo-random sequence, and is represented by C_initInitialization is performed as SL-SSID. M is the number of PSBCH payload bits participating in scrambling. In this embodiment, c (i) is a candidate sequence, and s_iIs the first scrambling sequence, s_iIs a subsequence of c (i), or a portion or fragment of c (i) sequence. v is determined using the 2 nd and 3 rd bits of the DFN least significant bit of the transmission PSBCH according to table 2.

Table 2: method for determining v value

(bit 3 of the least significant bit of DFN, bit 2 of the least significant bit of DFN)	Value of v
		(0,0)	0
(0,1)	1
		(1,0)	2
(1,1)	3

Secondly, when the first information is the S-SSB index number, the PSBCH load bit sequence a₀,a₁,a₂,a₃,...,a_A-1Scrambled into a bit sequence a'₀,a'₁,a'₂,a'₃,...,a'_A-1Wherein a'_i＝(a_i+s_i) mod2 and i ═ 0, 1. A is the total number of bits of the PSBCH payload.

s₀,s₁,s₂,s₃,...,s_A-1Produced according to the following procedure:

i＝0；

j＝0；

while i<A

s_i＝0；

else

s_i＝c(j+vM)；

j＝j+1；

end if

i＝i+1；

end while

Wherein C (i) is a pseudo-random sequence, and is represented by C_initInitialization is performed as SL-SSID. M is the number of PSBCH payload bits participating in scrambling. In this embodiment, c (i) is a candidate sequence, and s_iIs the first scrambling sequence, s_iIs a subsequence, or segment, of c (i), or v (S-SSB index).

And in a third mode, when the first information is the time slot number, the time slot number refers to the time slot number in a system wireless frame or the time slot number in a direct frame. Load bit sequence a of PSBCH₀,a₁,a₂,a₃,...,a_A-1Scrambled into a bit sequence a'₀,a'₁,a'₂,a'₃,...,a'_A-1Wherein a'_i＝(a_i+s_i) mod2 and i ═ 0, 1. A is the total number of bits of the PSBCH payload.

s₀,s₁,s₂,s₃,...,s_A-1Produced according to the following procedure:

i＝0；

j＝0；

while i<A

s_i＝0；

else

s_i＝c(j+vM)；

j＝j+1；

end if

i＝i+1；

end while

Wherein C (i) is a pseudo-random sequence, and is represented by C_initInitialization is performed as SL-SSID. M is the number of PSBCH payload bits participating in scrambling. In this embodiment, c (i) is a candidate sequence, and s_iIs the first scrambling sequence, s_iIs a sub-sequence of c (i), or a part or segment of c (i), and v is the slot number.

In this example, the scrambling is performed with different lengths of the first scrambling sequence, depending on the system configuration. Taking the system configuration including the operating band of the PSBCH as an example, when the operating band of the PSBCH belongs to FR1, the length of the first scrambling sequence used by the PSBCH is M1, and when the operating band of the PSBCH belongs to FR2, the length of the first scrambling sequence used by the PSBCH is M2, and M1 is not equal to M2.

Example two:

scrambling the PSBCH through a first scrambling sequence, and scrambling the PSBCH through a second scrambling sequence; and transmitting the scrambled PSBCH. Specifically, a first scrambling sequence is selected from candidate sequences according to a value of the first information; scrambling the PSBCH load bit sequence by the first scrambling sequence; the PSBCH load bit sequence is generated after the PBSCH load of the broadcast message in the PBSCH is interleaved. Then selecting a second scrambling sequence from the candidate sequences according to the value of the second information; and scrambling a PSBCH sequence through a second scrambling sequence, wherein the PSBCH sequence is generated after interleaving and rate matching are carried out on the PSBCH load of the broadcast message in the PSBCH.

As shown in fig. 3, the terminal generates a broadcast message, generates a PSBCH payload, performs interleaving processing to obtain a PSBCH payload bit sequence, and scrambles the PSBCH payload bit sequence by using a first scrambling sequence. And after scrambling, adding CRC and performing Polar coding, then performing rate matching, scrambling the PSBCH sequence after rate matching by using a second scrambling sequence, and then performing QPSK modulation and resource mapping on the PSBCH sequence after scrambling, thereby sending the S-SSB containing the PSBCH.

The first information in this example is similar to the first information in example one, and the first scrambling procedure is similar to the scrambling procedure in example one, and therefore, the description thereof is omitted. The present example will specifically describe the second information and the second scrambling procedure.

The second information in this example includes at least one of:

at least a portion of the bits of the DFN;

at least a portion of the bits of the S-SSB index number, such as two least significant bits or three least significant bits of the S-SSB index number;

at least some of the bits of the slot number, such as the two least significant bits or the three least significant bits of the slot number.

The candidate sequence is associated with second information, and the second scrambling process will be described below with reference to different second information as an example.

In the first mode, when the second information refers to two least significant bits of the S-SSB index number, one of the four candidate sequences (or called candidate subsequences) is selected as a second scrambling sequence according to the values of the two bits, and the PSBCH sequence is scrambled by using the second scrambling sequence. When the second information refers to three least significant bit bits of the S-SSB index number, one of eight candidate sequences (or called candidate subsequences) is selected as a second scrambling sequence according to the values of the three bit bits, and the PSBCH sequence is scrambled by using the second scrambling sequence.

Assuming that the S-SSB index number is 6 bits, such as 111001, starting from the rightmost side, the rightmost 1 st bit is the least significant bit 1, the rightmost 2 nd bit is the least significant bit 2, and so on, as shown in table 3.

Table 3: least significant bit signification table for S-SSB index number

When the second information refers to 2 or 3 least significant bits of the S-SSB index number, selecting one subsequence from the 4 or 8 candidate subsequences as a second scrambling sequence according to a value (0,1) or (0,0,1) of the 2 or 3 least significant bits of the S-SSB index number, and scrambling the PSBCH sequence using the second scrambling sequence, which refers to:

for PSBCH sequence b (0), …, b (M)_bit-1) wherein M_bitIs the length of the PSBCH sequence, and is scrambled by the following formula

Wherein c (i) is a pseudo-random sequence, and by c_initInitialization is performed as SL-SSID.

In the second mode, when the first information is a timeslot number, the timeslot number refers to a timeslot number in a system radio frame or a timeslot number in a direct frame. When the second information refers to two least significant bits of the slot number, one of the four candidate sequences (or called candidate subsequences) is selected as a second scrambling sequence according to the values of the two bits, and the PSBCH sequence is scrambled by using the second scrambling sequence. When the second information refers to three least significant bits of the slot number, one of eight candidate sequences (or called candidate subsequences) is selected as a second scrambling sequence according to the value of the three bits, and the PSBCH sequence is scrambled by using the second scrambling sequence.

Assuming that the slot number is 6 bits, such as 111001, from the rightmost side, the rightmost 1 st bit is the 1 st bit of the least significant bit, the rightmost 2 nd bit is the 2 nd bit of the least significant bit, and so on, as shown in table 4.

Table 4: least significant bit schematic table of time slot number

When the second information refers to the 2 or 3 least significant bits of the slot number, selecting one subsequence from the 4 or 8 candidate subsequences as a second scrambling sequence according to the value (0,1) or (0,0,1) of the 2 or 3 least significant bits of the slot number, and scrambling the PSBCH sequence by using the second scrambling sequence, which refers to:

In this example, the number of bits contained in the second information is different for different system configurations. Taking the system configuration as an example of an operating frequency band including the PSBCH, when the operating frequency band of the PSBCH belongs to FR1, v is two least significant bits of the S-SSB index number, or v is two least significant bits of the timeslot number; when the operating band of the PSBCH belongs to FR2, v is the three least significant bits of the S-SSB index number, or v is the three least significant bits of the slot number.

Example three:

scrambling the PSBCH through a second scrambling sequence; and transmitting the scrambled PSBCH. Specifically, a second scrambling sequence is selected from the candidate sequences according to the value of the second information; and scrambling a PSBCH sequence through a second scrambling sequence, wherein the PSBCH sequence is generated after interleaving and rate matching are carried out on the PSBCH load of the broadcast message in the PSBCH.

As shown in fig. 4, the terminal generates a broadcast message, generates a PSBCH load, performs interleaving processing to obtain a PSBCH load bit sequence, then adds CRC and performs Polar coding, then performs rate matching, scrambles the PSBCH sequence after rate matching by using a second scrambling sequence, and then performs QPSK modulation and resource mapping on the scrambled PSBCH sequence, thereby transmitting the S-SSB including the PSBCH.

The second information in this example is similar to the second information in example two, and the second scrambling procedure is similar to the scrambling procedure in example two, and therefore is not described again.

Example four:

in order to improve flexibility, the scrambling mode of the PSBCH is determined according to system configuration, and different scrambling modes can be selected by different system configurations. For example, according to the system configuration, it is determined to scramble the PSBCH at least once, and when it is determined to scramble the PSBCH multiple times, the scrambling method used in each scrambling process may be the same or different. Therefore, the scrambling mode of the PSBCH is flexibly determined according to the system configuration, the flexibility of PSBCH scrambling flow configuration is improved, the method is suitable for different scenes, and the success rate of PSBCH decoding is improved.

As shown in FIG. 3, the first scrambling process occurs after the interleaving of the PSBCH payload bit sequence, while the second scrambling process occurs after the PSBCH sequence rate matching. Depending on the system configuration, the PSBCH may undergo only the first scrambling procedure, or only the second scrambling procedure, or need to undergo both the first scrambling procedure and the second scrambling procedure before being transmitted.

One implementation is to control whether to perform the first or second scrambling procedure according to whether the operating band of the PSBCH belongs to FR1 or FR 2. Performing a first scrambling procedure on the PSBCH when an operating frequency band of the PSBCH belongs to FR 1; when the operating band of the PSBCH belongs to FR2, the PSBCH is subjected to a first scrambling process and a second scrambling process.

With the PSBCH scrambling method according to the embodiment of the present invention described above, in the PSBCH scrambling process, no scrambling process may be performed on specific bits in the timing information carried in the PSBCH, for example: at least some bits in the timing information, bits representing the S-SSB index number, etc. Specifically, at least a portion of the bits in the timing information, bits representing the S-SSB index number, etc. may not be scrambled when the PSBCH payload bit sequence is scrambled with the first scrambling sequence.

In the first embodiment, the terminal scrambles the physical direct link broadcast channel PSBCH through a scrambling sequence; and transmitting the scrambled PSBCH. The scrambling sequence used by scrambling is related to timing information carried by the PSBCH, so that mutual interference between PSBCH channels among different synchronization clusters in a direct link can be reduced, the decoding success rate of the PSBCH is improved, and the synchronization delay of a terminal can be reduced.

Second embodiment

As shown in fig. 5, an embodiment of the present invention further provides a terminal 50, including: the transceiver 51, the processor 52, the memory 53, and the memory 53 having stored thereon programs executable by the processor 52; the processor, when executing the program, controls the transceiver 51 to: transmitting a through link synchronization signal block S-SSB, the S-SSB including a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number.

Optionally, the processor 52 is further configured to: and initializing the scrambling sequence according to the through link synchronous signal identification number SL-SSID.

Optionally, the processor 52 is further configured to: scrambling the PSBCH through a first scrambling sequence;

or, scrambling the PSBCH through a second scrambling sequence;

Optionally, the processor 52 is configured to: scrambling the PSBCH load bit sequence through a first scrambling sequence; the PSBCH payload bit sequence is generated after the payload in the PSBCH is interleaved.

Optionally, the processor 52 is configured to: scrambling the PSBCH sequence through a second scrambling sequence; wherein, the PSBCH sequence is generated after the load in the PSBCH is interleaved and rate-matched.

Optionally, the processor 52 is specifically configured to: and selecting one sequence from the first candidate sequence set as a first scrambling sequence according to the first information, and scrambling the PSBCH by the first scrambling sequence.

Optionally, the processor is specifically configured to:

It should be noted that the terminal in this embodiment is a terminal corresponding to the method shown in fig. 1, and the implementation manners in the above embodiments are all applicable to the embodiment of the terminal, and the same technical effects can be achieved. In the terminal, the transceiver 51 and the memory 53, and the transceiver 51 and the processor 52 may be communicatively connected through a bus interface, and the function of the processor 52 may also be implemented by the transceiver 51, and the function of the transceiver 51 may also be implemented by the processor 52. It should be noted that, the terminal provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Third embodiment

As shown in fig. 6, an embodiment of the present invention further provides an information sending apparatus, which is applied to a terminal, and the apparatus includes the following functional modules:

a sending module 61, configured to send a direct link synchronization signal block S-SSB, where the S-SSB includes a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number.

Optionally, the apparatus further comprises: and the initialization module is used for initializing the scrambling sequence according to the synchronous signal identification number SL-SSID of the through link.

Optionally, the apparatus further comprises: a scrambling module 62, the scrambling module 62 comprising:

the first scrambling submodule is used for scrambling the PSBCH through a first scrambling sequence;

or, the second scrambling submodule is used for scrambling the PSBCH through a second scrambling sequence;

or, the third scrambling submodule is used for scrambling the PSBCH through the first scrambling sequence and then scrambling the PSBCH through the second scrambling sequence;

Optionally, the first scrambling submodule is specifically configured to: scrambling the PSBCH load bit sequence through a first scrambling sequence; the PSBCH payload bit sequence is generated after the payload in the PSBCH is interleaved.

Optionally, the second scrambling submodule is configured to scramble the PSBCH sequence by using a second scrambling sequence; wherein, the PSBCH sequence is generated after the load in the PSBCH is interleaved and rate-matched.

Optionally, the scrambling module 62 is specifically configured to: and selecting one sequence from the first candidate sequences as a first scrambling sequence according to the first information, and scrambling the PSBCH by the first scrambling sequence.

Optionally, the scrambling module 62 is specifically configured to:

Optionally, at least some of the bits of the slot number are 2 or 3 least significant bits of the slot number.

Optionally, in the process of scrambling the PSBCH according to the first scrambling sequence, at least one of at least a part of bits of the DFN, at least a part of bits of the S-SSB index number, and at least a part of bits of the slot number in the first information is not scrambled.

It should be noted that the apparatus in this embodiment is an apparatus corresponding to the method shown in fig. 1, and the implementation manners in the above embodiments are all applicable to the embodiment of the apparatus, and the same technical effects can be achieved. The device may further comprise a processing module and the like for processing the information transmitted by the transmitting module and the like. It should be noted that, the apparatus provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Fourth embodiment

As shown in fig. 7, an embodiment of the present invention further provides an information receiving method, which is applied to a terminal, and the method may include the following steps:

step 71: a through-link synchronization signal block S-SSB is received, the S-SSB containing a PSBCH scrambled by a scrambling sequence. Wherein the scrambling sequence is determined by at least one of first information and second information, the at least one of the first information and the second information comprising at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number. Wherein, the first information and the second information can be at least partial bits in target information carried by the S-SSB (such as timing information carried by the PSBCH). Specifically, the scrambling sequence may be determined from timing information carried in the PSBCH. It is worth pointing out that the PSBCH can also include: time domain configuration information (such as subframe configuration information), frequency domain configuration information (such as bandwidth information, subcarrier spacing information, and the like), coverage indication information (such as synchronization cluster information), and the like. In NR V2X, the PSBCH is contained in the S-SSB, that is, the S-SSB contains the PSBCH, and step 12 can also be understood as transmitting the S-SSB containing the scrambled PSBCH.

Further, the method further comprises: the PSBCH in the S-SSB is descrambled through a scrambling sequence (or descrambling). The descrambling process is the inverse process of the scrambling process in the first embodiment, and when the terminal at the transmitting side scrambles the PSBCH by using the first scrambling process, the terminal at the receiving side descrambles the PSBCH in the S-SSB by using the first descrambling process. And when the terminal at the transmitting side scrambles the PSBCH by adopting a second scrambling process, the terminal at the receiving side descrambles the PSBCH in the S-SSB by adopting a second descrambling process. When the terminal at the transmitting side scrambles the PSBCH by adopting the first scrambling process and the second scrambling process, the terminal at the receiving side descrambles the PSBCH in the S-SSB by adopting the first descrambling process and the second descrambling process. It should be noted that the first information and the second information related in the receiving side terminal embodiment are similar to the first information and the second information mentioned in the first embodiment, and the selection manner of the first information and the second information and the selection manner of the scrambling sequence in the first embodiment are all applicable to this embodiment, and therefore are not described herein again.

The terminal at the transmitting side transmits the PSBCH scrambled by the scrambling sequence, and the receiving side descrambles the PSBCH by adopting the corresponding scrambling sequence, so that the mutual interference between PSBCH channels among different synchronous clusters in a direct link can be reduced, the decoding success rate of the PSBCH is improved, and the synchronous time delay of the terminal can be reduced.

Fifth embodiment

As shown in fig. 8, an embodiment of the present invention further provides a terminal 80, including: a transceiver 81, a processor 82, a memory 83, the memory 83 having a program executable by the processor 82 stored thereon; the control transceiver 81 when the processor executes the program implements: receiving a through link synchronization signal block S-SSB, the S-SSB comprising a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number.

Optionally, the processor 82 is further configured to: and descrambling the PSBCH in the S-SSB through the scrambling sequence.

It should be noted that the terminal in this embodiment is a terminal corresponding to the method shown in fig. 7, and the implementation manners in the above embodiments are all applicable to the embodiment of the terminal, and the same technical effects can be achieved. In the terminal, the transceiver 81 and the memory 83, and the transceiver 81 and the processor 82 may be communicatively connected through a bus interface, the function of the processor 82 may be implemented by the transceiver 81, and the function of the transceiver 81 may be implemented by the processor 82. It should be noted that, the terminal provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Sixth embodiment

As shown in fig. 9, an embodiment of the present invention further provides an information receiving apparatus, which is applied to a terminal, and the apparatus includes the following functional modules:

a receiving module 91, configured to receive a direct link synchronization signal block S-SSB, where the S-SSB includes a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of: at least part of the bits of the direct radio frame number, DFN; at least part of bits of the S-SSB index number of the direct link synchronous broadcast channel block; at least some bits of the slot number.

Wherein, the device still includes: and the descrambling module is used for descrambling the PSBCH in the S-SSB through the scrambling sequence.

The apparatus in this embodiment is an apparatus corresponding to the method shown in fig. 7, and the implementation manners in the above embodiments are all applied to the embodiment of the apparatus, and the same technical effects can be achieved. The device may further comprise a processing module and the like for processing the information transmitted by the transmitting module and the like. It should be noted that, the apparatus provided in the embodiment of the present invention can implement all the method steps implemented by the method embodiment and achieve the same technical effect, and detailed descriptions of the same parts and beneficial effects as the method embodiment in this embodiment are omitted here.

Embodiments of the present invention further provide a processor-readable storage medium, which stores processor-executable instructions for causing the processor to execute the method of fig. 1 or fig. 7, where all the implementations in the above method embodiments are applicable to this embodiment, and the same technical effect can be achieved.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a U disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

Furthermore, it is to be noted that in the device and method of the invention, it is obvious that the individual components or steps can be decomposed and/or recombined. These decompositions and/or recombinations are to be regarded as equivalents of the present invention. Also, the steps of performing the series of processes described above may naturally be performed chronologically in the order described, but need not necessarily be performed chronologically, and some steps may be performed in parallel or independently of each other. It will be understood by those skilled in the art that all or any of the steps or elements of the method and apparatus of the present invention may be implemented in any computing device (including processors, storage media, etc.) or network of computing devices, in hardware, firmware, software, or any combination thereof, which can be implemented by those skilled in the art using their basic programming skills after reading the description of the present invention.

Thus, the objects of the invention may also be achieved by running a program or a set of programs on any computing device. The computing device may be a general purpose device as is well known. The object of the invention is thus also achieved solely by providing a program product comprising program code for implementing the method or the apparatus. That is, such a program product also constitutes the present invention, and a storage medium storing such a program product also constitutes the present invention. It is to be understood that the storage medium may be any known storage medium or any storage medium developed in the future. It is further noted that in the apparatus and method of the present invention, it is apparent that each component or step can be decomposed and/or recombined. These decompositions and/or recombinations are to be regarded as equivalents of the present invention. Also, the steps of executing the series of processes described above may naturally be executed chronologically in the order described, but need not necessarily be executed chronologically. Some steps may be performed in parallel or independently of each other.

While the preferred embodiments of the present invention have been described, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. An information sending method, applied to a terminal, the method comprising:

transmitting a through-link synchronization signal block, S-SSB, the S-SSB containing a physical through-link broadcast channel, PSBCH, scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

2. The information transmitting method of claim 1, wherein at least one of the first information and the second information is carried by a PSBCH payload, or wherein at least one of the first information and the second information is carried by a PSBCH demodulation reference signal (DMRS).

3. The method according to claim 1, further comprising:

and initializing the scrambling sequence according to the identification number SL-SSID of the through link synchronous signal.

4. The information transmitting method of claim 1, wherein the PSBCH is scrambled by a scrambling sequence, and comprises:

scrambling the PSBCH through a first scrambling sequence;

alternatively, the first and second electrodes may be,

scrambling the PSBCH through a second scrambling sequence;

alternatively, the first and second electrodes may be,

scrambling the PSBCH through the first scrambling sequence, and scrambling the PSBCH through the second scrambling sequence;

wherein the first scrambling sequence is determined according to the first information and the second scrambling sequence is determined according to the second information.

5. The information transmitting method of claim 4, wherein scrambling the PSBCH by the first scrambling sequence comprises:

scrambling the PSBCH load bit sequence through the first scrambling sequence; wherein the PSBCH payload bit sequence is generated after the payload in the PSBCH is interleaved.

6. The information transmitting method of claim 4, wherein scrambling the PSBCH by the second scrambling sequence comprises:

scrambling the PSBCH sequence through the second scrambling sequence; wherein the PSBCH sequence is generated after interleaving and rate matching of the load in the PSBCH.

7. The information transmitting method of claim 4, wherein scrambling the PSBCH by a first scrambling sequence comprises:

and selecting one sequence from a first candidate sequence set as the first scrambling sequence according to the first information, and scrambling the PSBCH through the first scrambling sequence.

8. The information transmission method as claimed in claim 7, wherein the number N1 of candidate sequences in the first candidate sequence set is 2^M1And M1 is the number of bits in the first information.

9. The method of claim 7, wherein each sequence in the first set of candidate sequences is a part of the first sequence or a subsequence of the first sequence.

10. The information transmitting method of claim 4, wherein scrambling the PSBCH by a second scrambling sequence comprises:

and selecting one sequence from a second candidate sequence set as the second scrambling sequence according to the second information, and scrambling the PSBCH through the second scrambling sequence.

11. The information transmission method as claimed in claim 10, wherein the number N2 of candidate sequences in the second candidate sequence set is 2^M2And M2 is the number of bits in the second information.

12. The method of claim 10, wherein each sequence in the second set of candidate sequences is a part of the second sequence or a subsequence of the second sequence.

13. The method of claim 1, wherein at least some of the bits of the DFN are bits 2 and 3 of a least significant bit of the DFN.

14. The method of claim 1, wherein at least some of the bits of the S-SSB index number are 2 or 3 least significant bits of the S-SSB index number.

15. The method for transmitting information according to claim 1, wherein at least some bits of the slot number are 2 or 3 least significant bits of the slot number.

16. The method of claim 1, wherein the timeslot number is a timeslot number in a system radio frame or a direct radio frame.

17. The information transmitting method of claim 1, wherein at least one of at least partial bits of the DFN, at least partial bits of the S-SSB index number, and at least partial bits of the slot number in the first information is not scrambled in the process of scrambling the PSBCH.

18. An information receiving method, applied to a terminal, the method comprising:

receiving a through-link synchronization signal block, S-SSB, the S-SSB including a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

19. The information receiving method according to claim 18, further comprising:

and descrambling the PSBCH in the S-SSB through the scrambling sequence.

20. A terminal, comprising: the transceiver, the processor, the memorizer, store the procedure that the said processor can carry out on the said memorizer;

the processor, when executing the program, controls the transceiver to: transmitting a through link synchronization signal block, S-SSB, the S-SSB containing a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

21. The terminal of claim 20, wherein at least one of the first information and the second information is carried by a PSBCH payload, or wherein at least one of the first information and the second information is carried by a PSBCH demodulation reference signal, DMRS.

22. The terminal of claim 20, wherein the processor is configured to: and initializing the scrambling sequence according to the identification number SL-SSID of the through link synchronous signal.

23. The terminal of claim 20, wherein the processor is specifically configured to:

scrambling the PSBCH through a first scrambling sequence;

alternatively, the first and second electrodes may be,

scrambling the PSBCH through a second scrambling sequence;

alternatively, the first and second electrodes may be,

24. The terminal of claim 23, wherein the processor is configured to:

25. The terminal of claim 23, wherein the processor is configured to:

26. The terminal of claim 23, wherein the processor is further configured to:

27. The terminal of claim 26, wherein the number of candidate sequences in the first set of candidate sequences N1 is 2^M1And M1 is the number of bits in the first information.

28. The signal terminal of claim 26, wherein each sequence in the first set of candidate sequences is a part of the first sequence or a subsequence of the first sequence.

29. The terminal of claim 23, wherein the processor is further configured to:

30. The terminal of claim 29, wherein the number N2 of candidate sequences in the second set of candidate sequences is 2^M2And M2 is the number of bits in the second information.

31. The terminal of claim 29, wherein each sequence in the second set of candidate sequences is a part of the second sequence or a subsequence of the second sequence.

32. The terminal of claim 20, wherein at least some of the bits of the DFN are bits 2 and 3 of a least significant bit of the DFN.

33. The terminal of claim 20, wherein at least some bits of the S-SSB index number are 2 or 3 least significant bits of the S-SSB index number.

34. The terminal of claim 20, wherein at least some of the bits of the slot number are 2 or 3 least significant bits of the slot number.

35. The terminal of claim 20, wherein the timeslot number is a timeslot number in a system radio frame or a direct radio frame.

36. The terminal of claim 20, wherein at least one of at least some bits of the DFN, at least some bits of the S-SSB index number, and at least some bits of the slot number in the first information is not scrambled in the process of scrambling the PSBCH.

37. An information transmission apparatus, applied to a terminal, the apparatus comprising:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

38. A terminal, comprising: the transceiver, the processor, the memorizer, store the procedure that the said processor can carry out on the said memorizer; the processor, when executing the program, controls the transceiver to: receiving a through-link synchronization signal block, S-SSB, the S-SSB including a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

39. The terminal of claim 38, wherein the processor is configured to:

and descrambling the PSBCH in the S-SSB through the scrambling sequence.

40. An information receiving apparatus, applied to a terminal, the apparatus comprising:

a receiving module, configured to receive a through link synchronization signal block S-SSB, where the S-SSB includes a PSBCH scrambled by a scrambling sequence; wherein the scrambling sequence is determined according to at least one of first information and second information, the at least one of the first information and the second information including at least one of:

at least part of the bits of the direct radio frame number, DFN;

at least some bits of the slot number.

41. A processor-readable storage medium having stored thereon processor-executable instructions for causing a processor to perform the method of transmitting information according to any one of claims 1 to 17 or the method of receiving information according to claim 18 or 19.