CN113271103B

CN113271103B - Resistance type high-speed high-precision SAR-ADC/DAC circuit and wireless charging equipment

Info

Publication number: CN113271103B
Application number: CN202110650826.2A
Authority: CN
Inventors: 李晔辰; 陈远明
Original assignee: China Resources Microelectronics Holding Co ltd; China Resources Shenzhen Bay Development Co ltd Science And Technology Research Branch; Shenzhen Research Institute Tsinghua University
Current assignee: China Resources Microelectronics Holding Co ltd; China Resources Shenzhen Bay Development Co ltd Science And Technology Research Branch; Shenzhen Research Institute Tsinghua University
Priority date: 2021-06-10
Filing date: 2021-06-10
Publication date: 2022-08-30
Anticipated expiration: 2041-06-10
Also published as: CN113271103A

Abstract

The invention discloses a resistance type high-speed high-precision SAR-ADC/DAC circuit and wireless charging equipment, which comprise a first operational amplifier and a second operational amplifier, wherein the first operational amplifier is used for carrying out first processing on a sampling voltage and transmitting the sampling voltage to an ADC/DAC module, and the second operational amplifier is used for carrying out second processing on a reference voltage and transmitting the reference voltage to the ADC/DAC module; the ADC/DAC module is used for carrying out third processing on the reference voltage subjected to the second processing, and transferring the reference voltage subjected to the third processing and the sampling voltage subjected to the first processing to the dynamic comparator, and the dynamic comparator outputs the converted serial SOB to the 12bits SAR logic device so that the 12bits SAR logic device outputs a parallel ADC; and the ADC/DAC module is also used for selectively outputting DAC signals after voltage division processing is carried out on the reference voltage subjected to the second processing. The invention can realize high-precision output and high-speed application on the basis of being compatible with ADC and DAC functions in a TRX chip with wireless charging.

Description

Resistance type high-speed high-precision SAR-ADC/DAC circuit and wireless charging equipment

Technical Field

The invention belongs to the technical field of wireless charging internal chips, and particularly relates to a resistance type high-speed high-precision SAR-ADC/DAC circuit and wireless charging equipment.

Background

At present, in the design of a wireless charging TRX chip, in order to sample and demodulate an AM modulation signal, calculate load power consumption, and provide an overcurrent reference voltage, a high-speed and high-precision ADC module and a DAC module are generally added, and even 2 to 3 groups of ADC modules may be needed to meet different application requirements. Are relatively commonThe capacitive SAR-ADC not only needs complex logic design, but also occupies larger layout area and cannot compatibly realize the DAC function; as shown in fig. 1, the conventional low-speed (several hundred KHz) low-precision (8 or 10bits) resistive SAR-ADC uses a conventional comparator (shown in fig. 2) and does not require high bandwidth due to its low-speed application; and it 2 ¹⁰ The divider resistors are arranged in sequence (shown in fig. 3), and although the MUX logic is relatively simple, the resistor array occupies a large layout area, and is only a low-precision resistor array. The SAR-ADC module based on the resistance belongs to low-precision and low-speed application, and is not suitable for being applied to a TRX chip.

Therefore, a resistive high-speed high-precision SAR-ADC/DAC circuit is needed to be applied to a TRX chip, meet the requirements of high speed and high precision, occupy smaller layout area and be compatible with ADC/DAC double functions.

Disclosure of Invention

The invention mainly aims to provide a resistance type high-speed high-precision SAR-ADC/DAC circuit and wireless charging equipment, and aims to solve the technical problems that the existing resistance type SAR-ADC module in the background technology is low in precision, only suitable for low speed and occupies a large layout area when applied to a TRX chip.

The invention provides a resistance type high-speed high-precision SAR-ADC/DAC circuit, which comprises a first operational amplifier and a second operational amplifier, wherein the first operational amplifier is used for carrying out first processing on a sampling voltage and transmitting the sampling voltage to an ADC/DAC module;

the ADC/DAC module is used for carrying out third processing on the reference voltage subjected to the second processing, transferring the reference voltage subjected to the third processing and the sampling voltage subjected to the first processing to the dynamic comparator, and the dynamic comparator outputs the converted serial SOB to the 12-bit SAR logic device so that the 12-bit SAR logic device outputs a parallel ADC; and the ADC/DAC module is also used for selectively outputting DAC signals after voltage division processing is carried out on the reference voltage subjected to the second processing.

On the basis of the first aspect, the ADC/DAC module includes a timing switch component and a transfer component, and a plurality of switches in the timing switch component transfer the divided voltage equivalent values of the first processed sampling voltage and the reference voltage to the transfer component according to a first preset switching rule.

On the basis of the first aspect, the timing switch assembly includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, and a seventh switch S7; the transfer component comprises a first transfer capacitor Ca and a second transfer capacitor Cb;

one end of the first transfer capacitor Ca is connected to one end of the first switch S1 and one end of the second switch S2, the other end of the first transfer capacitor Ca is connected to the first input end Va of the dynamic comparator, one end of the third switch S3 and one end of the seventh switch S7, one end of the second transfer capacitor Cb is connected to the first input end Vb of the dynamic comparator, one end of the fourth switch S4 and the other end of the seventh switch S7, the other end of the second transfer capacitor Cb is connected to one end of the sixth switch S6 and one end of the fifth switch S5, and the other end of the fifth switch S5 is connected to the other end of the sixth switch S6 and the other end of the second switch S2.

On the basis of the first aspect, the other end of the first switch S1 is simultaneously connected to a drain of a first NMOS transistor and one end of a third resistor R3, a source of the first NMOS transistor is simultaneously connected to a gate and a ground of the first NMOS transistor, the other end of the third resistor R3 is simultaneously connected to an output end of the first operational amplifier and a second input end of the first operational amplifier, and a first input end of the first operational amplifier is configured to receive the sampling voltage VIN.

On the basis of the first aspect, the ADC/DAC module comprises a module equivalent to 2 ¹² And the voltage division resistor array is used for carrying out voltage division processing on the reference voltage VREF subjected to the second processing.

On the basis of the first aspect, the voltage-dividing resistor array includes 64 resistors Rx in series relationship with each other, a first logic switch component for selecting a certain resistor of the 64 resistors Rx, 64 resistors Ry in series relationship with each other, and a second logic switch component for selecting a certain resistor of the 64 resistors Ry as a connection point.

On the basis of the first aspect, the output end of the voltage dividing resistor array is connected to an eighth switch S8, and the DAC signal is output when the eighth switch S8 is closed.

On the basis of the first aspect, the ADC/DAC module includes a third operational amplifier BUF3 having a first input end for receiving the reset voltage VRST, and a first output end of the third operational amplifier BUF3 is simultaneously connected to the second input end of the third operational amplifier BUF3, the other end of the third switch S3 and the other end of the fourth switch S4.

On the basis of the first aspect, the dynamic comparator includes an amplifying section for amplifying a difference between the first processed sampling voltage and a partial voltage of the reference voltage, and a dynamic transient comparison section for performing comparison processing on the amplified voltage output by the amplifying section.

The resistance type high-speed high-precision SAR-ADC/DAC circuit provided by the first aspect of the invention is applied to a wirelessly charged TRX chip, and has the beneficial effects that:

1. the high-speed (30MHz clock) high-bandwidth ADC circuit is mainly improved based on a common ADC resistance-type framework, high-bandwidth design is carried out on sampling voltage and reference voltage through a double operational amplifier, and the application of high speed (30MHz clock) is met by combining a dynamic comparator with optimized design, and meanwhile, 2 equivalent to the clock is adopted ¹² The 12bits high precision is realized by the resistor array with resistor voltage division and the 12bits SAR logic device.

2. Based on the integrated ADC/DAC module design, the dual functions of ADC/DAC can be realized, and based on the output of the DAC signal with selectable output, therefore, the influence of the capacitive load of the DAC signal on high speed and high bandwidth can be prevented when the ADC is applied.

3. The voltage dividing resistor array in the ADC/DAC module only needs 128 resistors and 130 switches to realize 2 ¹² (4096) The layout area is greatly saved compared with the traditional 4096 series resistors by the way of voltage division of the resistors.

A second aspect of the present invention provides a wireless charging device, comprising a resistive high-speed high-precision SAR-ADC/DAC circuit according to the first aspect; based on the selected resistance type high-speed high-precision SAR-ADC/DAC circuit, the formed wireless charging equipment is easy to miniaturize and realizes high charging efficiency.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a circuit connection diagram of a resistive SAR-ADC mentioned in the background art;

FIG. 2 is a schematic circuit connection diagram of a conventional comparator used in FIG. 1;

FIG. 3 is a schematic circuit diagram of the voltage divider resistor array used in FIG. 1;

FIG. 4 is a simple functional block diagram of the resistive high-speed high-precision SAR-ADC/DAC circuit according to the first aspect of the present invention;

FIG. 5 is a core functional block diagram of the resistive high-speed high-precision SAR-ADC/DAC circuit of the first aspect of the present invention;

FIG. 6 is a schematic circuit diagram of a voltage-dividing resistor array according to a first aspect of the present invention;

FIG. 7 is a schematic diagram showing the structure of any one of the switch S8, the switch D _ x0-D _ x64 (the first logic switch element), and the switch D _ y0-D _ y64 (the second logic switch element) according to the first aspect of the present invention;

FIG. 8 is a circuit diagram of a first operational amplifier according to a first aspect of the present invention;

FIG. 9 is a circuit diagram of a second operational amplifier according to the first aspect of the present invention;

FIG. 10 is a schematic circuit diagram of a dynamic comparator according to a first aspect of the present invention;

fig. 11 is a schematic diagram illustrating a detailed structure of any one of the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6 and the seventh switch S7 according to the first aspect of the present invention;

FIG. 12 is a timing diagram of switches corresponding to S1-S11 when the ADC/DAC module resets the sample according to the first aspect of the present invention;

FIG. 13 is a timing diagram of the switches corresponding to S1-S11 when the ADC/DAC module keeps comparing according to the first aspect of the present invention;

FIG. 14 is a general diagram of the switch timing sequence of the ADC/DAC module completing one bit conversion cycle according to the first aspect of the present invention;

FIG. 15 is a clock duty cycle adjustment circuit employed in the first aspect of the present invention;

FIG. 16 is a clock duty cycle adjustment circuit employed in the first aspect of the present invention;

fig. 17 is a schematic diagram of clock signals generated by the clock duty ratio adjusting circuit used in the first aspect of the present invention.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

It is noted that relative terms such as "first," "second," and the like may be used to describe various components, but these terms are not intended to limit the components. These terms are only used to distinguish one component from another component. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

The resistance type high-speed high-precision SAR-ADC/DAC circuit is applied to a TRX chip of wireless charging equipment; the TRX chip is a chip integrated with a TX (power transmission) function and an RX (power reception) function.

As shown in fig. 4, the resistive high-speed high-precision SAR-ADC/DAC circuit of the present invention comprises a first operational amplifier BUF1 for performing a first process on a sampling voltage VIN and a second operational amplifier BUF2 for performing a second process on a reference voltage VREF; the ADC/DAC module is used for carrying out third processing on the reference voltage VREF subjected to the second processing and transferring the reference voltage subjected to the third processing and the sampling voltage VIN subjected to the first processing to the dynamic comparator COMP; the circuit also comprises a 12bits SAR logic device which is used for outputting parallel ADC <11:0> according to the serial SOB output by the dynamic comparator COMP; the ADC/DAC module selectively outputs a DAC signal (DAC _ OUT) after voltage division processing is carried OUT on the reference voltage VREF subjected to the second processing; wherein selectively outputting the DAC signal indicates that the DAC signal may be output or that the DAC signal is not output. The SAR-ADC/DAC circuit is used for processing a sampling voltage VIN and a reference voltage VREF respectively based on the double operational amplifiers, and is suitable for high-speed application; and a 12bits SAR logic device is matched with an ADC/DAC module, so that high-precision (12bits) output is provided on the basis of providing double functions of an ADC and a DAC. It should be noted that the DAC signal (DAC _ OUT) is selectively output based on the ADC/DAC module, i.e., the influence of the capacitive load of the DAC signal on the high-speed bandwidth can be prevented by not outputting the DAC signal during the ADC application.

As shown in fig. 5, the ADC/DAC module includes a timing switch component and a transfer component, wherein a plurality of switches in the timing switch component transfer the divided voltage equivalent values of the first processed sampling voltage VIN and the reference voltage formed by the third processing on the reference voltage onto the transfer component according to a first preset switching rule; the first preset switching rule is a switching rule (shown in fig. 12) that the switches need to meet in the reset sampling stage, that is, by combining the opening and closing of the switches in the time sequence switch assembly in the reset sampling stage, the equivalent value of the sampling voltage and the reference voltage respectively processed by different operational amplifiers is transferred to the transmission assembly, so that the difference value is transmitted to the corresponding input end of the dynamic comparator COMP.

Further, the timing switch assembly includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, and a seventh switch S7; the transfer component comprises a first transfer capacitor Ca and a second transfer capacitor Cb; one end of the first transfer capacitor Ca is simultaneously connected to one end of the first switch S1 and one end of the second switch S2, the other end of the first transfer capacitor Ca is simultaneously connected to the first input end Va of the dynamic comparator, one end of the third switch S3 and one end of the seventh switch S7, one end of the second transfer capacitor Cb is simultaneously connected to the first input end Vb of the dynamic comparator, one end of the fourth switch S4 and the other end of the seventh switch S7, the other end of the second transfer capacitor Cb is simultaneously connected to one end of the sixth switch S6 and one end of the fifth switch S5, and the other end of the fifth switch S5 is simultaneously connected to the other end of the sixth switch S6 and the other end of the second switch S2; the other end of the first switch S1 is simultaneously connected to a drain of a first NMOS transistor and one end of a third resistor R3, a source of the first NMOS transistor is simultaneously connected to a gate and a ground of the first NMOS transistor N1, the other end of the third resistor R3 is simultaneously connected to an output end of the first operational amplifier BUF1 and a second input end of the first operational amplifier, and a first input end of the first operational amplifier BUF1 is configured to receive a sampling voltage VIN; the ADC/DAC module comprises a third operational amplifier BUF3 with a first input end for receiving the reset voltage VRST, and a first output end of the third operational amplifier BUF3 is simultaneously connected with a second input end of the third operational amplifier BUF3, the other end of the third switch S3 and the other end of the fourth switch S4. The preferred embodiment performs specific circuit connection limitation on the timing switch assembly and the transmission assembly, and realizes the following principle: after the sampling voltage VIN/the reference voltage VREF/the reset voltage VRST is driven by the high-bandwidth operational amplifier, under the control of the S1-S7 timing switch, the difference between the sub-voltages of the sampling voltage VIN and the reference voltage VREF after the first processing is transferred to the input end of the dynamic comparator through the first transfer capacitor Ca and the second transfer capacitor Cb, and finally the serial SOB is converted. The SOB bits are output via the 12bits SAR logic in parallel ADC <11:0> while the reference voltage for the next bit is adjusted. The sampling voltage VIN is converted from the most significant bit ADC <11> to the least significant bit ADC <0> bit by bit, and finally the parallel ADC <11:0> and the serial SOB are output. Wherein, the serial SOB represents an SOB signal applicable to serial transmission; parallel ADCs represent ADC signals suitable for parallel transmission. The divided voltage of the reference voltage VREF is a voltage formed by performing a third process on the reference voltage by a voltage dividing resistor array in the ADC/DAC module, and the third process is a voltage dividing process.

As shown in FIG. 5, the ADC/DAC module includes a 2 equivalent ¹² And the voltage dividing resistor array is used for dividing the reference voltage VREF subjected to the second processing to form a partial voltage of the reference voltage, the partial voltage of the reference voltage is used as a DAC signal, and the DAC signal is selectively output. Namely, the ADC/DAC module divides the reference voltage VREF processed by the second operational amplifier BUF2 through a built-in voltage dividing resistor array Vrefdivider; so as to use the voltage subjected to voltage division processing as a DAC signal, and then selectively output or not output.

Further, the 12bits _ SAR logic is based on the selection result of the received ADC _ DAC _ SEL selection signal, if the selection result is the DAC application, the 12bits _ SAR logic selects the DAC <11:0> signal input to output the parallel ADC <11:0>, the voltage dividing resistor array Vref divider in the ADC/DAC module divides the second processed reference voltage Vref to form a divided voltage of the reference voltage, and the divided voltage of the reference voltage is output as a DAC signal (DAC _ OUT).

Further, the ADC/DAC module selects the SOB signal input and outputs the parallel ADC <11:0> if the selection result is ADC application based on the received selection result of ADC _ DAC _ SEL.

As shown in fig. 6, the voltage dividing resistor array includes 64 resistors Rx connected in series with each other, a first logic switch component for selecting a certain resistor of the 64 resistors Rx, 64 resistors Ry connected in series with each other, and a second logic switch component for selecting a certain resistor of the 64 resistors Ry as a connection point; the first logical switch assembly includes 65 switches D _ x0-D _ x 64; the second logical switch assembly includes 65 switches D _ y0-D _ y 64. The high-order 64 resistors Rx and the low-order 64 resistors Ry are combined by the 65 switches D _ x0-D _ x64 and the 65 switches D _ x0-D _ x64, so that the equivalent output 2 is realized ¹² (4096) The resistors divide the voltage. The resistor array only needs 128 resistors, 130 switches and related logic circuitsCan realize 2 ¹² A resistor divides the voltage in a manner of 4096 (2) ¹² ) The layout area is greatly saved by the series resistors.

In order to output the divided voltage of the DAC signal or the reference voltage with high accuracy, the ratio of the resistor Rx and the resistor Ry needs to satisfy

n represents the resistance voltage division precision and can be greater than or equal to 99%; the calculation of this ratio can be done with a higher accuracy of analysis as follows: for the reference voltage precision, the LSB bit of the ADC/DAC is generated by the Ry resistor array, which requires that the resistance value of the Ry resistor array after being connected in parallel with a certain section of Rx resistor is almost equal to the resistance value of the Rx resistor, so as to ensure accurate voltage division of the high-bit resistor, and the precision of the voltage division of the resistor shown in fig. 6 is as follows:

and the theoretical resistance voltage division precision of the 12bits ADC is as follows:

if the actual accuracy is required to reach n of the theoretical value, then:

the parameters of the resistors Rx and Ry, the switches D _ x0-D _ x64 and the 65 switches D _ y0-D _ y64 need to be set by considering the following two aspects: 1.equivalence 2 ¹² The accuracy of individual resistance voltage division; 2. the time constants of the resistor, the switch parasitic capacitor and the transfer capacitor; for each bit conversion of the ADC, during the sampling reset phase, a new partial voltage of the reference voltage (switching of the switches D _ x0-D _ x64 and D _ y0-D _ y 64) needs to be output, which means that a certain settling time needs to be given to the partial voltage of the reference voltage. For high speed applications of the ADC, a faster settling speed is required, which includes the time constants of the resistor Rx and the parasitic capacitance of the switch D _ x0/64, and the time constants of Ry and the parasitic capacitance of D _ y0/64, especially the latter, which directly outputs the divided voltage of the reference voltage. To increase the settling speed, a time constant is proposed

ADC _ CLK represents the clock frequency externally provided to the ADC/DAC module; in order to reduce the RC time constant as much as possible and improve the stable speed, the switches D _ x0-D _ x64 and D _ y0-D _ y64 both use N-channel enhancement type MOS transistors (as shown in FIG. 7), and the reference voltage VREF corresponding to the switches cannot be set too high in consideration of the body effect of NMOS, and the set VREF is preferably set<VDD/2(VDD block supply voltage). In the design of the parameters of the switches D _ x0-D _ x64, the error of 64 resistors Ry caused by the on-resistance Ron is considered as well as the gate capacitance as low as possible; and for the parameter design of D _ y0-D _ y64, the gate capacitance is mainly considered, and the on-resistance does not influence the precision of the ADC/DAC. For an NMOS, its gate capacitance is proportional to W × L and its on-resistance is inversely proportional to W/L. In addition, the time constants of the resistors Rx and Ry and the transfer capacitor Ca/Cb are also noted. When the DAC is applied, the size of a capacitive load (such as the input end of a differential pair) of the DAC _ OUT output end is unknown, and the influence of the capacitive load on the high bandwidth of the ADC needs to be prevented.

As shown in fig. 5, a switching device S8 is disposed at the output end of the voltage dividing resistor array Vref divider to selectively output DAC signals; preferably, the switching device S8 may be an N-channel enhancement MOS transistor (as shown in fig. 7) to serve the purpose of switching or transmission gate. Generally, a conventional transmission gate is in a structure that an NMOS and a PMOS are connected in parallel, and an N-channel enhancement type MOS transistor is selected as the switching device S8, so that only the NMOS is utilized, and the PMOS part is abandoned, so that the parasitic capacitance of the switch or the transmission gate is reduced, and the high-speed effect is achieved. Wherein, A and B are the source and drain of the N-channel enhancement MOS transistor respectively, and can also be understood as the input or output of the transmission gate; CN is the grid of the N-channel enhancement type MOS tube, here is the control signal of the transmission gate, when the high level is high, the transmission gate is opened, A, B is conducted, when the CN is low, A, B is disconnected. Wherein, W, L is the minimum of N-channel enhancement type MOS pipe, W and L are the width and length of the grid electrode of the N-channel enhancement type MOS pipe, in order to reduce the parasitic capacitance.

As shown in fig. 8, a specific circuit of the first operational amplifier BUF1 is shown; MN represents an N-channel enhanced MOS tube, and MP represents a P-channel enhanced MOS tube; different numbers carried behind MN and MP represent MOS tubes at different connection positions. Specifically, the first operational amplifier BUF1 includes a first P-channel portion including a plurality of P-channel enhancement type MOS transistors, specifically including MP0, MP1, MP2, MP3, MP4, and MP20-MP32, a first N-channel portion, and two miller capacitors Cc 1; wherein, the gate of MP1 is used to receive Vinp voltage (the sampled voltage VIN without the first processing is taken as Vinp voltage), and the gate of MP2 is used to receive Vinn voltage. The first N-channel part comprises a plurality of N-channel enhancement type MOS tubes, specifically comprising MN0 and MN20-MN 35. One end of the miller capacitor Cc1 is simultaneously connected with the drain of MP30 and the source of MP31, the other end is simultaneously connected with one end of the resistor Rc1 and one end of the other miller capacitor Cc1, and the other end of the resistor Rc1 outputs Vout. The first operational amplifier BUF1 mainly functions to amplify the differential voltage between the sampling voltages VIN and Vinn entering through the Vinp terminal for output, so as to ensure stability while achieving high bandwidth.

The first operational amplifier BUF1 is a PMOS differential input, an AB output and two-stage amplification, is suitable for low input voltage and capacitive load output, can realize low system offset by two-stage amplification and is also beneficial to loop stability. For a two-stage amplification loop, there are two poles of miller capacitance and output, and two key parameters, GBW (unity gain bandwidth) and PM (phase margin). GBW determines the response speed of the first operational amplifier BUF1, and the higher GBW, the faster and smoother the output. The PM determines the stability of the loop and also affects how much the output ripple is (before stabilizing), which is related to the location of the output pole. In FIG. 8, GBW1 of BUF1 is calculated as follows:

the output pole Pout1 is calculated as follows:

for GBW1, by adjusting g _MP1/2 And C _c1 To achieve a high bandwidth of BUF1, where g _MP1/2 Is calculated as (k' _p As a process parameter):

thus, by increasing the tail current I _MP3 (the current generated by the P-channel enhancement type MOS tube MP 3), the width-to-length ratio of MP1/2(MP1/2 represents MP1 or MP2, because the parameters of the two P-channel enhancement type MOS tubes MP1 and MP2 are the same, and one of the two P-channel enhancement type MOS tubes can be selected) is increased, and the Miller capacitance C is reduced _c1 The high bandwidth of BUF1 can be achieved. Namely GBW1 (unity gain bandwidth) of BUF1 is preferably:

GBW1＞2×ADC_CLK(2-4)

for the output pole P _OUT1 Wherein C is _OUT The capacitor mainly comprises a first transfer capacitor Ca and a second transfer capacitor Cb. The Poutl output pole affects the PM (phase margin) size and the output ripple, and 2-3 times GBW1 Pout1 is generally preferred, which can achieve better loop stability and less ripple. Similarly, the width-to-length ratio (W/L) of MP0 and the width-to-length ratio (W/L) of MN0 are increased to increase (g) _MPO +g _MN0 ) To satisfy P _OUT1 And (4) setting the frequency point.

It should be noted that, as for the third operational amplifier BUF3, the specific structure is the same as that of the first operational amplifier BUF1, that is, the internal circuit structure is the same as that of the first operational amplifier BUF1 (fig. 8), so that the third operational amplifier BUF3 can achieve high bandwidth for the reset voltage VRST and ensure stability, which is not described herein again.

FIG. 9 is a schematic diagram of the circuit connection adopted by the second operational amplifier BUF 2; the second operational amplifier BUF2 comprises a second P-channel part, a second N-channel part and a Miller capacitor Cc2, wherein the second P-channel part comprises MP5, MP50-MP 54; the second N-channel portion comprises MN1-MN3, MN40-MN 41; wherein, the gate of MN2 is used for receiving Vinn voltage, the gate of MN1 is used for receiving Vinp voltage (the reference voltage VREF without the second processing is input to the gate of MN1 as Vinp voltage); one end of the miller capacitor Cc2 is connected to the drain of MP53 and the source of MP54, and the other end outputs Vout through a resistor Rc 2. The second operational amplifier BUF2 is used for amplifying the differential voltage between Vinp voltage and Vinn voltage for output, so as to ensure stability while realizing high bandwidth.

Similarly, by increasing the tail current I _MN3 (current generated by an N-channel enhancement type MOS tube MN 3), the width-to-length ratio of MN1/2(MN1/2 represents MN1 or MN2, and one of the two N-channel enhancement type MOS tubes MN1 and MN2 can be selected optionally because the parameters are the same) is increased, the Miller capacitance Cc2 is reduced, and the high bandwidth of BUF2 can be realized. Namely GBW2 (unity gain bandwidth) of BUF2 is preferably: GBW2>2 ADC _ CLK; and the output pole Pout2 of the second operational amplifier BUF2 is 2-3 times GBW 2; that is, by increasing the tail current, increasing the width-to-length ratio of MN1/2, and reducing the Miller capacitance, the high bandwidth of BUF2 can be realized; the frequency bin setting of Pout2 is satisfied by increasing the width-to-length ratio of MP 5.

FIG. 10 is a schematic diagram showing the circuit connections of the dynamic comparator; MN represents an N-channel enhanced MOS tube, and MP represents a P-channel enhanced MOS tube; different numbers carried behind MN and MP represent MOS tubes at different connection positions. Specifically, the method comprises the following steps: the dynamic comparator COMP comprises an amplifying part (left part of a dotted line) for amplifying a difference between a divided voltage of a sampling voltage and a reference voltage, and a dynamic transient comparison part (right part of the dotted line), wherein the amplifying part comprises MN4-MN7, MN10-MN11, MP50 and MP51, a source of MN10 and a drain of MN10 are simultaneously connected with a gate of an input terminal S10 and MN11 of a third inverter B3 and a gate of MN4, and gates of MP50 and MP51 are simultaneously connected with gates of an input terminal S10 and MN5 of a fourth inverter B4; the dynamic transient comparison part comprises MP6-MP11, MN12-MN16, a first inverter B1, a second inverter B2, a first NAND gate C1 and a second NAND gate C2; the gates of MP6, MP7, MP8 and MP9 are all connected to the output terminal S11 of the fifth inverter B5, and the gate of MN12 is connected to the output terminal S11 of the fifth inverter B5; the third inverter B3, the fourth inverter B4 and the fifth inverter B5 are connected in series, the first input end of the first NAND gate C1 is connected with the drain of the MP11 and the drain of the MN16 at the same time through the first inverter B1, the second input end of the first NAND gate C1 is connected with the output end of the second NAND gate C2, the second input end of the second NAND gate C2 is connected with the gate of the MP11 and the gate of the MN16 at the same time through the second inverter B2, and the output end of the first NAND gate C1 outputs serial SOB.

This patent uses a dynamic comparator as shown in fig. 10 to accomplish high speed ADC conversion. The arrangement of MOS transistors is mainly utilized, the large width-length ratio of MN13 and MN14 can be set, the correct turning of the instantaneous comparator is facilitated, and meanwhile MN10 and MN11 are convenient to match with MN13 and MN 14. The influence of the process corner can be avoided, the layout matching layout is convenient, and the layout area is saved.

In the circuit of fig. 10, the differential voltage between Vinp and Vinn is amplified by several tens of times by different discharge rates of MN6 and MN 7. The gate voltages of MN13 and MN14 are discharged to gate capacitances of MN10 and MN11 with negative potentials through MN6 and MN7 from a reset value VDD at the beginning, and due to different potentials of Vinp and Vinn, the discharging speeds of MN6 and MN7 are different, so that the amplification of the differential voltage on the gates of MN13 and MN14 is dozens of times. Since the gate charges of MN13 and MN14 are transferred to the gates of MN10 and MN11, in order to ensure the matching degree of MN13 and MN14 with MN10 and MN11, the same W and L may be used, that is, the gate width dimensions and the length dimensions of the four mos tubes of MN13, MN10, MN14 and MN11 are the same.

In fig. 4 and 5, the S1-S7 timing switch control functions to transfer the sampling voltage/reset voltage/reference voltage to the first transfer capacitor Ca and the second transfer capacitor Cb. In view of the influence of the gate charge transfer back and forth of the switch on the first and second transfer capacitances Ca and Cb during the switching, in order to reduce the influence, the S1-S7 sequential switch adopts a switch structure as shown in fig. 11. As shown in fig. 11, the first switch S1 includes an N-channel enhanced MOS transistor NSW1, an N-channel enhanced MOS transistor NSW2, and an N-channel enhanced MOS transistor NSW3, where the source of NSW1 is connected to the drain of the connection terminal A, NSW3, the source of NSW3 is connected to the source of the connection terminal B, NSW2, the gate of NSW2 is connected to the gates of the connection terminals CP and NSW1, the gate of NSW3 is connected to the CN terminal, and the drains of NSW1 and NSW2 are floating; when CN end is in high level, the transmission gate is opened, and the connection end A, B is conducted; when CN terminal is at low level, connection A, B is open. The gates of NSW1, NSW2, and NSW3 are the same in length and width dimensions. The finger of NSW3 was 2 times that of NSW1 and NSW2 (as shown in fig. 11). Since the connections CP, CN are 180 degrees out of phase, the gate charge during switching is only transferred back and forth between NSW1, NSW2, and NSW3, which avoids the influence on the charges of the first and second transfer capacitors Ca, Cb.

Similarly, in fig. 5, the source of the first NMOS transistor N1 is simultaneously connected to the gate of the first NMOS transistor N1 and ground, and the other end of the third resistor R3 is simultaneously connected to the output terminal of the first operational amplifier BUF1 and the second input terminal of the first operational amplifier; the arrangement of the first NMOS transistor N1 based on the third resistor R3 is to form an approximate match with the resistor and the switch shown in fig. 6, so that approximately the same RC is formed at both ends of the first transfer capacitor Ca and the second transfer capacitor Cb, and it is ensured that Ca and Cb have approximately the same transferred charge.

As shown in fig. 12, when the timing switch components S1-S7, S9 (representing the input terminal of the third inverter), S10 (representing the input terminal of the fourth inverter), and S11 (representing the output terminal of the fifth inverter) enter the reset sampling phase, S1, S5, S3, S4, and S7 are turned on, S2 and S6 are turned off, S9 is at a high level, and S10 and S11 are at a low level; the switches are not in sequence during the reset sampling phase. During this period, the sampling voltage/reset voltage/reference voltage is transmitted to the first transfer capacitor Ca and the second transfer capacitor Cb through the corresponding first operational amplifier, the second operational amplifier and the third operational amplifier, and a certain settling time is required to ensure the ADC accuracy. (in FIG. 12, the rising edge of S1-S7 indicates ON, and the falling edge indicates OFF). at the same time, the dynamic comparator is reset to zero, and is ready for the next bit of the ADC to be converted.

As shown in fig. 13, when the timing switch components S1-S7, S9 (representing the input terminal of the third inverter), S10 (representing the input terminal of the fourth inverter), and S11 (representing the output terminal of the fifth inverter) keep the comparison phase, S1 and S5 are synchronously turned off, S3 and S4 are synchronously turned off, S7 is turned off, S2 and S6 are synchronously turned on, S9 is at a low level, S10 is at a high level, and S11 is at a high level. In the comparison stage, the switching timing is in the preset sequence shown in fig. 13, and the interval between every two switching timings is about 1ns (about 1 ns), specifically: when the comparison phase is maintained, the trigger time of synchronous closing of S1 and S5 is 1ns faster than that of synchronous closing of S3 and S4, the trigger time of synchronous closing of S3 and S4 is 1ns faster than that of closing of S7, the trigger time of closing of S7 is 1ns faster than that of synchronous turning on of S2 and S6, the trigger time of synchronous turning on of S2 and S6 is 2ns faster than that of S9 at a low level, the trigger time of S9 at a low level is 1ns faster than that of S10 at a high level, and the trigger time of S10 at a high level is 2ns faster than that of S11 at a high level. The intervals of S2, S6 and S9 and the intervals of S10 and S11 are slightly longer (for example, about 2 ns) to allow time for voltage stabilization and differential amplification.

It should be noted that, as shown in fig. 14, in a bit conversion period, the holding comparison phase is dynamically and instantaneously completed without leaving too long, while the resetting sampling phase requires as long a time as possible to complete the stabilization of the sampling voltage and the reference voltage on the transfer capacitor Ca/Cb. As shown in fig. 15, the clock duty cycle adjusting circuit includes an inverter and a nand gate, and 2n inverters are connected in series between the output end of the inverter and the second input end of the nand gate; the output end of the inverter is also connected with the first input end of the NAND gate, and the clock duty cycle adjusting circuit can achieve the waveform that the duty cycle of the ADC _ CLK _ DLY is larger than 50% (shown in figure 17), thereby achieving the technical effect that in a bit conversion period, the comparison stage is dynamically and instantly completed without leaving too long time.

As shown in fig. 16, another clock duty cycle adjusting circuit is provided, the clock frequency circuit includes three inverters, MP12, MN17, MN18 and MP 13; one end of one inverter is connected with the other inverter in series, the other end of the inverter is connected with the grid of the MP12 and the grid of the MN17 at the same time, the source of the MP12 is connected with the source of the MP13 and the drain of the MP13 at the same time, and the grid of the MP13 is connected with the drain of the MP12, the drain of the MN17, the grid of the MN18 and the input end of the rest one inverter at the same time; by using the clock duty ratio adjusting circuit, the waveform (shown in figure 17) with the duty ratio of ADC _ CLK _ DLY larger than 50% can be achieved, so that the technical effect that in a bit conversion period, the comparison stage is dynamically and instantly completed without long time is achieved. ADC _ CLK is a 50% duty cycle clock provided outside the ADC system, and ADC _ CLK _ DLY is the clock used by the actual ADC. Wherein, the high level of the clock represents entering a reset sampling phase, and the low level represents entering a hold comparison phase.

The ADC/DAC module of this patent design development not only is applied to high-speed ADC, also can be applied to low-speed ADC, especially can set up low pass filter module in order to eliminate high frequency interference when low-speed is used at sampling voltage VIN input, specifically: as shown in fig. 5, the low-pass filtering module includes a resistor R100, a capacitor C100, and an MN100 (N-channel enhancement MOS transistor); one end of a capacitor C100 is connected with a first input end of the first operational amplifier BUF1, one end of a resistor R100 and a drain electrode of the MN100 at the same time, a source electrode of the MN100 is connected with the other end of the resistor R100 at the same time to form a common end for receiving a sampling voltage VIN, the other end of the capacitor C100 is grounded, and a grid electrode of the MN100 is used for receiving a HISPEED input signal; specifically, when the high-speed application is performed, the high-speed input signal is at a high level, MN100 is turned on, resistor R100 is short-circuited, and the equivalent low-pass filtering module is turned off, so that the high-speed application is not affected; when the high-speed filter is applied at a low speed, the HISPEED input signal is at a low level, the MN100 is disconnected, and the low-pass filter module is started to filter high-frequency interference.

The actual offset of the operational amplifier and the dynamic comparator is not eliminated by the design, which is the random offset which can not be avoided in the actual process after the offset of the system is eliminated by optimizing the circuit and layout design. Therefore, in practical application, it is suggested to preset known sampling voltage, calculate and store the offset of the ADC conversion result, and correct the ADC result of the actual voltage by the chip built-in software in the later stage to solve the ADC offset problem.

A second aspect of the present invention provides a wireless charging device, including a wireless charging body, wherein the wireless charging body is internally provided with a resistive high-speed high-precision SAR-ADC/DAC circuit as described in the first aspect; based on the selected resistance type high-speed high-precision SAR-ADC/DAC circuit, the formed wireless charging equipment is easy to miniaturize and achieves high charging efficiency.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. A resistance type high-speed high-precision SAR-ADC/DAC circuit is characterized by comprising a first operational amplifier and a second operational amplifier, wherein the first operational amplifier is used for carrying out first processing on a sampling voltage and transmitting the sampling voltage to an ADC/DAC module, and the second operational amplifier is used for carrying out second processing on a reference voltage and transmitting the reference voltage to the ADC/DAC module;

the ADC/DAC module is used for carrying out third processing on the reference voltage subjected to the second processing, transferring the reference voltage subjected to the third processing and the sampling voltage subjected to the first processing to the dynamic comparator, and the dynamic comparator outputs the converted serial SOB to the 12-bit SAR logic device so that the 12-bit SAR logic device outputs a parallel ADC; the ADC/DAC module is also used for selectively outputting DAC signals after voltage division processing is carried out on the reference voltage subjected to the second processing;

the ADC/DAC module comprises a time sequence switch assembly and a transfer assembly, wherein a plurality of switches in the time sequence switch assembly transfer the divided voltage equivalent values of the first processed sampling voltage and the reference voltage to the transfer assembly according to a first preset switching rule;

the timing switch assembly includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, and a seventh switch S7; the transfer component comprises a first transfer capacitor Ca and a second transfer capacitor Cb;

one end of the first transfer capacitor Ca is simultaneously connected to one end of the first switch S1 and one end of the second switch S2, the other end of the first transfer capacitor Ca is simultaneously connected to the first input end Va of the dynamic comparator, one end of the third switch S3 and one end of the seventh switch S7, one end of the second transfer capacitor Cb is simultaneously connected to the first input end Vb of the dynamic comparator, one end of the fourth switch S4 and the other end of the seventh switch S7, the other end of the second transfer capacitor Cb is simultaneously connected to one end of the sixth switch S6 and one end of the fifth switch S5, and the other end of the fifth switch S5 is simultaneously connected to the other end of the sixth switch S6 and the other end of the second switch S2.

2. The resistive high-speed high-precision SAR-ADC/DAC circuit according to claim 1, wherein the other end of the first switch S1 is connected to the drain of a first NMOS transistor and one end of a third resistor R3, the source of the first NMOS transistor is connected to the gate of the first NMOS transistor and ground, the other end of the third resistor R3 is connected to the output end of the first operational amplifier and the second input end of the first operational amplifier, and the first input end of the first operational amplifier is used for receiving a sampling voltage VIN.

3. The resistive high-speed high-precision SAR-ADC/DAC circuit of claim 1, wherein the ADC/DAC module comprises 2 equivalent ¹² And the voltage dividing resistor array is used for dividing the reference voltage VREF subjected to the second processing.

4. The resistive high-speed high-accuracy SAR-ADC/DAC circuit of claim 3 wherein the divider resistor array comprises 64 resistors Rx in series relationship with each other, a first logic switch component for selecting a certain resistor of the 64 resistors Rx, 64 resistors Ry in series relationship with each other, and a second logic switch component for selecting a certain resistor of the 64 resistors Ry as a connection point.

5. The resistive high-speed high-precision SAR-ADC/DAC circuit of claim 3, wherein the output end of the voltage-dividing resistor array is connected with an eighth switch S8, and the DAC signal is output when the eighth switch S8 is closed.

6. The resistive high-speed high-precision SAR-ADC/DAC circuit according to claim 1, wherein the ADC/DAC module comprises a third operational amplifier BUF3 having a first input terminal for receiving a reset voltage VRST, and a first output terminal of the third operational amplifier BUF3 is connected to the second input terminal of the third operational amplifier BUF3, the other terminal of the third switch S3 and the other terminal of the fourth switch S4 at the same time.

7. The resistive high-speed high-precision SAR-ADC/DAC circuit of claim 1, wherein the dynamic comparator comprises an amplifying section for amplifying a difference between the divided voltages of the first processed sampling voltage and the reference voltage and a dynamic transient comparing section for comparing an amplified voltage output by the amplifying section.

8. A wireless charging device comprising a resistive high-speed high-precision SAR-ADC/DAC circuit according to any of claims 1-7.