CN113270999B

CN113270999B - Current-limiting configuration chip and switching power supply system

Info

Publication number: CN113270999B
Application number: CN202110810692.6A
Authority: CN
Inventors: 陈博; 李瑞平; 刘彬
Original assignee: Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Current assignee: Shanghai Xinlong Semiconductor Technology Co ltd Nanjing Branch
Priority date: 2021-07-19
Filing date: 2021-07-19
Publication date: 2021-10-01
Anticipated expiration: 2041-07-19
Also published as: CN113270999A

Abstract

In the current-limiting configuration chip and the switching power supply system, the current-limiting configuration chip comprises a first power tube, a second power tube, an input comparison module, a counting comparison module, a logic control module and a current-limiting configuration module; when the current-limiting configuration module detects that the driving signal output by the counting comparison module is not inverted, the driving logic control module maintains the allowable current of the first power tube at the first current-limiting current, so that the current-limiting configuration chip can meet various characteristic loads and use conditions at the initial power-on stage, the on-load starting is realized, and the output voltage logic relationship of the current-limiting configuration chip can be normally established; when the current-limiting configuration module detects that the driving signal is turned over, the driving logic control module adjusts the allowable current of the first power tube into a second current-limiting current, so that the current-limiting configuration chip can limit the maximum current flowing through the first power tube in a short circuit abnormal state, and the output current of the current-limiting configuration chip is controllable.

Description

Current-limiting configuration chip and switching power supply system

Technical Field

The invention relates to the technical field of power supply chips, in particular to a current-limiting configuration chip and a switching power supply system.

Background

In the field of power supply chips, in order to ensure safe and stable operation of a power supply, the power supply chip itself has a current limiting measure, the maximum output current value of a power supply system is limited by limiting the maximum switching current of an internal power tube, and the maximum switching current which flows through the power tube is generally limited and called as the maximum current limiting current of the power supply chip.

In general, the situation that the output current is too large due to the problems of short circuit and the like is prevented by limiting the maximum switching current of the power tube, so that the failure of a power supply chip or a power supply system is avoided. The general measure is that the current limiting current of the chip in normal operation is set to be slightly larger than the maximum application current of the system design, namely the current limiting current of the chip is just close to enough, so that the power supply chip system can obtain sufficient overcurrent protection.

However, due to structural limitations of the power supply system, the power supply system needs to simultaneously charge the load and the output capacitor at the initial stage of power-on, a transient current flowing through a power tube in the power supply chip at the initial stage of power-on of the power supply system is greater than an actual working current, and if a current-limiting current of the power supply chip is configured to just meet a maximum current for the load, the power supply chip may have a situation that an output voltage cannot be normally established, and a repeated restart may occur in the power supply chip power-on process, which finally results in that the power supply system cannot normally work.

In view of this, how to set the current-limiting current of the power chip so that the power chip can normally establish the system logic voltage relationship under various test conditions and avoid the occurrence of the power system failure caused by the excessive output current due to the short-circuit problem of the power chip under the condition of the normal logic voltage relationship is an urgent problem to be solved.

Disclosure of Invention

The invention aims to provide a current-limiting configuration chip and a switching power supply system, and aims to solve the problem that the logic voltage relation of the power supply chip cannot be normally established because the current-limiting current of the conventional power supply chip is set to be smaller or set to be a fixed value possibly cannot meet the actual requirement; the second purpose is to solve the problem that the switch power supply system fails due to overlarge output current caused by the short circuit problem of the conventional power supply chip under the condition of normal logic voltage relation.

To solve the above technical problem, according to an aspect of the present invention, there is provided a current-limiting configuration chip applied to a switching power supply system, the current-limiting configuration chip including:

the input comparison module is configured to acquire power supply voltage input to the current-limiting configuration chip and reference voltage with sawtooth waveform of an externally provided signal in real time, and generate a comparison signal with pulse width changing along with the power supply voltage according to the power supply voltage and the reference voltage;

the counting comparison module is used for fixedly outputting a driving signal and internally setting a detection period comprising first detection time; the counting comparison module is used for detecting the pulse number of the comparison signal according to the first detection time, recording once pulse width data when the pulse number is detected to be an expected value, further carrying out difference amplification operation on the pulse width data corresponding to the detection period group to generate a difference amplification value, and turning over the driving signal when the difference amplification value is smaller than or equal to a threshold value; when the counting comparison module detects that the number of pulses is an expected value, the detection period further includes a second detection time after the first detection time, and the pulse width data represents a pulse width of the comparison signal in the second detection time; the counting comparison module is used for starting a detection period with the number of the detected pulses as an expected value for the first time, and sequentially taking two adjacent detection periods as the detection period groups, wherein the two adjacent detection period groups are not overlapped.

A first power tube and a second power tube; the input end of the first power tube is used for obtaining the power supply voltage, and the output end of the first power tube is connected with the output end of the second power tube and then is commonly connected to the output end of the current-limiting configuration chip; the input end of the second power tube is grounded;

the logic control module is accessed to the control end of the first power tube and the control end of the second power tube and is used for controlling the first power tube and the second power tube to be alternately opened and closed;

the current limiting configuration module is used for controlling the logic control module to maintain the allowed current of the first power tube as a first current limiting current when the driving signal is not inverted; when the driving signal is turned over, the logic control module is driven to adjust the allowed current of the first power tube into a second current-limiting current; the second current-limiting current is less than the first current-limiting current.

Optionally, the first power tube is a PMOS tube, the input end of the first power tube is a source electrode of the PMOS tube, the output end of the first power tube is a drain electrode of the PMOS tube, and the control end of the first power tube is a gate electrode of the PMOS tube; the second power tube is an NMOS tube, the output end of the second power tube is the drain electrode of the NMOS tube, the input end of the second power tube is the source electrode of the NMOS tube, and the control end of the second power tube is the grid electrode of the NMOS tube.

Optionally, the current-limiting configuration module is configured to implement configuration of a second current-limiting current according to a resistance value of an adjustable resistor, where one end of the adjustable resistor is connected to the current-limiting configuration module, and the other end of the adjustable resistor is grounded; the second current-limiting current is equal to the product of the resistance value of the adjustable resistor and a preset coefficient.

Optionally, the current-limiting configuration chip includes a soft start module, an input end of the soft start module is configured to obtain the power voltage, an output end of the soft start module is connected to the logic control module, and the soft start module is configured to send a start signal to the logic control module according to a real-time magnitude of the power voltage, so as to drive the logic control module to adjust a switching frequency at which the first power tube and the second power tube are alternately turned on and turned off; the frequency of the start signal is used to be equal to the signal frequency of the reference voltage.

Optionally, the input comparing module includes: the circuit comprises an amplifier, a comparator, a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is used for acquiring the power supply voltage; the second end of the first resistor is connected with the first end of the second resistor, and the second end of the first resistor and the first end of the second resistor are connected to the non-inverting input end of the amplifier together; the second end of the second resistor is grounded; the first end of the third resistor is connected to the inverting input end of the amplifier, and the second end of the third resistor is grounded; a first end of the fourth resistor is connected to an inverting input end of the amplifier, and a second end of the fourth resistor is connected to an output end of the amplifier; the output end of the amplifier is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is used for obtaining the reference voltage, and the output end of the comparator is configured as the output end of the input comparison module.

Optionally, the count comparing module includes a shift register unit, a differential amplifier, a threshold comparator, a pulse counter and a logic switch, and the shift register unit includes a receiving buffer, a first register and a second register;

the pulse counter is used for detecting the pulse number of the comparison signal according to the first detection time, and outputting a one-time trigger signal when the pulse number is detected to be an expected value;

the receiving buffer is used for receiving the trigger signal to record the pulse width data and register the pulse width data in the first register;

the first register is used for shifting the pulse width data corresponding to the detection period before the detection period group which is originally registered into the second register when the pulse width data corresponding to the detection period after the detection period group is registered;

the differential amplifier is used for carrying out difference amplification operation on the pulse width data in the first register and the pulse width data in the second register so as to generate the differential amplification value;

the threshold comparator fixedly outputs the driving signal, is internally provided with the threshold, and inverts the driving signal when the obtained differential amplification value is smaller than or equal to the threshold;

the first end of the logic switch is used for acquiring the driving signal, and the second end of the logic switch is used for being connected with the current limiting configuration module;

after the pulse counter outputs the trigger signal twice in the detection period group, the logic switch is closed; the pulse counter is used for resetting when the driving signal is not turned over after the detection of the number of pulses at one time is finished; when the driving signal is turned over, the pulse counter stops detecting the pulse number of the comparison signal, and the logic switch is kept closed; when the differential amplification value is larger than the threshold value, the first register and the second register are reset, and the logic switch is disconnected.

Optionally, a plurality of the detection periods are continuous; when the counting and comparing module detects that the pulse number is an expected value, the detection period is the sum of the corresponding first detection time and the corresponding second detection time; the first detection time and the second detection time are both integral multiples of the period of the reference voltage, the integral multiples of the first detection time and the period of the reference voltage are equal to the expected value, and the pulse width data represent the pulse width of the period of a second reference voltage corresponding to the comparison signal in the second detection time.

Based on another aspect of the present invention, the present invention further provides a switching power supply system, which includes a first capacitor circuit, a second capacitor circuit, an inductor, and the current limiting configuration chip as described above; the first end of the first capacitor circuit is connected with the input end of the current-limiting configuration chip, and the second end of the first capacitor circuit is grounded; the first end of the inductor is connected with the output end of the current-limiting configuration chip, the second end of the inductor is connected with the first end of the second capacitor circuit, and the second end of the second capacitor circuit is grounded; when the first power tube is started and the second power tube is stopped, the first capacitor circuit, the first power tube, the inductor and the second capacitor circuit form a first loop; when the first power tube is turned off and the second power tube is turned on, the second power tube, the inductor and the second capacitor circuit form a second loop.

Optionally, the current-limiting configuration chip includes an output feedback module, a fifth resistor, and a sixth resistor; the fifth resistor and the sixth resistor are connected in series and then connected in parallel with the second capacitor circuit, and the output feedback module is connected to a common line of the fifth resistor and the sixth resistor; the output feedback module is used for detecting and collecting the load voltage output by the switching power supply system in real time according to the sixth resistor, and forming a feedback signal to the logic control module according to the load voltage so as to drive the logic control module to adjust the duty ratio of the first power tube and the second power tube.

Optionally, the switching power supply system includes a clamp capacitor, the current-limiting configuration chip is provided with a clamp capacitor end connected to the logic control module, and the clamp capacitor is coupled between the input end of the current-limiting configuration chip and the clamp capacitor end.

In summary, in the current-limiting configuration chip and the switching power supply system provided in the present invention, the current-limiting configuration chip includes a first power transistor, a second power transistor, an input comparison module, a count comparison module, a logic control module, and a current-limiting configuration module; the input comparison module acquires the input power voltage and the external reference voltage in real time to generate a comparison signal, the counting comparison module detects the pulse width of the comparison signal at second detection time of two sub-detection periods before and after, and the counting comparison module compares the pulse width with a threshold value according to the change of the pulse width at the two second detection times to output a driving signal; when the driving signal is not turned over, the current-limiting configuration module drives the logic control module to maintain the allowable current of the first power tube at the first current-limiting current, so that the current-limiting configuration chip can meet various characteristic loads and use conditions at the initial power-on stage, the on-load starting is realized, and the output voltage logic relationship of the current-limiting configuration chip can be normally established; when the driving signal is turned over, the comparison signal is considered not to be changed any more, the current limiting configuration module drives the logic control module to adjust the allowable current of the first power tube into the second current limiting current, so that the current limiting configuration chip can limit the maximum current flowing through the first power tube in a short circuit abnormal state, and the output current of the current limiting configuration chip is ensured to be controllable. The counting comparison module can also enable the current-limiting configuration chip to have the function of power-on reset again to work under the first current-limiting current under the condition of power failure, so that the situation that the current-limiting configuration chip cannot be powered on and started again due to too low allowable current of the first power tube is avoided. Compared with the prior art, the allowable current of the first power tube of the current-limiting configuration chip has variability, the power-on process and the actual working load of the current-limiting configuration chip can be better compatible, the function of starting the larger current-limiting current during power-on can be realized, the function of protecting the smaller current-limiting current under the normal working state can also be realized, and the reliability and the practicability of the current-limiting configuration chip are improved.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation to the scope of the invention.

Fig. 1 is a longitudinal view of a schematic diagram of a switching power supply system according to an embodiment of the present invention.

FIG. 2 is a graph of supply voltage versus time for an embodiment of the present invention.

Fig. 3 is a longitudinal view of a schematic diagram of a current limiting configuration chip according to an embodiment of the invention.

FIG. 4 is a longitudinal view of a schematic diagram of a count compare module and an input compare module in accordance with an embodiment of the present invention.

Fig. 5-7 are timing diagrams of the reference voltage signal, the comparison signal, the trigger signal, the driving signal and the logic switch at different time periods according to an embodiment of the invention.

In the drawings:

100-current limiting configuration chip; 110-a logic control module; 120-input comparison module; 130-count comparison module; 140-a current limit configuration module; 150-an oscillator module; 160-soft start module; 170-output feedback module; 121-an amplifier; 122-a comparator; 131-a pulse counter; 132-a receive buffer; 133-a first register; 134-a second register; 135-a differential amplifier; 136-a threshold comparator; 200-an input power module; 300-a load module; k1-logic switch;

p1-power input pin; p2-clamp capacitor terminal pin; p3-power output pin; p4-feedback signal input terminal pin; P5-GND terminal pin; p6-second current limit configuration pin;

q1-first power tube; q2-second power tube; c1 — first capacitance; c2 — second capacitance; cx-clamp capacitance; an L-inductor; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; rx-adjustable resistance;

vin-supply voltage; VA-proportional voltage; VB-reference voltage; VC-a comparison signal; VD-trigger signal; VE-drive signal.

Detailed Description

To further clarify the objects, advantages and features of the present invention, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is to be noted that the drawings are in greatly simplified form and are not to scale, but are merely intended to facilitate and clarify the explanation of the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.

As used in this application, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally employed in a sense including "and/or," the terms "a" and "an" are generally employed in a sense including "at least one," the terms "at least two" are generally employed in a sense including "two or more," and the terms "first", "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "proximal end" and "distal end" generally refer to the corresponding two parts, which include not only the end points, but also the terms "mounted", "connected" and "connected" should be understood broadly, e.g., as a fixed connection, as a detachable connection, or as an integral part; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. Furthermore, as used in the present invention, the disposition of an element with another element generally only means that there is a connection, coupling, fit or driving relationship between the two elements, and the connection, coupling, fit or driving relationship between the two elements may be direct or indirect through intermediate elements, and cannot be understood as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation inside, outside, above, below or to one side of another element, unless the content clearly indicates otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

The following describes the current limiting configuration chip and the switching power supply system of the present embodiment with reference to the drawings.

As shown in fig. 1, fig. 1 is a longitudinal view of a schematic diagram of a switching power supply system according to an embodiment of the present invention, and the embodiment provides a switching power supply system, which includes a first capacitor circuit, a second capacitor circuit, an inductor L, a fifth resistor R5 (an upper voltage-dividing resistor), a sixth resistor R6 (a lower voltage-dividing resistor), and a current-limiting configuration chip 100; a first end of the first capacitor circuit is connected with an input end of the current-limiting configuration chip 100, and a second end of the first capacitor circuit is grounded; a first end of the inductor L is connected to an output end of the current limiting configuration chip 100, a second end of the inductor L is connected to a first end of the second capacitor circuit, and a second end of the second capacitor circuit is grounded; referring to fig. 3, fig. 3 is a longitudinal view of a schematic diagram of a current-limiting configuration chip according to an embodiment of the present invention, a first power transistor Q1 and a second power transistor Q2 are disposed in the current-limiting configuration chip 100, and an input terminal of the first power transistor Q1 is connected to an input terminal of the current-limiting configuration chip 100 to obtain a power voltage Vin input to the current-limiting configuration chip 100; the output end of the first power tube Q1 is connected with the output end of the second power tube Q2, and is commonly connected to the output end of the current-limiting configuration chip 100; the input end of the second power tube Q2 is grounded. When the first power transistor Q1 is turned on and the second power transistor Q2 is turned off, the first capacitor circuit, the first power transistor Q1, the inductor L and the second capacitor circuit form a first loop; when the first power transistor Q1 is turned off and the second power transistor Q2 is turned on, the second power transistor Q2, the inductor L and the second capacitor circuit form a second loop. Specifically, an input power module 200 may be adopted to provide the power voltage Vin to the switching power supply system, a first end of the input power module 200 is connected to a first end of the first capacitor circuit and an input end of the current limiting configuration chip 100, and a second end of the input power module 200 is connected to a second end of the first capacitor circuit; the load module 300 receives a load voltage output by the output terminal of the switching power supply system, a first terminal of the load module 300 is connected to a second terminal of the inductor L and a first terminal of the second capacitor circuit, and a second terminal of the load module 300 is connected to a second terminal of the second capacitor circuit. In addition, a first end of the fifth resistor R5 is connected to the second end of the inductor L and is configured to be connected to a first end of the load module 300; a second end of the fifth resistor R5 is connected to a first end of the sixth resistor R6, and is commonly connected to an output feedback module inside the current limiting configuration chip 100; the second end of the sixth resistor R6 is grounded and is used for being connected with the second end of the load module 300, and the fifth resistor R5 and the sixth resistor R6 are used for realizing real-time collection of load voltage. The first loop can realize normal input and output of the power voltage Vin, and the second loop can be understood as a freewheeling loop, so that the switching power supply system can continue to supply power to the load module 300 after the first power transistor Q1 is turned off. In the switching power supply system of this embodiment, the power voltage Vin provided by the input power module 200 is filtered by the first capacitor circuit, and then is input into the current-limiting configuration chip 100 from the input end of the current-limiting configuration chip 100, and after being processed by the current-limiting configuration chip 100, the controllable pulse-type power switching voltage is output from the output end of the current-limiting configuration chip 100, and after being stored in the inductor L and filtered by the second capacitor circuit, the constant load voltage (dc voltage) is output to the load module 300, so as to satisfy the load-carrying characteristic of the load module 300. In this embodiment, the first capacitor circuit is the first capacitor C1 shown in fig. 2, and the second capacitor C2 is the second capacitor C2 shown in fig. 2, but in this embodiment, the first capacitor circuit may also be a parallel structure of a plurality of capacitors, and the second capacitor circuit may also be a parallel structure of a plurality of capacitors.

Referring to fig. 2, fig. 2 is a graph of a power voltage variation with time according to an embodiment of the invention, in which a power voltage Vin is used as an input voltage of the current limiting configuration chip 100, a state variation of the power voltage Vin varies with time, specifically, within a time period of 0 to T1, the time period belongs to an initial power-on stage of the current limiting configuration chip 100, and a rising trend of the power voltage Vin is steeper, that is, a slope is larger; in the time period from T1 to T2, the power supply voltage Vin gradually tends to be gentle, namely the slope gradually decreases, and the current limiting configuration chip 100 starts to establish a normal output voltage logic relation; after time T2, the power voltage Vin is stable, the logic relationship of the output voltage of the current limiting configuration chip 100 is established, and the current limiting configuration chip 100 enters the normal operation mode. At the stage from the initial power-on stage of the current-limiting configuration chip 100 to the stage when the power supply voltage Vin is substantially unchanged, the current-limiting current of the current-limiting configuration chip 100 needs to be configured accordingly, so that the maximum current flowing through the first power tube Q1 does not exceed the current-limiting current, thereby ensuring the normal operation of the current-limiting configuration chip 100, whereas the current-limiting current configured by the conventional current-limiting configuration chip 100 is a fixed value, if the value of the current-limiting current is set to be small, the output voltage of the current-limiting configuration chip 100 may not be normally established, the power-on process may be restarted repeatedly, and further the switching power supply system designed based on the current-limiting configuration chip 100 may not normally operate. The purpose of this embodiment is to configure the current-limiting current of the current-limiting configuration chip 100 to be the first current-limiting current at the power-on stage, so as to better compatible with the power-on process of the current-limiting configuration chip 100 and the load of the actual operation, and to enable the larger current-limiting current to start during the power-on period, thereby ensuring that the output voltage logic can start to be established; when the logic relation of the output voltage is completely established, and the power supply voltage Vin is kept unchanged, the current-limiting current is configured to be the second current-limiting current, so that the smaller current-limiting current protection is realized under the normal working state.

It is understood that, as mentioned in the background, the current limiting current of the current limiting configuration chip 100 of the present embodiment is the maximum switching current flowing through the internal first power transistor Q1, i.e. the allowed current of the first power transistor Q1, and further can be understood as the maximum current allowed to flow through the first power transistor Q1.

In view of the above, the current limiting configuration chip 100 provided in this embodiment is applied to the above-mentioned switching power supply system, and the current limiting configuration chip 100 provided in this embodiment is preferably a synchronous rectification power switching power supply integrated circuit chip using advanced integrated circuit manufacturing processes. Further, the current limiting configuration chip 100 has six pins, which are a power input terminal pin P1, a clamp capacitor terminal pin P2, a power output terminal pin P3, a feedback signal input terminal pin P4, a GND terminal pin P5, and a second current limiting configuration pin P6. The functions of some pins will be explained below, and the functions of the pins that are not mentioned will be explained later in conjunction with an actual configuration scenario, where the power input terminal pin P1 is used to obtain the power voltage Vin provided by the input power module 200, the power output terminal pin P3 is used to output the controllable pulse-type power switch voltage (with the high level amplitude being the same as the amplitude of the power voltage Vin, which is the value of Vin) that is processed by the current limiting configuration chip 100, and the GND terminal pin P5 is connected to ground.

Referring to fig. 3, the current limiting configuration chip 100 of the present embodiment further includes an input comparing module 120, a count comparing module 130, a logic control module 110, and a current limiting configuration module 140 besides the first power transistor Q1 and the second power transistor Q2, and the respective modules will be separately described below.

The input comparing module 120 of this embodiment is configured to obtain the power voltage Vin input to the current limiting configuration chip 100 and the reference voltage VB with a sawtooth waveform provided from the outside in real time, and generate a comparison signal VC with a pulse width varying with the power voltage Vin according to the power voltage Vin and the reference voltage VB. Specifically, the input comparing module 120 samples the power supply voltage Vin in real time to obtain a proportional voltage VA, where the proportional voltage VA is in a proportional relationship with the power supply voltage Vin, and then compares the proportional voltage VA with a reference voltage to generate the comparison signal VC, and outputs the comparison signal VC from the output end of the input comparing module 120. Note that, in the initial power-on stage (low-frequency startup stage, stages 0 to T1 in fig. 2), the frequency of the reference voltage VB signal is maintained at the first stable value, the period of the reference voltage VB signal is maintained at the corresponding first stable period, and when the input/output of the current limiting configuration chip 100 is started (node T1 in fig. 2), the signal frequency of the reference voltage VB is raised to the second stable value, and the period of the reference voltage VB signal is maintained at the corresponding second stable period and thereafter remains unchanged.

In an embodiment, please refer to fig. 4, fig. 4 is a longitudinal diagram of a schematic diagram of the count comparison module 130 and the input comparison module 120 according to an embodiment of the present invention, the input comparison module 120 includes: the amplifier 121, the comparator 122, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4; a first end (connected to the input end of the current-limiting configuration chip 100) of the first resistor R1 is used to obtain the power voltage Vin; the second end of the first resistor R1 and the first end of the second resistor R2 are connected and are connected to the non-inverting input end of the amplifier 121 in common; a second end of the second resistor R2 is grounded; a first end of the third resistor R3 is connected to the inverting input terminal of the amplifier 121, and a second end of the third resistor R3 is connected to ground; a first end of the fourth resistor R4 is connected to the inverting input terminal of the amplifier 121, and a second end of the fourth resistor R4 is connected to the output terminal of the amplifier 121; the output terminal of the amplifier 121 is connected to the non-inverting input terminal of the comparator 122, the inverting input terminal of the comparator 122 is used for obtaining the reference voltage, and the output terminal of the comparator 122 is configured as the output terminal of the input comparison module 120. Specifically, the power supply voltage Vin is filtered and then connected to the input terminal of the current limiting configuration chip 100, the first resistor R1 and the second resistor R2 perform voltage division detection on the power supply voltage Vin, the amplifier 121 amplifies the voltage-divided power supply voltage Vin to obtain the proportional voltage VA, and the comparator 122 compares the proportional voltage VA with the reference voltage VB to output the comparison signal VC. It can be understood that the input voltage (power voltage Vin) is a dc signal, the proportional voltage VA is also a dc signal, the reference voltage VB is a sawtooth wave signal, and the waveform of the generated comparison signal VC is a square wave. It should be noted that the fourth resistor R4 is set to avoid the infinite amplification of the amplifier 121, and the circuit self-activates while the bandwidth is narrowed, and the fourth resistor R4 is set to reduce the amplification of the amplifier 121 to a value set in practical situations, and to widen the bandwidth, thereby improving the circuit integrity and making the proportional voltage VA a more preferable value.

The count comparison module 130 of the present embodiment is configured to fixedly output a driving signal VE and is internally provided with a detection period including a first detection time; the count comparison module 130 is configured to detect a pulse number of the comparison signal VC according to the first detection time (that is, detect the pulse number of the comparison signal VC within the first detection time, where the pulse number specifically refers to a high-level pulse number of the comparison signal VC), record pulse width data once when the pulse number is detected to be an expected value, further perform a difference amplification operation on the pulse width data corresponding to the detection period group to generate a difference amplification value, and turn over the drive signal VE when the difference amplification value is less than or equal to a threshold value; when the count comparison module 130 detects that the number of pulses is an expected value, the detection period further includes a second detection time after the first detection time, and the pulse width data represents a pulse width of the comparison signal VC within the second detection time; the count comparison module 130 is configured to start with a detection period in which the number of pulses detected for the first time is an expected value, and sequentially use two adjacent detection periods as the detection period groups, where the two adjacent detection period groups are not overlapped. Specifically, the counting and comparing module 130 detects the number of pulses of the comparison signal VC according to a first detection time of a detection period from an initial power-on stage of the current limiting configuration chip 100, the number of pulses detected by the counting and comparing module 130 in the early stage does not reach an expected value, after a plurality of detection periods with the first detection time (which may be regarded as segments 0 to T1 in fig. 1), the counting and comparing module 130 detects the number of pulses with the expected number for the first time (which may be regarded as a node T2 in the figure), and at this time, the detection period further includes a second detection time, and the counting and comparing module 130 records the pulse width (i.e., pulse width data) of the comparison signal VC for the second detection time, and thereafter, since the power supply voltage Vin is continuously established, the number of pulses with the expected number may be detected. Starting with a detection cycle in which the number of pulses detected for the first time is an expected value, sequentially setting two adjacent detection cycles as the detection cycle groups, and the two adjacent detection cycle groups are non-overlapping (no detection cycle is overlapped between the two adjacent detection cycles), it can be further understood that starting with a detection cycle in which the number of pulses detected for the first time is an expected value, sequentially designating a first valid detection cycle, a second valid detection cycle, a third valid detection cycle, … …, a J (J is a positive integer) valid detection cycle, setting the first valid detection cycle and the second valid detection cycle as the first detection cycle group, setting the third valid detection cycle and the fourth valid detection cycle as the second detection cycle group, … …, setting the (J-1) th valid detection cycle and the J (J-2) th valid detection cycle as the (J/2) th detection cycle group, then, starting from the first detection period group, difference amplification operation is sequentially performed on the pulse width data corresponding to the two detection periods in the detection period group (after the pulse width data corresponding to the next detection period is subtracted from the pulse width data corresponding to the previous detection period, amplification is performed again), a differential amplification value is generated, and comparison is performed with a threshold until the corresponding differential amplification value obtained in the (J/2) th detection period group does not exceed the threshold, so that the counting and comparing module 130 inverts the driving signal VE. It should be noted that the "pulse width" in the "pulse width data representing the pulse width of the comparison signal VC in the second detection time" refers to the pulse width of the comparison signal VC between a rising edge and a falling edge at the second detection time, that is, a complete pulse width (high-level pulse width) of the comparison signal VC. The specific size of the threshold value can be set by those skilled in the art according to actual situations, and will not be described herein.

In this embodiment, the count comparison module 130 may be configured to output the driving signal VE which is originally a high-level signal, and when the differential amplification value is smaller than or equal to the threshold, the driving signal VE is inverted to output a low-level signal.

In a specific embodiment, the count comparison module 130 includes that the count comparison module 130 includes a shift register unit including a receiving buffer 132, a first register 133 and a second register 134, a differential amplifier 135, a threshold comparator 136, a pulse counter 131 and a logic switch K1; the pulse counter 131 is configured to detect a pulse number of the comparison signal VC according to the first detection time, and output a one-time trigger signal VD when the pulse number is detected to be an expected value; the receiving buffer 132 is configured to receive the trigger signal VD, record the pulse width data, and register the pulse width data in the first register 133; the first register 133 is configured to shift the pulse width data corresponding to the detection period before the detection period group, which is originally registered, to the second register 134 when the pulse width data corresponding to the detection period after the detection period group is registered; the differential amplifier 135 is configured to perform a difference amplification operation on the pulse width data in the first register 133 and the pulse width data in the second register 134 to generate the differential amplification value, that is, it is understood that when neither the pulse width data in the first register 133 nor the pulse width data in the second register 134 is empty, the differential amplifier 135 will be triggered to perform the difference amplification operation on the pulse width data in the two registers, otherwise, the differential amplifier 135 will not be triggered; the threshold comparator 136 fixedly outputs the driving signal VE, is provided with the threshold therein, and inverts the driving signal VE when the obtained differential amplification value is smaller than or equal to the threshold; a first terminal of the logic switch K1 is used for obtaining the driving signal VE, and a second terminal of the logic switch K1 is used for connecting with the current limiting configuration module 140; after the pulse counter 131 outputs the trigger signal VD twice in the detection period group, the logic switch K1 is closed, that is, the number of pulses detected by the pulse counter 131 at the first detection time of the previous detection period in the detection period group reaches an expected value, and the number of pulses detected at the first detection time of the next detection period also reaches an expected value, at this time, the logic switch K1 is closed to output the inverted or non-inverted drive signal VE; the pulse counter 131 is used for resetting when detecting that the driving signal VE is not inverted after the detection of the number of pulses once is finished, so as to facilitate the detection of the number of pulses again next time; when the driving signal VE is inverted, the pulse counter 131 stops detecting the pulse number of the comparison signal VC, the first register 133 and the second register 134 respectively latch respective pulse width data, and the logic switch K1 remains closed to output the inverted driving signal VE; when the differential amplification value is greater than the threshold value, both the first register 133 and the second register 134 are reset (i.e., the pulse width data registered in each register is cleared), the logic switch K1 is turned off (specifically, turned off within the second detection time of the subsequent detection period corresponding to the detection period group), the threshold comparator 136 maintains the original output of the driving signal VE, and thereafter, the pulse width data corresponding to the next detection period group is re-detected and compared until it is detected that the two corresponding pulse width data in a certain detection period group are approximately equal, and the output differential amplification value is smaller than the threshold value.

In an exemplary embodiment, the expected value is set to 100, the count comparison module 130 starts to operate from the initial power-up stage of the current limiting configuration chip 100 (please refer to fig. 2 for the process of establishing the power voltage Vin), and the plurality of detection cycles detected by the count comparison module 130 are sequentially recorded as a first detection cycle, a second detection cycle, a third detection cycle, … …, an mth (M is a positive integer) detection cycle, … …, an (N-1) th detection cycle, and an nth (N is a positive integer) detection cycle. In the first detection period, the pulse counter 131 detects that the number of pulses of the comparison signal VC is less than 100 according to the first detection time, the pulse counter 131 will not send the trigger signal VD, the receiving buffer 132, the first register 133, the second register 134, and the differential amplifier 135 will not generate corresponding actions, and the threshold comparator 136 will maintain the originally fixed output driving signal VE. In the second detection period, the third detection period … …, and up to the (M-1) th detection period, as in the first detection period, after each reset and zero clearing, the number of pulses of the comparison signal VC detected in each detection period corresponding to the first detection time is detected and is not 100, and the threshold comparator 136 maintains the originally fixedly output drive signal VE. In the mth detection period, the pulse counter 131 obtains 100 pulse numbers according to the first detection time of the detection period (it can be considered that the mth detection period is a detection period in which the pulse counter 131 obtains 100 pulse numbers for the first time), at this time, the detection period further includes the second detection time when the detection period is located at the first detection time, the pulse counter 131 sends a trigger signal VD to the receiving buffer 132, and the receiving buffer 132 records the pulse width of the comparison signal VC at the second detection time of the detection period and shifts the comparison signal VC to the first register 133. In the mth to nth detection periods, the pulse counter 131 can detect 100 pulses, and from the mth detection period (for convenience of description, the "th detection period" in this paragraph will be indicated by the corresponding letter), M and (M + 1) are sequentially set as the first detection period group, and (M + 2) and (M + 3) are set as the second detection period group, … …, (N-1) and N are set as the ith (i is a positive integer) detection period group. Taking the first detection period group as an example, the first register 133 registers the pulse width data corresponding to M first, and when the pulse width data corresponding to (M + 1) is registered, the pulse width data corresponding to M is synchronously shifted to the second register 134, and at this time, the pulse width data of both registers are not empty, the differential amplifier 135 is triggered to output a differential amplification value, and then the differential amplification value is compared with a threshold value to determine whether to invert the driving signal VE. It can be further understood that, in the first detection period group until the (i-1) th detection period group (i.e., M to (N-2)), the pulse width data in the second register 134 is greater than the pulse width data in the first register 133, the differential amplification value is greater than the threshold, the drive signal VE will not be inverted, the input power supply voltage Vin is still continuously established, the input and output logic relationship of the current limiting configuration chip 100 is not completely established, the logic switch K1 is turned off in the internal count comparison module 130, and the first register 133 and the second register 134 are reset and cleared after the differential amplification value and the threshold are compared; in the ith detection period group ((N-1) — N), the pulse width data in the second register 134 is approximately equal to the pulse width data in the first register 133, the differential amplification value is smaller than or equal to the threshold value, the driving signal VE is inverted, the input power voltage Vin is already stable, the input-output logic relationship of the current limiting configuration chip 100 is completely established, in the internal count comparison module 130, the first register 133 and the second register 134 respectively latch the respective pulse width data, the logic switch K1 keeps a closed state to output the inverted driving signal VE, and the inverted driving signal VE is fed back to the pulse counter 131, so that the pulse counter 131 stops working.

Further, two of the sub-detection periods of the detection period are continuous; the first detection time and the second detection time of the sub-detection period are continuous, and the sub-detection period is equal to the sum of the first detection time and the second detection time, so that the first detection time and the second detection time are considered to be continuous; the first detection time and the second detection time are both integer multiples of the signal period of the reference voltage (here, refer to second stable periods which are both integer multiples), and the multiple of the first detection time and the signal period of the reference voltage is equal to the expected value (i.e., the second stable period which is the multiple of the expected value), and the pulse width data represents the pulse width of the signal period of the second reference voltage corresponding to the comparison signal VC in the second detection time. Specifically, two adjacent detection periods are consecutive (without time interval), so that two adjacent detection period groups are also consecutive. The detection period may be considered to be equal to the first detection time when the count comparison module 130 does not detect the number of pulses of the expected number, and may be considered to further include the second detection time and be equal to the sum of the first detection time and the second detection time when the count comparison module 130 detects the number of pulses of the expected number. Meanwhile, in consideration of the delay problem of signal transmission, the pulse width data in this embodiment specifically refers to the pulse width of the signal period of the second reference voltage corresponding to the comparison signal VC within the second detection time, so as to ensure the integrity of the acquired pulse width. Specifically, referring to fig. 5 to 7, fig. 5 to 7 are timing diagrams of signals of a reference voltage, a comparison signal, a trigger signal, a driving signal, and a logic switch at different time periods according to an embodiment of the present invention, where T1> T2> T3> T4= T5= T6= T7= T8= T9= T10, Tx is a first detection time, Ty is a second detection time, and Tz is a period of the second reference voltage in the second detection time.

Referring to fig. 5, T1 is an initial start-up phase of the power-up of the current limiting configuration chip 100, it can be considered that a plurality of detection periods with a first detection time Tx (it can be understood that T1 is equal to even times or odd times of Tx), the pulse counter 131 cannot detect the number of pulses of the 100 comparison signals VC at the first detection time of each detection period, and the threshold comparator 136 maintains the original output of the driving signal VE, which is a high-level output.

Referring to fig. 6, T2 is a sum of a detection period in which the pulse counter 131 detects the number of pulses with the expected number for the first time and a detection period in which the number of pulses with the expected number for the second time in the current limiting configuration chip 100 (which is equivalent to a first detection period group), the pulse counter 131 sends out the trigger signal VD (the trigger signal VD is active at a high level) twice in sequence, the logic switch K1 is closed in a T10 segment, the first register 133 registers a pulse width corresponding to the comparison signal VC in a previous Tz first, then registers a pulse width corresponding to the comparison signal VC in the next Tz, finally the first register 133 registers a pulse width corresponding to the comparison signal VC in the previous Tz, the second register 133 registers a pulse width corresponding to the comparison signal VC in the previous Tz, at this time, the pulse widths of the first register 133 and the second register 134 are not equal, the threshold comparator 136 continuously outputs at a high level, and the logic switch K1 is open at a next period of the reference voltage VB after T10.

Referring to fig. 7, T3 is the sum of two detection periods (corresponding to the last detection period group, which can also be understood as passing through T2 similar to the even or odd multiple) when the pulse counter 131 detects the number of pulses of the expected number twice in the current limiting configuration chip 100, the pulse counter 131 sends the trigger signal VD twice in sequence, and the logic switch K1 is closed in the T9 segment. When the trigger signal VD is sent for the first time in T3, due to the delay, the trigger signal VD is sent to the receiving buffer 132 at 0.5 times T4, at this time, the pulse width of the comparison signal VC starts to be recorded from 0.5 times T4, and because the pulse width at this time is incomplete, the pulse width of the T5 segment is recorded as pulse width data, the pulse counter 131 detects that the drive signal VE is still high-level output at the T6 segment, and resets and clears to restart to detect the number of counting pulses; in the section 0.5 times T7, the pulse counter 131 sends out the trigger signal VD for the second time, and records the pulse width of the comparison signal VC from 0.5 times T7, because the pulse width is incomplete at this time, the receiving buffer 132 will record the pulse width corresponding to the comparison signal VC in the section T8 again, finally the first register 133 registers the pulse width corresponding to the comparison signal VC in the section T8, and the second register 134 registers the pulse width corresponding to the section T5, at this time, because the input and output voltages are completely established, the pulse widths in the two registers are approximately equal and do not exceed the threshold, the drive signal VE of the threshold comparator 136 is inverted from high level to low level for output, the two registers latch the pulse width data corresponding to each other, and the logic switch K1 will remain closed thereafter. It should be noted that the difference amplification operation of the pulse width data in the two registers, the comparison operation of the threshold comparator 136, and the closing operation of the logic switch K1 are performed with a small delay, and the response speed of each device is extremely fast, and all the operations are completed within the time period T9.

It can be appreciated that, in the period T1, the frequency of the reference voltage VB signal is maintained at the first stable value, and the period of the reference voltage VB signal is maintained at the corresponding first stable period; in the segments T2 and T3, the frequency of the reference voltage VB signal is maintained at the second stable value (the first stable value is smaller than the second stable value) and the period of the reference voltage VB signal is maintained at the corresponding second stable period. The first sensing time Tx may be set equal to a desired multiple (set to 100 times) of the second settling period, and the second sensing time Ty may be set equal to 3 times the second settling period, so Tz is the second settling period within the second sensing time Ty.

Of course, in other embodiments, the delay-reducing full adder circuit may be configured to reduce the delay of the trigger signal VD, so that the collected pulse width is the pulse width of the period of the first reference voltage VB corresponding to the comparison signal VC in the second detection time (corresponding to the pulse widths of the segments T4 and T7). The embodiment of the present invention will not be described in detail with respect to the above-mentioned delay-reducing full adder circuit, and those skilled in the art can adapt the delay-reducing full adder circuit according to the prior art.

The logic control module 110 of this embodiment is connected to the control terminal of the first power transistor Q1 and the control terminal of the second power transistor Q2, and is configured to control the first power transistor Q1 and the second power transistor Q2 to be alternately turned on and off.

In an exemplary embodiment, the first power transistor Q1 is a PMOS transistor, the input terminal of the first power transistor Q1 is a source terminal of the PMOS transistor, the output terminal of the first power transistor Q1 is a drain terminal of the PMOS transistor, and the control terminal of the first power transistor Q1 is a gate terminal of the PMOS transistor; the second power tube Q2 is an NMOS tube, the output end of the second power tube Q2 is the drain of the NMOS tube, the input end of the second power tube Q2 is the source of the NMOS tube, and the control end of the second power tube Q2 is the gate of the NMOS tube. Further, the logic control module 160 sends the control signal to the first power transistor Q1 as a first control signal, and sends the control signal to the second power transistor Q2 as a second control signal, so that the first control signal and the second control signal are non-overlapping in order to avoid the simultaneous turn-on of the first power transistor Q1 and the second power transistor Q2. When the first control signal is at a low level, the voltage of the first control signal is lower than the source voltage of the first power tube Q1, the absolute value of the voltage difference between the grid source and the grid source is greater than the minimum starting voltage of the first power tube Q1, the second control signal is at a low level, and the voltage difference between the grid source and the grid source is less than the minimum starting voltage of the second power tube Q2, so that the first power tube Q1 is started, and the second power tube Q2 is cut off; the first control signal is at high level, the absolute value of the difference between the first control signal and the source voltage of the first power tube Q1 is smaller than the minimum turn-on voltage of the first power tube Q1, the second control signal is at high level, the voltage of the second control signal is higher than the source voltage of the second power tube Q2, and the voltage difference between the gate and the source is larger than the minimum turn-on voltage of the second power tube Q2, so that the first power tube Q1 is turned off, and the second power tube Q2 is turned on.

The current limiting configuration module 140 of this embodiment is connected to the logic control module 110, and is configured to obtain the driving signal VE in real time; when the driving signal VE is not inverted (the original state output is maintained), the current limiting configuration module 140 controls the logic control module 110 to maintain the allowed current of the first power transistor Q1 as a first current limiting current; when the driving signal VE is inverted, the current limiting configuration module 140 drives the logic control module 110 to adjust the allowed current of the first power transistor Q1 to be a second current limiting current; the second current-limiting current is less than the first current-limiting current. It should be noted that the first current-limiting current is usually a default current-limiting current initially set by the current-limiting configuration chip 100, and is not required to be set by the current-limiting configuration module 140, although corresponding software or hardware may be configured on the current-limiting configuration module 140 to enable the current-limiting configuration module 140 to have a function of setting the first current-limiting current, the current-limiting configuration module 140 maintains the allowable current of the first power transistor Q1 at the first current-limiting value, that is, the allowable current of the first power transistor Q1 is not changed, and the allowable current of the first power transistor Q1 is to be maintained at the default first current-limiting current of the current-limiting configuration chip 100; the allowed current of the first power tube Q1 is adjusted to be a second current-limiting current, and the current-limiting configuration module 140 changes the allowed current of the first power tube Q1 from the first current-limiting current to the second current-limiting current by the control module acting on the allowed current of the first power tube Q1 accordingly. With the arrangement, the first current-limiting current can be better compatible with the power-on process and the actual working load of the current-limiting configuration chip 100, so that the purpose of starting the larger current-limiting current during power-on can be realized, and the output voltage logic can be normally established; after the output voltage logic is completely established, that is, the input voltage is stable (in fig. 2, the second half of the time T2, the power supply voltage Vin is stable), the allowed current of the first power tube Q1 is configured as the second current-limiting current, so that the purpose of realizing the small current-limiting protection of the current-limiting configuration chip 100 in the normal working state can be ensured. In addition, the first current-limiting current and the second current-limiting current represent that the allowable current of the first power tube Q1 of the current-limiting configuration chip 100 of the present embodiment has variability, which solves the problem that the allowable current of the first power tube Q1 of the conventional current-limiting configuration chip 100 is set to be smaller or set to be a fixed value (it can be understood that there is no variability in the allowable current of the first power tube Q1 of the conventional current-limiting configuration chip 100), improves the reliability and practicability of the current-limiting configuration chip 100, does not need to increase the packaging and use cost, and facilitates the fast updating and iteration of the chip.

Optionally, the current-limiting configuration module 140 is configured to implement configuration of a second current-limiting current according to a resistance of an adjustable resistor, where one end of the adjustable resistor Rx is connected to the current-limiting configuration module 140, and the other end is grounded; the second current-limiting current is equal to the product of the resistance value of the adjustable resistor Rx and a preset coefficient. Specifically, referring to fig. 1, in the present embodiment, one end of the adjustable resistor Rx and the second current-limiting configuration pin P6And the other end of the resistor is grounded, the adjustable resistor Rx is externally arranged on the current-limiting configuration chip 100, so that a technician can conveniently adjust the resistance value, and in other embodiments, the adjustable resistor Rx can also be internally arranged on the current-limiting configuration chip 100. Second current limiting current

In an exemplary embodiment, the predetermined coefficient D =0.0002A/Ω, and the second current limiting current is configured to be 2A, so that the resistance of the adjustable resistor Rx is 10k Ω.

Optionally, the current limiting configuration chip 100 of this embodiment further includes an oscillator module 150, two ends of the oscillator module 150 are respectively connected to the input comparing module 120 and the logic control module 110, and are respectively configured to provide the required reference voltage VB to the input comparing module 120 and the logic control module 110, where a signal waveform of the reference voltage VB is a sawtooth wave. In this embodiment, the oscillator module 150 may be an oscillator or an oscillating circuit, which is not limited in the present invention.

Preferably, the current-limiting configuration chip 100 further includes a soft-start module 160, an input end of the soft-start module 160 is connected to an input end (a power input end pin P1) of the current-limiting configuration chip 100, an output end of the soft-start module 160 is connected to the logic control module 110, and the soft-start module 160 is configured to send a start signal to the logic control module 110 according to a real-time magnitude of the power voltage Vin, so as to drive the logic control module 110 to adjust a switching frequency of the first power transistor Q1 and the second power transistor Q2, which are alternately turned on and off; the frequency of the reference voltage VB of the oscillator module 150 is equal to the frequency of the start signal. The soft start module 160 may also be called a self-start module, and is configured to control the logic control module 110 in the current-limiting configuration chip 100 to sequentially enter a working state after the chip pins are powered on. Since the analog circuit and the digital circuit need to enter a predetermined state, in order to avoid the impact of the surge current at the power-on moment on the corresponding digital circuit or analog circuit after the power input pin P1 of the chip is powered on, the soft start module 160 sets the start bias, and adds a processing procedure to protect the logic control module 110 from the damage of the pulse during power-on. In this embodiment, the soft start module 160 provides a proper start bias voltage for the logic control module 110, so that the logic control module 110 operates at a stable voltage, and the logic control module 110 implements soft start. The soft start module 160 in this example may be a soft start or a soft start circuit, which is not limited by the invention. While the power voltage Vin is gradually increased, the frequency of the start signal is gradually increased, the oscillator module 150 is configured to adaptively adjust the signal frequency of the reference voltage VB according to the frequency of the start signal, that is, the oscillator module 150 and the soft start module 160 are linked, and in the low-frequency start phase, the signal frequency of the reference voltage VB and the frequency of the start signal of the soft start module 160 are adjusted to be equal. In addition, the start signal of the soft start module 160 drives the logic control module 110 to adjust the switching frequency of the first power transistor Q1 and the second power transistor Q2 for alternately turning on and off, specifically, referring to fig. 1, in the power-up stage (0 to T1 stage in fig. 1), the logic control module 110 controls the switching frequency of the first power transistor Q1 and the second power transistor Q2 for alternately turning on and off to gradually increase from the first switching frequency (e.g., 30 KHz); at node T1, the logic relationship of the output voltage of the switching current system is gradually and normally established, and the switching frequency is gradually increased from the first switching frequency to the second switching frequency (e.g. 150 KHz) and maintained at the second switching frequency after node T1.

Preferably, the current limiting configuration chip 100 includes an output feedback module 170, the switching power supply system is configured to provide a load voltage to the load module 300, and the output feedback module 170 is configured to detect and collect the load voltage in real time and form a feedback signal to the logic control module 110 according to the load voltage, so as to drive the logic control module 110 to adjust duty ratios of the first power transistor Q1 and the second power transistor Q2, thereby stabilizing magnitudes of the output voltage and the output current. Specifically, referring to fig. 2, the load voltage is detected by dividing the voltage through the fifth resistor R5 and the sixth resistor R6, the load voltage is collected in real time through the sixth resistor R6, and the common terminal of the fifth resistor R5 and the sixth resistor R6 is connected to the output feedback module 170 through the feedback signal input terminal pin P4. In addition, when the feedback signal sent by the output feedback module 170 to the logic control module 110 reflects that the collected voltage is greater than a preset value (for example, the preset value is set to be 60% of the load voltage in normal operation), the switching frequency of the first power transistor Q1 and the switching frequency of the second power transistor Q2, which are alternately turned on and off, start to be gradually increased from the first switching frequency to the second switching frequency (corresponding to sections T1 to T2 in fig. 1).

Preferably, the switching power supply system includes a clamping capacitor Cx, and the current limiting configuration chip 100 includes a clamping capacitor terminal connected to the logic control module 110, and the clamping capacitor Cx is coupled between the input terminal (power input pin P1) of the current limiting configuration chip 100 and the clamping capacitor terminal (clamping capacitor terminal pin P2). One end of the clamping capacitor Cx is connected to the power input pin P1, and the other end thereof is connected to the logic control module 110 through the clamping capacitor pin P2, which provides a gate-to-source driving Voltage (VGS) for an internal power transistor (e.g., a P-type metal-oxide-semiconductor transistor (PMOS transistor)). Referring to fig. 1, a clamp capacitor Cx is disposed outside the current limiting configuration chip 100, the first power transistor Q1 is a PMOS transistor, and the clamp capacitor provides a stable voltage for turning on the first power transistor Q1 through a clamp capacitor terminal pin P2.

Based on the above current limiting configuration chip 100, the present embodiment correspondingly provides a control method of a current limiting configuration chip, which is applied to the above current limiting configuration chip 100, and the control method of the current limiting configuration chip will be described with reference to the specific devices listed above. The control method of the current limiting configuration chip comprises the following steps:

the method comprises the following steps: the input comparison module 120 obtains a proportional voltage related to the power voltage Vin, and generates a comparison signal VC after comparing with a reference voltage VB provided by the oscillator. Specifically, the amplifier 121 in the input comparing module 120 detects and obtains a proportional voltage proportional to the power voltage Vin, and then compares the proportional voltage with the reference voltage VB by the comparator 122 to generate a comparison signal VC, wherein the waveform of the comparison signal VC is a square wave and the pulse width of the comparison signal VC varies with the power voltage Vin.

Step two: the pulse width of the comparison signal VC at the first detection time of the detection period is obtained by the pulse counter 131. When the current limiting configuration chip 100 is in a low-frequency startup stage (corresponding to stages 0 to T1 in fig. 1, and stage T1 in fig. 5, at this time, the switching frequencies of two power transistors of the chip belong to the low-frequency stage and gradually rise, for example, from 30KHz, the logic switch K1 is in an off state, the pulse counter 131 does not detect the number of pulses with the expected number, the current limiting configuration module 140 defaults to receive the driving signal output by the count comparison module 130 without turning over, and at this time, the current limiting configuration module 140 is used to maintain the current limiting current (specifically, the allowed current of the first power transistor Q1) of the current limiting configuration chip 100 as the first current limiting current with default setting, so as to ensure that the output voltage can be normally established, and the load startup cannot be caused by the current limiting current setting being smaller. In the low-frequency starting stage of power-on, the number of the pulse counters 131 cannot be counted to 100, at this time, the receiving buffer 132 and the two registers have no action, the pulse counters 131 are reset and cleared, and the pulse number of the comparison signal VC in the first detection time of the next detection period starts to be detected.

Step three: when the output voltage logic is normally established, the signal frequency of the reference voltage VB provided by the oscillator module 150 rises to enter a stable state, the number of pulses of the comparison signal VC output by the comparator 122 starts to increase, the pulse counter 131 detects that the number of pulses of the comparison signal VC reaches an expected value at the first detection time of the previous detection period, the pulse counter 131 sends a trigger signal VD to the receiving buffer 132 once, so that the receiving buffer 132 receives the pulse width between the rising edge and the falling edge of the comparison signal once within the second detection time of the detection period, and shifts and registers the pulse width in the first register 133, and the pulse counter 131 resets, clears and starts to count again.

Step four: the power voltage Vin continuously rises, the pulse counter 131 detects that the number of pulses of the comparison signal VC reaches 100 at the first detection time of the next detection period, the pulse counter 131 sends a trigger signal VD to the receiving buffer 132, so that the receiving buffer 132 receives the pulse width of the comparison signal VC from a rising edge to a falling edge within the second detection time of the detection period, and shifts and registers the pulse width into the first register 133, and the pulse width originally registered by the first register 133 is synchronously shifted into the second register 134. At this time, the pulse counter counts twice and sends two trigger signals to the shift register unit successively (the two trigger signals can be considered to be valid), and at this time, the logic switch K1 is closed.

Step five: when the pulse widths in the first register 133 and the second register 134 are not empty, the primary differential amplifier 135 is triggered, the pulse width data in the two registers are subjected to difference amplification operation to generate a differential amplification value, then the threshold comparator 136 is triggered, the differential amplification value is compared with a preset threshold, if the differential amplification value is greater than the threshold, the threshold comparator 136 maintains the original driving signal output, and if the differential amplification value is less than or equal to the threshold, the threshold comparator 136 outputs the inverted driving signal. In the low-frequency starting stage of power-on, the pulse width in the first register 133 is greater than that in the second register 134, the driving signal output by the threshold comparator 136 is unchanged, the pulse counter 131 is reset and cleared to start counting again, the pulse widths in the two registers are reset and cleared, and the logic switch K1 is turned off.

Step six: and repeating the fourth step to the sixth step until the pulse width in the first register 133 is approximately equal to the pulse width in the second register 134, and outputting the inverted driving signal by the threshold comparator 136. After the threshold comparator 136 outputs the inverted driving signal, the pulse widths of the two registers are latched, and the pulse counter 131 stops operating.

Step seven: when the threshold comparator 136 outputs the inverted driving signal, the logic switch K1 remains in a closed state, and the inverted driving signal is output to the current limiting configuration module 140, so that the current limiting configuration module 140 is driven to configure the allowable current of the first power transistor of the current limiting configuration chip to be the second current limiting current.

Step eight: and if the current-limiting configuration chip 100 is powered off, repeating the first step, the second step and the third step, and then realizing power-on reset.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.

Claims

1. A current limiting configuration chip is applied to a switching power supply system and is characterized by comprising:

the counting comparison module is used for fixedly outputting a driving signal and internally setting a detection period comprising first detection time; the counting comparison module is used for detecting the pulse number of the comparison signal according to the first detection time, recording once pulse width data when the pulse number is detected to be an expected value, further carrying out difference amplification operation on the pulse width data corresponding to the detection period group to generate a difference amplification value, and turning over the driving signal when the difference amplification value is smaller than or equal to a threshold value; when the counting comparison module detects that the number of pulses is an expected value, the detection period further includes a second detection time after the first detection time, and the pulse width data represents a pulse width of the comparison signal in the second detection time; the counting comparison module is used for starting a detection period with the number of pulses detected for the first time as an expected value, and sequentially taking two adjacent detection periods as the detection period groups, wherein the two adjacent detection period groups are not overlapped;

2. The current-limiting configuration chip of claim 1, wherein the first power transistor is a PMOS transistor, the input terminal of the first power transistor is a source of the PMOS transistor, the output terminal of the first power transistor is a drain of the PMOS transistor, and the control terminal of the first power transistor is a gate of the PMOS transistor; the second power tube is an NMOS tube, the output end of the second power tube is the drain electrode of the NMOS tube, the input end of the second power tube is the source electrode of the NMOS tube, and the control end of the second power tube is the grid electrode of the NMOS tube.

3. The current-limiting configuration chip of claim 1, wherein the current-limiting configuration module is configured to configure the second current-limiting current according to a resistance of an adjustable resistor; one end of the adjustable resistor is connected with the current limiting configuration module, and the other end of the adjustable resistor is grounded; the second current-limiting current is equal to the product of the resistance value of the adjustable resistor and a preset coefficient.

4. The current-limiting configuration chip according to claim 1, wherein the current-limiting configuration chip includes a soft start module, an input end of the soft start module is configured to obtain the power voltage, an output end of the soft start module is connected to the logic control module, and the soft start module is configured to send a start signal to the logic control module according to a real-time magnitude of the power voltage, so as to drive the logic control module to adjust a switching frequency at which the first power transistor and the second power transistor are alternately turned on and off; the frequency of the start signal is used to be equal to the signal frequency of the reference voltage.

5. The current limiting configuration chip of claim 1, wherein the input comparison module comprises: the circuit comprises an amplifier, a comparator, a first resistor, a second resistor, a third resistor and a fourth resistor; the first end of the first resistor is used for acquiring the power supply voltage; the second end of the first resistor is connected with the first end of the second resistor, and the second end of the first resistor and the first end of the second resistor are connected to the non-inverting input end of the amplifier together; the second end of the second resistor is grounded; the first end of the third resistor is connected to the inverting input end of the amplifier, and the second end of the third resistor is grounded; a first end of the fourth resistor is connected to an inverting input end of the amplifier, and a second end of the fourth resistor is connected to an output end of the amplifier; the output end of the amplifier is connected with the non-inverting input end of the comparator, the inverting input end of the comparator is used for obtaining the reference voltage, and the output end of the comparator is configured as the output end of the input comparison module.

6. The current-limiting configuration chip of claim 1, wherein the count comparison module comprises a shift register unit, a differential amplifier, a threshold comparator, a pulse counter, and a logic switch, the shift register unit comprising a receiving buffer, a first register, and a second register;

7. The current limiting configuration chip of claim 1 or 6, wherein a plurality of the sensing periods are consecutive; when the counting and comparing module detects that the pulse number is an expected value, the detection period is the sum of the corresponding first detection time and the corresponding second detection time; the first detection time and the second detection time are both integral multiples of the period of the reference voltage, the integral multiples of the first detection time and the period of the reference voltage are equal to the expected value, and the pulse width data represent the pulse width of the period of a second reference voltage corresponding to the comparison signal in the second detection time.

8. A switching power supply system, comprising: a first capacitive circuit, a second capacitive circuit, an inductor and a current limiting configuration chip according to any one of claims 1 to 6; the first end of the first capacitor circuit is connected with the input end of the current-limiting configuration chip, and the second end of the first capacitor circuit is grounded; the first end of the inductor is connected with the output end of the current-limiting configuration chip, the second end of the inductor is connected with the first end of the second capacitor circuit, and the second end of the second capacitor circuit is grounded; when the first power tube is started and the second power tube is stopped, the first capacitor circuit, the first power tube, the inductor and the second capacitor circuit form a first loop; when the first power tube is turned off and the second power tube is turned on, the second power tube, the inductor and the second capacitor circuit form a second loop.

9. The switching power supply system according to claim 8, wherein the current limiting configuration chip comprises an output feedback module, a fifth resistor and a sixth resistor; the fifth resistor and the sixth resistor are connected in series and then connected in parallel with the second capacitor circuit, and the output feedback module is connected to a common line of the fifth resistor and the sixth resistor; the output feedback module is used for detecting and collecting the load voltage output by the switching power supply system in real time according to the sixth resistor, and forming a feedback signal to the logic control module according to the load voltage so as to drive the logic control module to adjust the duty ratio of the first power tube and the second power tube.

10. The switching power supply system according to claim 8, wherein the switching power supply system comprises a clamp capacitor, the current limiting configuration chip is provided with a clamp capacitor terminal connected to the logic control module, and the clamp capacitor is coupled between the input terminal of the current limiting configuration chip and the clamp capacitor terminal.