CN113270393A - Test key structure and wafer stacking structure - Google Patents
Test key structure and wafer stacking structure Download PDFInfo
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- CN113270393A CN113270393A CN202110518956.0A CN202110518956A CN113270393A CN 113270393 A CN113270393 A CN 113270393A CN 202110518956 A CN202110518956 A CN 202110518956A CN 113270393 A CN113270393 A CN 113270393A
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Abstract
The invention provides a test key structure and a wafer stacking structure, comprising: the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit. The distances between adjacent test pads on the test key unit are not completely the same, i.e., a test pad design with a non-uniform distance and an asymmetric structure is adopted, so that the test pad sequence on the test key unit is easily distinguished. The test key structure can be used for judging the sequence of the test pads by eyes, reduces the risk of errors when a test program is established, and can obviously reduce the time for eliminating faults. The risk of human misoperation when the position of the lower needle is confirmed is avoided. The wafer stacking structure combines the test program of the single wafer, so that the test time is saved, and the manpower for rewriting the test program and the risk of errors are reduced.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a test key structure and a wafer stacking structure.
Background
In semiconductor processing, in order to maintain stable product quality, the semiconductor devices produced are constantly tested. Generally speaking, various semiconductor processes can be used to fabricate devices on a die, and simultaneously, the same steps are used to fabricate devices to be tested and test pads on the scribe lines of the wafer to simulate the same processes on the die. The test key structure comprises a plurality of test pads which are distributed at intervals in the test key unit. The testing device such as probe is used to contact the testing pad and measure various parameters of the testing element to inspect whether the process is normal, so as to effectively control the product quality.
For WAT (Wafer Acceptance Test), a probe card is required to be aligned with a Test pad and then simultaneously probe down for the requirement of automatic testing. For the design of the test pads with uniform spacing, the positions and the sequence of the wafers after mirror image turning cannot be distinguished.
As the scale of integrated circuits increases, the demand for dicing street space also increases. When the distance between adjacent test key units is close, and the distance between adjacent test key units is just equal to the distance between adjacent test pads in one of the test key units, and the distances between the test pads in the test key units are equal (uniform), there is a risk of setting an error in the position of the lower pin. When the alignment fails and the position of the lower needle needs to be confirmed manually, the risk of artificial misjudgment exists.
Particularly, when a product after wafers are stacked is tested, after an upper wafer is subjected to a stacking process, a device of the upper wafer is turned over in a mirror image mode, and a silicon substrate on the back of the wafer is placed on the surface of the upper wafer. Under a microscope, relevant marks on the front surface are blurred, and the design of uniform spacing of the test pads cannot distinguish the sequence of the test pads. And the respective test pads of the upper and lower sheets are in completely opposite order, and the test of the two sheets must be separately performed without rewriting the test program.
Disclosure of Invention
The invention aims to provide a test key structure, which can easily distinguish the sequence of test pads on a test key unit, reduce the risk of errors in establishing a test program and avoid manual misoperation.
Another objective of the present invention is to provide a wafer stacking structure, which combines the testing procedures of the single wafers, thereby saving the testing time and reducing the labor required for rewriting the testing procedures and the risk of errors.
The present invention provides a test key structure comprising:
the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit.
Further, the minimum spacing between adjacent test pads is a design rule minimum spacing.
Furthermore, the test key units are distributed in the cutting channels of the wafer, and the plurality of to-be-tested elements and the plurality of test pads in the test key units are arranged in a single row.
Further, the element to be tested is not arranged in the minimum spacing between the adjacent test pads.
Further, the distance between adjacent test key units is greater than the minimum spacing between adjacent test pads.
Furthermore, the test key structure comprises a first common pad, and a test end of each of the plurality of devices to be tested is electrically connected with the first common pad.
Further, each of the devices under test is electrically connected to at least one of the test pads adjacent to the device under test.
Furthermore, the plurality of test pads comprise a second common pad, and a test end of each of the plurality of devices to be tested is electrically connected with the second common pad.
Further, the test pad on the side of the minimum pitch is defined as the first common pad.
The invention also provides a wafer stacking structure, comprising:
a bottom wafer and an upper wafer; the first surface of the bottom wafer is bonded to the first surface of the upper wafer;
the first surface of the bottom wafer and the first surface of the upper wafer are distributed with the test key structures, and the test key structures on the first surface of the bottom wafer are in mirror symmetry with the test key structures on the first surface of the upper wafer.
Further, the test key structure on the first surface of the bottom wafer comprises at least one first test key unit,
the test key structure on the first surface of the upper wafer comprises at least one second test key unit, and the second test key unit is in mirror symmetry with the first test key unit.
Furthermore, a bottom bonding metal layer is further arranged on the first surface of the bottom wafer, an upper bonding metal layer is further arranged on the first surface of the upper wafer, the first test key unit is bonded facing the upper bonding metal layer, and the second test key unit is bonded facing the bottom bonding metal layer.
Further, the wafer stack structure further includes:
the groove penetrates through one side of the upper layer wafer, which is far away from the bonding surface, to respectively expose the upper layer bonding metal layer and the second test key unit;
the plug is filled in the groove and is electrically connected with the upper bonding metal layer and the test pad of the second test key unit respectively;
the lead-out bonding pad is positioned on the surface of one side, far away from the bonding surface, of the upper wafer; the leading-out bonding pad comprises a first leading-out bonding pad and a second leading-out bonding pad, and the first leading-out bonding pad, the plug, the upper bonding metal layer and the test pad in the first test key unit are electrically connected in sequence; the second lead-out pad, the plug and the test pad in the second test key unit are electrically connected in sequence.
Compared with the prior art, the invention has the following beneficial effects:
the present invention provides a test key structure, comprising: the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit. The distances between the adjacent test pads on the test key unit are not completely the same, that is, the test pads with non-uniform distances and the test pad design with an asymmetric structure are adopted, so that the test pad sequence on the test key unit is easily distinguished. The test key structure can be used for judging the sequence of the test pads by eyes, reduces the risk of errors when a test program is established, and can obviously reduce the time for eliminating faults. The risk of human misoperation when the position of the lower needle is confirmed is avoided. The wafer stacking structure combines the test program of the single wafer, so that the test time is saved, and the manpower for rewriting the test program and the risk of errors are reduced.
Drawings
Fig. 1 is a schematic structural diagram of a first test key according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a second test key according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a third exemplary test key structure according to the present invention.
FIG. 4 is a diagram illustrating a test key structure of an upper wafer in a wafer stack structure according to an embodiment of the invention.
Fig. 5 is a schematic diagram of a wafer stack structure according to an embodiment of the invention.
FIG. 6a is a diagram of a test key unit on a bottom wafer according to an embodiment of the invention.
FIG. 6b is a diagram of a test key unit on an upper wafer according to an embodiment of the present invention.
FIG. 7 is a schematic diagram illustrating a position of a tip of a probe card according to an embodiment of the invention.
FIG. 8 is a schematic diagram of a probe card tip image to needle according to an embodiment of the invention.
Wherein the reference numbers are as follows:
a T-test key unit; 1. 2, y, z-to-be-tested element; 12. 13, 22, 23, y2, y3, z2, z 3-test pad; c1 — first common pad; c2 — second common pad; 10-a bottom wafer; 20-upper wafer; v-grooves.
Detailed Description
Based on the above research, the embodiment of the present invention provides a test key structure. The invention is described in further detail below with reference to the figures and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted, however, that the drawings are designed in a simplified form and are not to scale, but rather are to be construed in an illustrative and descriptive sense only and not for purposes of limitation.
An embodiment of the present invention provides a test key structure, including:
the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit.
The distances between the adjacent test pads on the test key unit are not completely the same, that is, the test pads with non-uniform distances are adopted, and the test pads with asymmetric structures are designed, so that the test pad sequence on the test key unit is easily distinguished. The problem of in the conventional test key unit design, the test pad interval is even equidistance, and when whole test key unit was the axisymmetric structure, the difficult lower needle position of distinguishing leads to the risk of erroneous judgement to and have the difficult test pad order of distinguishing behind the wafer turn-over is solved.
It should be appreciated that, for example, in the conventional test key unit design, the pitches of the plurality of test pads are uniformly and equidistantly spaced, and the pitches of the plurality of test pads are still equidistant after the wafer is turned over, so that it is difficult to distinguish the sequence of the test pads.
FIG. 1 is a diagram of a test key structure according to an embodiment of the present invention. As shown in fig. 1, at least one Test key unit T is disposed in the wafer, for example, in the scribe lane. The test key unit T refers to a test unit that is added to a wafer fixing position in order to monitor a process during wafer processing in a semiconductor foundry.
The test key unit T is provided with a plurality of elements to be tested and a plurality of test pads (metal bonding pads) distributed at intervals, the distances between the adjacent test pads are not completely the same, and the plurality of test pads in the test key unit T are asymmetric about the central axis of the test key unit T. The device under test is labeled 1, 2, y and z, and is at least one of a transistor, a capacitor, a resistor, an N-type semiconductor, a P-type semiconductor, a compound semiconductor or a metal wire element.
For example, the dut is exemplified by a transistor, and each dut is connected to 3 test pads. The device under test 1 is electrically connected to the test pads 12, 13 and the first common pad C1, respectively. The device under test 2 is electrically connected to the test pad 22, the test pad 23, and the first common pad C1, respectively. The device under test y is electrically connected to the test pad y2, the test pad y3, and the first common pad C1, respectively. For example, the source, the drain and the gate of the transistor are respectively connected with the test pad through metal wires; any one of the optional source, drain and gate serves as a common electrode, for example, the source of each device under test is electrically connected to the first common pad C1. The source of the device under test 1 is connected to the first common pad C1, the gate of the device under test 1 is connected to the test pad 12, the drain of the device under test 1 is connected to the test pad 13, and so on for other devices under test.
Preferably, the test key units T are distributed in the scribe lines of the wafer, and the plurality of devices to be tested and the plurality of test pads in the test key units T are arranged in a single row. The minimum spacing between adjacent test pads may be a design rule minimum spacing, b being a design rule minimum spacing. And the element to be tested is not arranged in the minimum spacing b between the adjacent test pads. Illustratively, the spacing between the leftmost test pad C1 and the test pad 12 within the test key unit T is a minimum of b, the spacing between the test pad 12 and the test pad 13 is C, b ≠ C, and b < C. No device to be tested is arranged in the minimum distance b, and the distances between other adjacent test pads in the row direction can be equal, namely c, d, e, f and g can be equal.
The distance a between the adjacent test key units T is larger than or equal to the minimum distance b between the adjacent test pads.
Fig. 1 shows a first test key structure a with a minimum spacing b in the test key unit T arranged between a first test pad (first common pad C1) and a second test pad (test pad 12). It should be understood that the minimum spacing b may also be provided between subsequent adjacent test pads. Fig. 2 shows a second test key structure B, which is shown in fig. 2, in which the minimum distance B within the test key unit T is arranged between the second test pad (test pad 13) and the third test pad (first common pad C1). Illustratively, the test pad on the side of the minimum pitch b is defined as the first common pad C1.
Each element to be tested is electrically connected with at least one adjacent test pad. When the device under test is, for example, a capacitor or a resistor, the device under test has two testing terminals, one testing terminal of each device under test is electrically connected to its adjacent testing pad, and the other testing terminal of each device under test can be electrically connected to the common testing pad.
Fig. 1 and 2 show that the device under test has three testing terminals, two testing terminals of each device under test are electrically connected to two adjacent testing pads respectively, and the third testing terminal of each device under test can be electrically connected to a common testing pad.
FIG. 3 shows a third test key structure C, as shown in FIG. 3, each DUT has four test terminals, two test terminals of each DUT are electrically connected to two adjacent test pads respectively, a third test terminal of each DUT is electrically connected to the first common pad C1, and a fourth test terminal of each DUT is electrically connected to the second common pad C2. In this embodiment, each device to be tested is connected to 4 test pads. The elements to be tested of the test key unit and the test pads are arranged in a single row and are arranged in the cutting channel. The device under test is, for example, a transistor, a substrate terminal of which is also to be tested, and the fourth test terminal is, for example, a substrate, and the substrate of each device under test is electrically connected to the second common pad C2. Any one of the optional source electrode, the optional drain electrode and the optional grid electrode is used as a common electrode, for example, the source electrode of each element to be tested is electrically connected with the first common pad C1; it is also possible to connect the sources and drains of different devices under test to a common electrode, for example, to electrically connect both the source of the PMOS transistor and the drain of the NMOS transistor to the first common pad C1. The source of the element to be tested 1 is connected with the first common pad C1, the gate of the element to be tested 1 is connected with the test pad 12, the drain of the element to be tested 1 is connected with the test pad 13, the substrate end of the element to be tested 1 is connected with the second common pad C2, and so on for other elements to be tested.
The present embodiment further provides a wafer stacking structure, as shown in fig. 1, 4 to 6b, including:
a bottom wafer 10 and a top wafer 20; a first surface of the bottom wafer 10 faces a first surface of the upper wafer 20;
the test key structures introduced above are distributed on both the first surface of the bottom wafer 10 and the first surface of the upper wafer 20, and the test key structure a located on the first surface of the bottom wafer 10 is mirror symmetric to the test key structure D located on the first surface of the upper wafer 20.
Fig. 5 is a schematic diagram of a wafer stack structure according to an embodiment of the invention. Fig. 6a is a schematic diagram of a first test key unit T1 in the test key structure a on the bottom wafer 10 according to the embodiment of the present invention. Fig. 6b is a diagram illustrating a second test key unit T2 in the test key structure D on the upper wafer 20 according to the embodiment of the present invention.
The first surface (front or back) of the bottom wafer 10 is distributed with test structures a, and the test structures a include at least one first test key unit T1. The first surface (front or back) of the upper wafer is distributed with test structures D, and the test structures D include at least one second test key unit T2. The second test key unit T2 is also mirror symmetric to the first test key unit T1.
Turning the upper layer wafer 20 and bonding the upper layer wafer with the bottom layer wafer 10; after the upper wafer 20 is turned over, the arrangement sequence and the pitch of the pads (the test pads and the common pads) on the test structure D are the same as the arrangement sequence and the pitch distribution of the pads (the test pads and the common pads) on the test structure a on the bottom wafer 10 when viewed from the side of the upper wafer 20 away from the bonding surface; and the pad (test pad and common pad) arrangement order and pitch distribution of the second test key unit T2 and the first test key unit T1 are the same when viewed from the side of the upper wafer 20 away from the bonding surface. Under the lamination process, the bottom layer wafer 10 and the upper layer wafer 20 use a mirror image design, and the directions of the Test key (Test key) units T are ensured to be consistent after the lamination process.
As shown in fig. 5, the first test key unit T1 is bonded face-to-face with the upper bonding metal layer H2 located thereabove, and pads (test pads and common pads) in the first test key unit T1 are electrically connected with pads in the upper bonding metal layer. The pads in the upper bonding metal layer are distributed corresponding to the pads in the first test key unit T1. The second test key unit T2 is face-to-face bonded with the underlying bonding metal layer H1 located therebelow. In an embodiment, the pads (test pads and common pads) in the second test key cell T2 may be electrically connected with the pads in the underlying bond metal layer H1. The pads in the bottom bonding metal layer H1 are distributed corresponding to the pads in the second test key cell T2. In other embodiments, the bottom bonding metal layer H1 may also be a dummy (dummy) metal layer, and there is no substantial device signal in the bottom bonding metal layer H1, and only the metal layer distribution balance on the wafer is satisfied, so as to prevent the bonding effect from being reduced due to different material stresses in combination with the pads in the second test key unit T2.
The wafer stack structure further includes: the groove, the plug and the lead-out pad. The groove penetrates through one side of the upper wafer 20 far away from the bonding surface to the bonding pads (the test pads and the common pads) in the second test key unit T2 which respectively expose the upper bonding metal layer H2 and the upper wafer. Illustratively, the groove sequentially penetrates through the substrate and the dielectric layer of the upper wafer, and exposes the bonding pads in the upper bonding metal layer H2 and the second test key unit T2 in the dielectric layer, respectively. The plugs K are filled in the grooves and electrically connected to the upper bonding metal layer H2 and the test pads of the second test key unit T2, respectively.
The lead-out pad is positioned on the surface of one side of the upper wafer 20 far away from the bonding surface; the lead-out pads comprise a first lead-out pad P1 and a second lead-out pad P2, and the first lead-out pad P1, the plug K, the upper bonding metal layer H2 and the test pads in the first test key unit T1 are electrically connected in sequence; the second lead pad P2, the plug K, and the test pad in the second test key unit T2 are electrically connected in this order. The material of the lead pad includes copper or aluminum and other suitable materials.
The plug can be made of copper or tungsten, and can be formed by electroplating. The first lead pad P1 is electrically connected to a pad in the first test key cell T1 through the upper bonding metal layer H2. The second lead pad P2 is electrically connected to a pad in the second test key unit T2. In another embodiment, the upper bonding metal layer H2 and the second test key unit T2 are respectively connected to the metal layer far away from the bonding surface through a re-routing structure (RDL), and the grooves penetrate through the side of the upper wafer 20 far away from the bonding surface to expose the corresponding metal layer far away from the bonding surface.
The probe needles on the probe card test the first test key unit T1 by contacting the first lead-out pads P1, and the probe needles on the probe card test the second test key unit T2 by contacting the second lead-out pads P2. Since the second test key unit T2 and the first test key unit T1 have the same arrangement order and pitch distribution of the pads (test pads and common pads) when viewed from the side of the upper wafer 20 away from the bonding surface, the probes on the probe card only need to set one set of test program and probes for testing the first test key unit T1 and the second test key unit T2, and the test program includes the arrangement order and pitch distribution of the corresponding probes. When the first test key unit T1 needs to be tested, the probe set arranged on the probe card is shifted to a position above the first test key unit T1 for corresponding testing; when the second test key unit T2 needs to be tested, the probe sets arranged and distributed on the probe card are entirely shifted to the position above the second test key unit T2 for corresponding test, that is, different probe test programs need to be respectively arranged for the reason that the conventional pad arrangement is different for the merged bottom wafer 10 and the upper wafer 20, and only one set of test program is needed to complete the test of the wafer stacking structure.
WAT (wafer Acceptance Test) Test, for testing a Test Key (Test Key) unit on a wafer scribing channel, whether the process of each step is normal and stable is monitored through electrical parameters, generally before the wafer finishes the process, the wafer is delivered from a factory to a sealed Test factory, the Test method is that a probe is pricked on a Test pad (metal pad) of the Test Key unit, the other end of the probe card is connected to a WAT Test machine, the WAT Recipe automatically controls the Test position and content, and after a certain Test Key unit is tested, the probe card can automatically move to the next Test Key unit until the whole wafer is tested.
The probe card must use the same design specifications as the test key units on the wafer. Since the probe card is fixed on the probe stage, the direction of the test key unit and the direction of the wafer notch (notch) are defined. The pin cards are unevenly spaced and are asymmetric defining a unique pin down position.
This embodiment tests the design of uneven spacing and asymmetric test pads on the key unit: when the test pad pitch is non-uniform (b ≠ c) and the test key unit T is not in an axisymmetric pattern, there is a significant difference in the pitch (e.g., b and g) across the test key unit T, for example. And after the wafer is turned over, the sequence of the test pads can be judged according to the change of the spacing.
The arrangement of the probe card is determined by the arrangement design of the test pads on the test key unit T, and the pin pitch of the probe card must correspond to the pitch of the test pads. After the test pad position is set by the parameter (recipe), the probe card tip position (as shown in FIG. 7) is formed, and then aligned with the probe card tip image (as shown in FIG. 8) one by one to start the test. Due to the non-uniform asymmetric design used and the probe card is not rotatable, the test key unit orientation becomes unique. The risk of selecting a wrong test pad between adjacent test key units is also absent due to uneven pin spacing.
WAT, Wafer Acceptance Test, which is the Test of the Test key unit before the Wafer leaves the factory. In the wafer manufactured by the standard process, a plurality of special patterns for special test are placed on the scribing channels among the chips, namely, the test key units. This is independent of the chip's own function, which is responsible for the Fab detection of process fluctuations. The WAT needs to mark the die that failed the test and only needs to encapsulate the die that passed the test. In one embodiment, the test pads are formed using the same process used to form the semiconductor devices, allowing the process to be tested and verified without contaminating or disturbing the production devices. The test pads may be formed in dicing streets of the wafer such that the test pads are removed during dicing and the area of the wafer is saved. Placing test pads on production wafers, rather than using sacrificial wafers for testing, may reduce wafer-to-wafer variation that may not be perceptible with dedicated test wafers. A test key cell with one or more test pads may also allow testing of a range of physical properties, such as strain relaxation, dopant activation and deactivation, and the like.
In summary, the present invention provides a test key structure, including: the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit. The distances between the adjacent test pads on the test key unit are not completely the same, that is, the test pads with non-uniform distances and the test pad design with an asymmetric structure are adopted, so that the test pad sequence on the test key unit is easily distinguished. The invention provides a method for judging the sequence of WAT test pads by flesh eyes, which reduces the risk of errors when a test program is established and can obviously reduce the time for troubleshooting. The risk of human misoperation when confirming the position of the lower needle is eliminated from the design. And wafer testing of the lamination process is realized, and testing procedures of single wafers are combined, so that the testing time is saved. And reduces the manpower of rewriting the test program and the risk of error. The time and the error rate of program establishment are reduced, the testing steps and the testing time are reduced, errors in manual operation are avoided, and the occupied area of the WAT test key structure is reduced.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, the description is relatively simple because the method corresponds to the device disclosed by the embodiment, and the relevant points can be referred to the description of the method part.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the claims of the present invention, and any person skilled in the art can make possible the variations and modifications of the technical solutions of the present invention using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention, and therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention belong to the protection scope of the technical solutions of the present invention.
Claims (13)
1. A test key structure, comprising: the test key unit is provided with a plurality of elements to be tested and a plurality of test pads distributed at intervals, the distance between every two adjacent test pads is not completely the same, and the plurality of test pads in the test key unit are asymmetric about the central axis of the test key unit.
2. The test key structure of claim 1, wherein the minimum spacing between adjacent test pads is a design rule minimum spacing.
3. The test key structure of claim 2, wherein the test key units are distributed in scribe lines of the wafer, and a plurality of the devices under test and a plurality of the test pads in the test key units are arranged in a single row.
4. The test key structure of claim 2, wherein no device under test is disposed within the minimum spacing between adjacent test pads.
5. The test key structure of claim 2, wherein a distance between adjacent test key units is greater than a minimum spacing between adjacent test pads.
6. The test key structure of claim 2, wherein the test key structure comprises a first common pad, and a test end of each of the plurality of devices under test is electrically connected to the first common pad.
7. The test key structure of claim 6, wherein each of the devices under test is electrically connected to at least one of the test pads adjacent thereto.
8. The test key structure of claim 6, wherein the plurality of test pads comprises a second common pad, and a test end of each of the plurality of devices under test is electrically connected to the second common pad.
9. The test key structure of claim 6, wherein the test pad on the side of the minimum pitch is defined as the first common pad.
10. A wafer stack structure, comprising:
a bottom wafer and an upper wafer; the first surface of the bottom wafer is bonded to the first surface of the upper wafer;
the first surface of the bottom wafer and the first surface of the upper wafer are both distributed with the test key structure of any one of claims 1 to 9, and the test key structure on the first surface of the bottom wafer and the test key structure on the first surface of the upper wafer are mirror symmetric.
11. The wafer stack structure of claim 10,
the test key structure on the first surface of the bottom wafer comprises at least one first test key unit,
the test key structure on the first surface of the upper wafer comprises at least one second test key unit, and the second test key unit is in mirror symmetry with the first test key unit.
12. The wafer stack structure of claim 11,
the first surface of the bottom wafer is further provided with a bottom bonding metal layer, the first surface of the upper wafer is further provided with an upper bonding metal layer, the first test key unit faces the upper bonding metal layer for bonding, and the second test key unit faces the bottom bonding metal layer for bonding.
13. The wafer stack structure of claim 12, further comprising:
the groove penetrates through one side of the upper layer wafer, which is far away from the bonding surface, to respectively expose the upper layer bonding metal layer and the second test key unit;
the plug is filled in the groove and is electrically connected with the upper bonding metal layer and the test pad of the second test key unit respectively;
the lead-out bonding pad is positioned on the surface of one side, far away from the bonding surface, of the upper wafer; the leading-out bonding pad comprises a first leading-out bonding pad and a second leading-out bonding pad, and the first leading-out bonding pad, the plug, the upper bonding metal layer and the test pad in the first test key unit are electrically connected in sequence; the second lead-out pad, the plug and the test pad in the second test key unit are electrically connected in sequence.
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