CN113270133A - Test circuit and test method of charge pump - Google Patents

Test circuit and test method of charge pump Download PDF

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Publication number
CN113270133A
CN113270133A CN202110536787.3A CN202110536787A CN113270133A CN 113270133 A CN113270133 A CN 113270133A CN 202110536787 A CN202110536787 A CN 202110536787A CN 113270133 A CN113270133 A CN 113270133A
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China
Prior art keywords
switch tube
charge pump
mos transistor
capacitor
test circuit
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付先锋
夏仲仪
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202110536787.3A priority Critical patent/CN113270133A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The application provides a test circuit and a test method of a charge pump, comprising the following steps: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor; the second end of the second switch tube is connected with the second end of the capacitor; the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor. Therefore, the test circuit of the charge pump provided by the embodiment of the application can effectively test whether the output voltage and the output current of the charge pump are abnormal or not by conducting the first switch tube and the second switch tube at different times so that the first switch tube and the second switch tube alternately charge and discharge the capacitor, that is, by using the first switch tube, the second switch tube and the capacitor as the load of the charge pump.

Description

Test circuit and test method of charge pump
Technical Field
The present invention relates to the field of semiconductors, and in particular, to a test circuit and a test method for a charge pump.
Background
Burn-in testing is currently also performed on 3D NAND memory devices after they are manufactured. The 3D NAND memory device can be repeatedly subjected to the cycle of the erasing process, the reading process, the writing process and the reading process during the aging test, and a charge pump circuit is utilized to provide high voltage for the erasing process of the 3D NAND memory device during the erasing process of the 3D NAND memory device.
However, before the charge pump provides high voltage for the 3D NAND memory device erase/write process, the charge pump circuit itself needs to be tested, and an effective method for testing the charge pump is now continued.
Disclosure of Invention
In view of the above, the present application provides an efficient method and circuit for testing a charge pump.
The embodiment of the application provides a test circuit of a charge pump, including: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor;
the second end of the second switch tube is connected with the second end of the capacitor;
the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor.
Optionally, the first switching tube is a first metal oxide semiconductor field effect MOS transistor, and the second switching tube is a second MOS transistor;
the drain electrode of the first MOS transistor is connected with the output end of the charge pump, and the source electrode of the first MOS transistor is connected with the drain electrode of the second MOS transistor and the first end of the capacitor;
the source electrode of the second MOS transistor is connected with the second end of the capacitor;
the gates of the first MOS transistor and the second MOS transistor are connected with clock signals with complementary phases, so that the first MOS transistor and the second MOS transistor alternately charge and discharge the capacitor under the driving of the clock signals with complementary phases.
Optionally, the channel types of the first MOS transistor and the second MOS transistor are the same.
Optionally, the first MOS transistor and the second MOS transistor are N-type MOS transistors.
Optionally, the method further includes: an inverter;
the phase complementary clock signals are obtained using the inverters.
Optionally, the method further includes: a clock module;
the clock module is used for outputting the clock signal with a preset frequency.
Optionally, the method further includes: a switch unit;
the first end of the switch unit is connected with the output end of the charge pump, and the second end of the switch unit is connected with the first switch tube and used for being switched on when the charge pump outputs high voltage.
Optionally, the charge pump is used for providing a high voltage for an erasing process of the 3D NAND memory device.
The embodiment of the application provides a test method of a charge pump, and by using the test circuit in the embodiment, if the equivalent current of the test circuit is greater than a preset value, the test result indicates that a fault unit exists in the charge pump.
Optionally, the equivalent current of the test line is equal to a product of a voltage difference value, a capacitance value of the capacitor, and a frequency of the clock signal, where the voltage difference value is a difference between a source and a drain of the MOS transistor minus a turn-on voltage of the MOS transistor.
The test circuit of charge pump that this application embodiment provided includes: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor; the second end of the second switch tube is connected with the second end of the capacitor; the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor.
Therefore, the test circuit of the charge pump provided by the embodiment of the application can effectively test whether the output voltage and the output current of the charge pump are abnormal or not by conducting the first switch tube and the second switch tube at different times so that the first switch tube and the second switch tube alternately charge and discharge the capacitor, that is, by using the first switch tube, the second switch tube and the capacitor as the load of the charge pump.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 shows a schematic diagram of a charge pump circuit in the prior art;
FIG. 2 is a schematic diagram illustrating a test circuit of a charge pump according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram illustrating a test circuit of another charge pump according to an embodiment of the present disclosure.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, embodiments accompanying the present application are described in detail below with reference to the accompanying drawings.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited by the specific embodiments disclosed below.
Next, the present application will be described in detail with reference to the drawings, and in the detailed description of the embodiments of the present application, the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration, and the drawings are only examples, which should not limit the scope of the protection of the present application. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
As described in the background section, burn-in tests are currently performed on 3D NAND memory devices after the 3D NAND memory devices are manufactured. The 3D NAND memory device can be repeatedly subjected to the cycle of the erasing process, the reading process, the writing process and the reading process during the aging test, and a charge pump circuit is utilized to provide high voltage for the erasing process of the 3D NAND memory device during the erasing process of the 3D NAND memory device. Referring to fig. 1, a schematic diagram of a charge pump circuit in the prior art is shown, where load represents a portion of the charge pump circuit connected to a load.
However, before the charge pump provides high voltage for the 3D NAND memory device erase/write process, the charge pump circuit itself needs to be tested, and an effective method for testing the charge pump is now continued.
At present, for testing a charge pump, in the prior art, a charge pump circuit is not connected with any load, and the output voltage and the output current of the charge pump are directly tested, but the test result is poor. In the prior art, a resistance load is connected to a charge pump circuit to reduce the power consumption of the charge pump and improve the output voltage capability, so that a very large resistance load needs to be connected, the very large resistance load occupies a large area of a 3D NAND memory device, and the manufacturing cost of the device is increased.
Based on this, this application embodiment provides a test circuit of charge pump, includes: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor; the second end of the second switch tube is connected with the second end of the capacitor; the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor.
Therefore, the test circuit of the charge pump provided by the embodiment of the application can effectively test whether the output voltage and the output current of the charge pump are abnormal or not by conducting the first switch tube and the second switch tube at different times so that the first switch tube and the second switch tube alternately charge and discharge the capacitor, namely, the first switch tube, the second switch tube and the capacitor are used as the load of the charge pump, and the test circuit provided by the embodiment of the application does not need to design a large resistance load, so that the area of a 3D NAND memory device is saved, the manufacturing cost of the device is reduced, in addition, the test circuit composed of the capacitor and the switch tube is insensitive to the temperature change, the stability of the test circuit can be increased, and the accuracy of the test result obtained when the test circuit tests is higher than that obtained when the test circuit tests by using the resistor.
For a better understanding of the technical solutions and effects of the present application, specific embodiments will be described in detail below with reference to the accompanying drawings.
Referring to fig. 2, a test circuit of a charge pump for providing a high voltage for an erase/write process of a 3D NAND memory device is provided according to an embodiment of the present application. The test circuit 200 may include: a first switch tube 210, a second switch tube 220 and a capacitor 230. The switch tube is composed of a controllable switch tube, and the type of the controllable switch tube can be any one of the following types: an Insulated Gate Bipolar Transistor (IGBT), a Metal Oxide Semiconductor field Effect Transistor (MOSFET, hereinafter referred to as MOS Transistor), a SiC MOSFET (Silicon Carbide field Effect Transistor), and the like. The capacitor 230 may be a fixed capacitor or a gate oxide capacitor.
In the embodiment of the present application, a first terminal of the first switching tube 210 is connected to the output terminal of the charge pump, and a second terminal of the first switching tube 210 is connected to a first terminal of the second switching tube 220 and a first terminal of the capacitor 230. A first terminal of the second switch tube 220 is connected to a first terminal of the capacitor 230, and a second terminal of the second switch tube 220 is connected to a second terminal of the capacitor 230.
In the embodiment of the present application, the first switch tube 210 and the second switch tube 220 are not turned on at the same time, so that the first switch tube 210 and the second switch tube 220 alternately charge and discharge the capacitor 230. That is, when the output end of the charge pump outputs a voltage, the first switch tube 210 is turned on, the second switch tube 220 is turned off, the voltage output by the output end of the charge pump charges the capacitor 230, the first switch tube 210 is turned off, the second switch tube 220 is turned on, and the capacitor 230 is discharged through the second switch tube 230.
In the embodiment of the present application, a voltage detection device or a current detection device may be connected to the output end of the test circuit 200, the voltage or the current when the voltage output by the output end of the charge pump passes through the test circuit is tested, if the current passing through the test circuit is greater than a predetermined value or the voltage is less than the predetermined value, the test result indicates that a fault unit exists in the charge pump, which is because the current passing through the test circuit is greater than the predetermined value, it indicates that the power consumption of the charge pump is very large, and most of the voltage is not output to the load; otherwise, if the current passing through the test circuit is smaller than the preset value or the voltage is larger than the preset value, the test result is that the charge pump is normal.
In the embodiment of the present application, the equivalent current of the test line is proportional to the product of the capacitance value of the capacitor 230 and the frequency of the clock signal. The equivalent current of the test line is equal to the product of the voltage difference, which is the voltage difference between the source and drain of the MOS transistor minus the turn-on voltage of the MOS transistor, the capacitance of the capacitor 230, and the frequency of the clock signal, and the reference formula is as follows:
Figure BDA0003069950110000051
where Q is the amount of charge when the capacitor C is charged, f is 1/T, f is the frequency of the clock signal, C is the capacitance of the capacitor 230, VgsIs the difference between the source and drain voltages of the MOS transistor in saturation, VtIs the turn-on voltage of the MOS transistor.
In an embodiment of the present application, the first switching transistor 210 may be a first metal oxide semiconductor field effect transistor, i.e., a first MOS transistor 211. Similarly, the second switching transistor 220 may also be a second MOS transistor 221. At this time, referring to fig. 3, the drain of the first MOS transistor 211 is connected to the output terminal of the charge pump, and the source of the first MOS transistor 211 is connected to the drain of the second MOS transistor 221 and the first terminal of the capacitor 230. The drain of the second MOS transistor 221 is connected to the first terminal of the capacitor 230, and the source of the second MOS transistor 221 is connected to the second terminal of the capacitor 230.
The gates of the first MOS transistor 211 and the second MOS transistor 221 are connected to the clock signals with complementary phases, so that the first MOS transistor 211 and the second MOS transistor 221 alternately charge and discharge the capacitor 230 under the driving of the clock signals with complementary phases. That is, the gate of the first MOS transistor 211 is connected to the first clock signal to drive the first MOS transistor 211 to turn on and off, and the gate of the second MOS transistor 221 is connected to the second clock signal to drive the second MOS transistor 221 to turn on and off. The phase of the second clock signal is opposite to the phase of the first clock signal, that is, the phase of the second clock signal is complementary to the phase of the first clock signal, so that under the driving of two clock signals with complementary phases, the second MOS transistor 221 is turned off when the first MOS transistor 211 is controlled to be turned on, and when the output end of the charge pump outputs a voltage, the voltage output by the output end of the charge pump charges the capacitor 230; when the first MOS transistor 211 is controlled to be turned off, the second MOS transistor 221 is turned on, and the capacitor 230 is discharged through the second MOS transistor 221.
In practical applications, the channel types of the first MOS transistor 211 and the second MOS transistor 221 may be the same or different. The N-type MOS transistor has lower power consumption and higher conductivity than the P-type MOS transistor, and thus the first MOS transistor 211 and the second MOS transistor 221 can be selected as N-type MOS transistors.
In an embodiment of the present application, the test circuit 200 may further include: an inverter. The inverters may be used to provide phase complementary clock signals, which are input to the gates of the first and second MOS transistors 211 and 221. In practical application, the inverter can multiplex the inverters already arranged in the 3D NAND memory device, i.e., one inverter does not need to be arranged in the test circuit 200, so that the area of the 3D NAND memory device occupied by the test circuit 200 can be saved, and the manufacturing cost of the device can be reduced.
In an embodiment of the present application, the test circuit 200 may further include: and a clock module. The clock module may be configured to output a clock signal of a predetermined frequency, which is input to an inverter that provides two clock signals with complementary phases using the clock signal. In practical application, the clock module can multiplex the clock modules already arranged in the 3D NAND memory device, i.e., a clock module does not need to be arranged in the test circuit 200 separately, so that the area of the 3D NAND memory device occupied by the test circuit 200 can be saved, and the manufacturing cost of the device can be reduced.
In an embodiment of the present application, the test circuit 200 may further include: a switch unit. The first end of the switch unit is connected to the output end of the charge pump, and the second end of the switch unit is connected to the first switching tube 210 or the first MOS transistor 211, and is used for turning on when the output high voltage of the charge pump is outputted, so as to connect the test circuit 200 to test the charge pump.
The test circuit of charge pump that this application embodiment provided includes: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor; the second end of the second switch tube is connected with the second end of the capacitor; the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor.
Therefore, the test circuit of the charge pump provided by the embodiment of the application can effectively test whether the output voltage and the output current of the charge pump are abnormal or not by conducting the first switch tube and the second switch tube at different times so that the first switch tube and the second switch tube alternately charge and discharge the capacitor, that is, by using the first switch tube, the second switch tube and the capacitor as the load of the charge pump.
Based on the test circuit of the charge pump provided by the above embodiment, the embodiment of the application also provides a test method of the charge pump.
The method for testing the charge pump provided by the embodiment of the present application can utilize the test circuit of the charge pump described in the foregoing embodiment. The method for testing the charge pump provided by the embodiment of the application comprises the following steps:
the output end of the test circuit 200 is connected with a voltage detection device or a current detection device, the voltage or the current of the voltage output by the output end of the charge pump when passing through the test circuit is tested, if the current passing through the test circuit is larger than a preset value or the voltage is smaller than the preset value, the test result is that a fault unit exists in the charge pump, because the current passing through the test circuit is larger than the preset value, the power consumption of the charge pump is very large, and most of the voltage is not output to a load; otherwise, if the current passing through the test circuit is smaller than the preset value or the voltage is larger than the preset value, the test result is that the charge pump is normal.
In the embodiment of the present application, the equivalent current of the test line is proportional to the product of the capacitance value of the capacitor 230 and the frequency of the clock signal. The equivalent current of the test line is equal to the product of the voltage difference, which is the voltage difference between the source and drain of the MOS transistor minus the turn-on voltage of the MOS transistor, the capacitance of the capacitor 230, and the frequency of the clock signal, and the reference formula is as follows:
Figure BDA0003069950110000081
where Q is the amount of charge when the capacitor C is charged, f is 1/T, f is the frequency of the clock signal, C is the capacitance of the capacitor 230, VgsIs the difference between the source and drain voltages of the MOS transistor in saturation, VtIs the turn-on voltage of the MOS transistor.
Therefore, according to the test method of the charge pump provided by the embodiment of the application, the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor, that is, the first switch tube, the second switch tube and the capacitor are used as a load of the charge pump, and whether the output voltage and the output current of the charge pump are abnormal or not can be effectively tested.
The foregoing is merely a preferred embodiment of the present application and, although the present application discloses the foregoing preferred embodiments, the present application is not limited thereto. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

Claims (10)

1. A circuit for testing a charge pump, comprising: the first end of the first switch tube is connected with the output end of the charge pump, and the second end of the first switch tube is connected with the first end of the second switch tube and the first end of the capacitor;
the second end of the second switch tube is connected with the second end of the capacitor;
the first switch tube and the second switch tube are not conducted at the same time, so that the first switch tube and the second switch tube alternately charge and discharge the capacitor.
2. The test circuit of claim 1, wherein the first switch transistor is a first metal oxide semiconductor field effect transistor (MOS) transistor, and the second switch transistor is a second MOS transistor;
the drain electrode of the first MOS transistor is connected with the output end of the charge pump, and the source electrode of the first MOS transistor is connected with the drain electrode of the second MOS transistor and the first end of the capacitor;
the source electrode of the second MOS transistor is connected with the second end of the capacitor;
the gates of the first MOS transistor and the second MOS transistor are connected with clock signals with complementary phases, so that the first MOS transistor and the second MOS transistor alternately charge and discharge the capacitor under the driving of the clock signals with complementary phases.
3. The test circuit of claim 2, wherein the channel type of the first MOS transistor and the second MOS transistor is the same.
4. The test circuit of claim 3, wherein the first and second MOS transistors are N-type MOS transistors.
5. The test circuit of claim 2, further comprising: an inverter;
the phase complementary clock signals are obtained using the inverters.
6. The test circuit of claim 5, further comprising: a clock module;
the clock module is used for outputting the clock signal with a preset frequency.
7. The test circuit of any one of claims 1-6, further comprising: a switch unit;
the first end of the switch unit is connected with the output end of the charge pump, and the second end of the switch unit is connected with the first switch tube and used for being switched on when the charge pump outputs high voltage.
8. The test circuit of any of claims 1-6, wherein the charge pump is configured to provide a high voltage for 3D NAND device erase/write.
9. A method for testing a charge pump, using the test circuit of any one of claims 1-8, wherein if the equivalent current of the test circuit is greater than a predetermined value, the test result is that a faulty cell exists within the charge pump.
10. The method of claim 9, wherein the equivalent current of the test line is equal to a voltage difference value, which is a voltage difference of a source and a drain of a MOS transistor minus a turn-on voltage of the MOS transistor, a product of a capacitance value of the capacitor and a frequency of the clock signal.
CN202110536787.3A 2021-05-17 2021-05-17 Test circuit and test method of charge pump Pending CN113270133A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050012002A (en) * 2003-07-24 2005-01-31 주식회사 하이닉스반도체 Semiconductor memory device with ability of testing charge pump circuit for internal voltage
JP2012175828A (en) * 2011-02-22 2012-09-10 Panasonic Corp Current detection circuit of step-up converter
CN108767944A (en) * 2018-08-22 2018-11-06 上海艾为电子技术股份有限公司 A kind of switched charge circuit
CN112730958A (en) * 2020-12-22 2021-04-30 海光信息技术股份有限公司 Voltage overshoot detection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20050012002A (en) * 2003-07-24 2005-01-31 주식회사 하이닉스반도체 Semiconductor memory device with ability of testing charge pump circuit for internal voltage
JP2012175828A (en) * 2011-02-22 2012-09-10 Panasonic Corp Current detection circuit of step-up converter
CN108767944A (en) * 2018-08-22 2018-11-06 上海艾为电子技术股份有限公司 A kind of switched charge circuit
CN112730958A (en) * 2020-12-22 2021-04-30 海光信息技术股份有限公司 Voltage overshoot detection circuit

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