CN113268415A - Interlocking rule automatic test system and method based on test case - Google Patents
Interlocking rule automatic test system and method based on test case Download PDFInfo
- Publication number
- CN113268415A CN113268415A CN202110511344.9A CN202110511344A CN113268415A CN 113268415 A CN113268415 A CN 113268415A CN 202110511344 A CN202110511344 A CN 202110511344A CN 113268415 A CN113268415 A CN 113268415A
- Authority
- CN
- China
- Prior art keywords
- test
- module
- test case
- interlocking
- station
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 287
- 238000000034 method Methods 0.000 title claims abstract description 32
- 238000004088 simulation Methods 0.000 claims description 42
- 238000004891 communication Methods 0.000 claims description 39
- 238000004458 analytical method Methods 0.000 claims description 18
- 230000009191 jumping Effects 0.000 claims description 18
- 230000008859 change Effects 0.000 claims description 11
- 230000005279 excitation period Effects 0.000 claims description 9
- 238000010998 test method Methods 0.000 claims description 7
- 230000000737 periodic effect Effects 0.000 claims description 4
- 230000006870 function Effects 0.000 description 46
- 238000012423 maintenance Methods 0.000 description 6
- 238000012790 confirmation Methods 0.000 description 5
- 230000005284 excitation Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 4
- 230000014509 gene expression Effects 0.000 description 4
- 230000003993 interaction Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000002452 interceptive effect Effects 0.000 description 2
- 238000005192 partition Methods 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005347 demagnetization Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3684—Test management for test design, e.g. generating new test cases
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/362—Software debugging
- G06F11/3648—Software debugging using additional hardware
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
The invention discloses an automatic interlocking rule testing system and method based on a test case, and relates to the technical field of rail transit interlocking control.
Description
Technical Field
The invention relates to the technical field of rail traffic interlocking control, in particular to an interlocking rule automatic test system and method based on test cases.
Background
The interlocking refers to a mutual restriction relationship among the signalers, the turnouts and the approaches, and has the main function of ensuring the correct logic among the approaches, the turnouts and the signalers and preventing driving accidents; meanwhile, the computer interlock can improve the working efficiency and reduce the labor intensity.
The realization mode of the present interlocking logic mainly comprises 2 types, one type is realized based on a high-level language C, and the interlocking logic is realized by defining a route selection and switch moving program module, a route establishing program module, a route locking program module, a signal opening program module, a route unlocking program module and the like by adopting a process-oriented idea; the other method is realized by adopting open Boolean algebra, the thought and the method of a relay interlocking shaping circuit are used for converting the Boolean algebra into a Boolean expression with an operational relationship, all the Boolean expressions are calculated according to a specified sequence to realize interlocking logic, and a universal interlocking rule is used as the root of safe and reliable operation of an interlocking system in an actual field, the reliable and effective confirmation test work of the interlocking rule plays a crucial role in ensuring the normal application of a field signal system; for example, in the currently common interlocking system based on the boolean logic operation with the variable running period of the lower computer, the operation logic is abstracted into a general interlocking rule by an interlocking rule developer according to the functional requirements of the interlocking system through input information of other subsystems of a track signal system and processing of state acquisition information of trackside signal equipment, the signal equipment is configured by the designer according to specific application of an actual project, and the general interlocking rule is instantiated through a boolean expression generation tool to generate a boolean logic expression of the interlocking operation specific to the specific application.
Different implementations of interlock logic have benefits, but in any event, the problem of automatic testing of interlock data needs to be investigated. In the existing interlocking rule confirmation test method, after each time of the interlocking rule is modified and iterated, when a confirmation test is performed, a tester needs to manually execute relevant operations on a test station upper computer interface after the universal rule is instantiated according to a test case and record the jump process of a Boolean variable, and then an analyst analyzes a parameter time sequence according to a test record and judges the correctness of rule design, the traditional rule confirmation test mode has huge requirements on test manpower and analysis manpower, low execution efficiency and high requirements on the capability of rule test and parameter analysts, and if the tester does not understand a test scene thoroughly enough, a large amount of repeated tests can be caused, so that the manpower is wasted; meanwhile, the requirement on the time sequence is very strict based on the interlocking rule of Boolean logic, most faults occurring in actual field operation are generated by the special time sequence of one more period or one less period of each parameter excitation or demagnetization, and the traditional manual test analysis is difficult and painful for accurately controlling the time for accurately exciting or demagnetizing each parameter.
In the prior art, as a chinese invention patent document having a publication number of CN103885879A, a publication time of 6/25/2014, and a name of "script parsing method for an interlocking software automatic test platform system", a script parsing method for an interlocking software automatic test platform system is disclosed, which is characterized by comprising the following steps:
1) reading in a script: the input files are a universal test script template file, an interlocking table configuration file, an interlocking confirmation test table and an interlocking table;
2) and (3) compiling the script: the method comprises the steps of lexical analysis, grammar compiling and grammar tree creation;
3) and (3) script building: generating a final script for testing operation according to the syntax tree;
4) the script runs.
Compared with other technologies, the technical scheme has the advantages of reducing labor cost, improving efficiency and the like, and by using the automatic testing system, the automatic testing function can be realized aiming at the station yard operation logic of the interlocking system. However, this automatic test method is mainly based on a universal script parsing method, and is implemented by setting an application for an interlocking system in a specific project, that is, there is no technical scheme for performing an interlocking communication test on the interlocking system in a test environment according to a targeted case model, and the targeted case model, i.e., a test case file, is a designed test case file having a specified format and capable of automatically running in an interlocking rule automatic test system. A plurality of test cases can be defined in the test case file, each test case can define a plurality of operation steps, and an abstract function and an operation object (equipment name) are defined in each operation step of the case and are used for analyzing commands by the automatic test system and then sending the commands to the lower computer to execute operation. In each operation step, the variable name to be checked, the specific time of the variable condition and the process of variable jump are defined aiming at the function command. The process of variable jump can be defined as four formats of 0-0, 1-1, 0-1 and 1-0, and respectively represents that the variable is always kept at 0 and no jump occurs in a designated period after operation; the variable is always kept at 1 within a designated period after operation and no jump occurs; the variable jumps from 0 to 1 in a specified period after operation; the variable jumps from 1 to 0 in a specified period after operation, the interlocking system is automatically tested based on the test case, and the condition and the problem of the system can be mastered in a targeted manner under the condition of not influencing normal operation.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a system and a method for realizing the automatic testing of the interlocking rules based on the software function realization, easy environment construction, correct analysis of test cases, accurate tracking of case parameters and correct judgment of test results, thereby accurately positioning the design defects of the general rules.
The purpose of the invention is realized by the following technical scheme:
an interlocking rule automatic test system based on test cases comprises a test case execution module, a test station upper computer module, a simulation module, a result judgment module, a test station lower computer module and a plurality of adjacent station lower computer modules; it should be noted here that the interlocking system in the station yard generally includes an upper computer, a lower computer, a communication module (including an I/O interface with the trackside system), and a maintenance station, where the communication module is used to implement information interaction between the interlocking system and an external subsystem; the maintenance platform is used for recording the operation result and the interactive information of each period of the interlocking system and alarming the system abnormity; in the interlocking rule automatic test system, the core logic of the interlocking system is mainly tested, the logic runs in a test station and lower computer modules of adjacent stations of the test station, a maintenance platform does not participate in logic operation, and therefore the logic operation is not embodied in the automatic test system, the communication of the interlocking system is realized by a communication board card except the communication of an internal upper computer and a lower computer, and other communication is realized by a communication board card.
The simulation module is used for simulating an interface of an external subsystem for communicating with the interlocking system, and the test station upper computer module is used for simulating an upper computer of the interlocking system, serving as a man-machine interface, issuing an operation command to the test station lower computer module and carrying out interface display according to status code bits sent by the test station lower computer module; the test station lower computer module is also called an interlocking machine, is used for simulating a lower computer of an interlocking system, is used for carrying out interlocking logic operation according to a command sent by the test station upper computer module and state information sent by other external subsystems through the simulation module, and is the core of the interlocking system;
the test case execution module analyzes an upper computer command from an input test case and sends the upper computer command to the test station upper computer module, generates a code bit setting instruction for the simulation module according to the content of the test case, and sends an expected result obtained by executing the test case to the result judgment module; the test case execution module is used for reading in the test case of the input file, analyzing the operation of each step in the test case, analyzing the jump period of the key parameter after each step is executed, and executing the analyzed command, namely, the automatic test system supports real-time tracking of various parameter forms to the period for positioning various key parameters.
After receiving the upper computer command, the test station upper computer module generates an execution command for the adjacent station lower computer module and the test station lower computer module, and simultaneously monitors the execution states of the adjacent station lower computer module and the test station lower computer module;
the simulation module sets code bits of all external interfaces according to the code bit setting instruction, and the test station lower computer module performs interlocking operation on external interface information acquired from the simulation module and interface information transmitted from the adjacent station lower computer module according to the execution command; the adjacent station lower computer module and the test station lower computer module send real-time operation data results of the execution commands to the result judgment module periodically; and the result judging module compares the real-time operation data result with the expected result and judges the test result.
The test case execution module, the test station upper computer module, the simulation module, the result judgment module, the test station lower computer module and the plurality of adjacent station lower computer modules are integrated in the automatic test system, the test case execution module reads in a test case file and analyzes the test case file, the analyzed upper computer interface command code bits are sent to the lower computer through the upper computer module to be executed, the analyzed simulated external interface code bit state is sent to the simulation module, the external interface code bits are set to a specified state through the simulation module, and the lower computer module carries out interlocking operation according to the command received from the upper computer, the external interface information collected by the simulation module and the interface information transmitted from the lower computer of an adjacent station field. And the result judging module acquires the data of real-time operation in each period from the lower computer, compares the expected results defined in the case executing module and judges the test result.
Correspondingly, the invention also provides an interlocking rule automatic test method based on the test case, which comprises a data input step, a function analysis step, a case execution step and a result judgment step;
the data input step comprises the steps of reading and detecting a test case file and a data file of a tested station yard from a specified path through a test case execution module, periodically sending station yard display information to an upper computer of the test station by a lower computer of the test station and a lower computer of an adjacent station, and displaying real-time station yard information by the upper computer according to received code bits;
in the function analysis step, the test case file read in the data input step is processed through a test case execution module, all test cases in the test case file are read, the expected jump of the key parameter in each test case is obtained, and the function of the corresponding operation step in all the test cases is analyzed to obtain the operation instruction corresponding to each test case; the method comprises the following steps that a test case file comprises a plurality of test cases, each test case stores a plurality of operation commands in a function form, and the operation commands are analyzed to form operation instructions which are executed step by step on a lower computer; after a certain step of the operation instruction is executed by a lower computer of the test station, an expected code bit change is required to prove whether the execution of the operation of the step is successful and whether the operation is in accordance with the expectation, and the key parameter is the proof of the expected change after the operation is executed, so that the key parameter corresponding to each operation step in the operation instruction is periodically analyzed to obtain the excitation period of each key parameter, namely the execution period of each operation step is obtained, the execution period of each operation instruction and the test case thereof is correspondingly obtained, and the operation instruction in the corresponding test case is gradually issued to the lower computer of the test station according to the excitation period of the key parameter.
The period in the periodic analysis refers to an operation period of the interlocking system, namely, the time for the interlocking system to perform one complete operation, wherein the one complete operation comprises that the interlocking system receives the external code bit change, all received information is sent to the lower computer, the lower computer performs one complete operation according to all updated external code bits, and the lower computer outputs the result obtained by the operation to the external system; the external code bits include upper computer commands.
The operation instruction comprises a plurality of operation steps with a sequence, the test case comprises a plurality of function commands, and each function command corresponds to one operation step.
In the function analysis step, the test case execution module analyzes the functions into three categories, specifically:
in the first type, the function is an operation instruction function of an upper computer of the test station, the test case execution module directly resolves the function into operation code bit information of an interface between the upper computer and a lower computer of the test station, and then when the step corresponding to the operation instruction is executed, the upper computer module directly issues a command to the lower computer for execution;
the second type is that the function is used for setting the state of the code bit of the external interface except the upper computer interface of the test station, the external code bit transmitted to the lower computer of the tested interlocking system by the external subsystem is directly set to be in a specified state for simulating the code bit of the communication between the interlocking system and other subsystems, the interlocking system carries out logic operation according to the state of the external code bit, and in order to enhance the scene simulation of actual operation, the state of the input code bit of the external interface can be locked and unlocked, or one-key simulation communication interruption or communication recovery is carried out on the external interface; the external code bit is transmitted to the lower computer module through a simulation system (equivalent to an actual interface part and an external subsystem part) for logical operation, and the upper computer does not participate in the communication of the external code bit and only displays the state according to the state code bit sent by the lower computer.
In the third category: the function is a function for setting the system state, and the function is analyzed into an instruction for simulating the restart of the tested interlocking system, the function can simulate the restart of the interlocking system under various working conditions, and the response of the test system after the restart is on the safety side.
The operation commands of the upper computer comprise a route transaction command, a route cancel command or a general person solve command, a turnout operation command, various functional button commands and the like.
The external subsystems comprise a ZC subsystem, a CC subsystem, trackside equipment and other subsystems in adjacent stations and in interlocking relation with the station piece.
In the case executing step, the lower computer of the test station executes according to the operation instructions issued step by step in the function analyzing step, specifically, but not limited to, acquiring and responding to states of trackside scattered equipment such as emergency ESP closing, staff protection switches SPKS, partition doors PD, screen doors PDKJ, flood gates FDG, car buckling and the like by interlocking, responding to information sent by a vehicle-mounted CC and a zone controller ZC system by interlocking, responding to interlocked objects such as turnouts, approaches and the like of the upper computer/ATS operation instructions, and recording data of code bit jumping of the lower computer of the test station when executing each step of the corresponding operation instructions according to an excitation period of key parameters.
When the interlocking system based on the boolean logic performs the interlocking operation, a large number of intermediate variables are operated, and data of code bit jump is the intermediate variable which leads to the final output, that is, the data of code bit jump is the intermediate variable which leads to the final output when the interlocking system based on the boolean logic performs the interlocking operation, for example, the route is established (always end command issue LRC =1, LXS = 1), after a series of operations, it is shown that a route locking signal is open (LXJ-SBO = 1), which is not directly obtained in the middle, LRC =1, LXS =1, after the interlocking check that various conditions are satisfied, the auxiliary starting parameter LRKJ jumps (jumps from 0 to 1), the terminal parameter LZJ jumps (jumps from 0 to 1), the starting parameter LKJ jumps (jumps from 0 to 1), and further the intra-segment-side segment locking permission parameter ljlsbsjc jumps (jumps from 0 to 1), the sections allow locking, the locking parameter section-QJJ (jump from 0 to 1), the section-XLJ, the section-SLJ jump (jump from 1 to 0), and the signal open check parameter-LXJCHK jump (jump from 1 to 0), wherein the parameters LRKJ, llzj, LKJ, ljsbjc, QJJ, XLJ, SLJ, LXJCHK all count intermediate parameters, i.e., data for code bit jumps.
And in the result judging step, the code bit jumping data of each test case recorded in the case executing step is checked one by one with the expected jumping of the key parameters in the corresponding test case obtained in the function analyzing step, and if the code bit jumping data of any test case does not accord with the expected jumping, the corresponding test case is considered to be failed to be executed.
In the result judging step, after the test case is considered to be failed to execute, the subsequent operation steps are skipped and the test case is directly ended, and the executed test result and all the running information in the test case range cached in the parameter recording interface are saved in a rtf file format.
Compared with the prior art, the technical scheme comprises the following innovation points and beneficial effects (advantages):
1. the method greatly simplifies the environmental requirements for building the test system, and has a wider simulation range for scenes which may appear in the actual field. The inter-station communication of the interlocking system abandons the traditional mode that a TCP/IP protocol is adopted among a plurality of lower computers to realize analog communication, and adopts the mode of multithread communication to realize the inter-station communication in an analog mode. On one hand, communication configuration files are not needed for the simulation of inter-station communication, on the other hand, hardware limitation is broken through, multi-station communication can be achieved only by operating lower computer modules on a plurality of computers, and a plurality of stations can be simulated and operated simultaneously by directly configuring a plurality of stations on one computer, so that inter-station code bit interaction is achieved. Meanwhile, the test system of the scheme supports free communication among multiple stations, and is also provided with an interface for simulating communication interruption by one key, so that the state of the code bits of communication among the stations can be changed in a mode of directly placing the code bits sent by the adjacent station on the simulator of the station, the communication delay among the stations is simulated, and the simulation of a complex network environment on site is supported.
2. The ADS file ensures the consistency of the operation result and the actual field interlocking logic operation, and prevents the difference between the test result and the field actual operation result caused by the problem of the compiling tool to the maximum extent.
3. According to the method, the input file read by the test system in the automatic test mode is the form type test case, and the comment explanation can be added in the test case under the operation of each step, so that the use thresholds of testers and auditors are greatly reduced, and the test case is convenient to expand or check.
4. The test system in the method can automatically identify and execute each test case defined in the input file, and can check the legality of the test case before executing the test, thereby greatly reducing the manpower for confirming the test and checking the parameters. For the test case without error, the test system can analyze the function defined by each step of the test case, and check the executed result to the specific periodicity and keep the test record, thereby reducing the risk that the hidden problem can not be tested due to the fact that the specific periodicity of the control parameter excitation can not be accurately controlled in a manual test mode.
5. In the method, the test system realizes the recording of the test result in various modes in an automatic test mode, and can accurately position and indicate the tested problem and the corresponding parameter for the failed case, thereby realizing the high-efficiency problem positioning of one-time test.
6. The method relates to the matching relation between the external input code bits and the output of the interlocking system to the external interface, and the method is realized in a simulation mode of configuration files in the simulation module, so that the dependence on laboratory hardware equipment is eliminated, the specific application extension of the interlocking system aiming at different product lines is supported, and the simulation module is more flexible and convenient.
Drawings
The foregoing and following detailed description of the invention will be apparent when read in conjunction with the following drawings, in which:
FIG. 1 is a schematic diagram of the overall topology of the automatic test system of the present invention;
FIG. 2 is a schematic flow chart of the automatic test method of the present invention;
FIG. 3 is a logic process diagram of the automatic test method of the present invention.
Detailed Description
The technical solutions for achieving the objects of the present invention are further illustrated by the following specific examples, and it should be noted that the technical solutions claimed in the present invention include, but are not limited to, the following examples.
Example 1
As a specific embodiment of the interlocking rule automatic test system based on the test case, as shown in fig. 1, the interlocking rule automatic test system comprises a test case execution module, a test station upper computer module, a simulation module, a result judgment module, a test station lower computer module and a plurality of adjacent station lower computer modules; it should be noted here that the interlocking system in the station yard generally includes an upper computer, a lower computer, a communication module (including an I/O interface with the trackside system), and a maintenance station, where the communication module is used to implement information interaction between the interlocking system and an external subsystem; the maintenance platform is used for recording the operation result and the interactive information of each period of the interlocking system and alarming the system abnormity; in the interlocking rule automatic test system, the core logic of the interlocking system is mainly tested, the logic runs in a test station and lower computer modules of adjacent stations of the test station, a maintenance platform does not participate in logic operation, and therefore the logic operation is not embodied in the automatic test system, the communication of the interlocking system is realized by a communication board card except the communication of an internal upper computer and a lower computer, and other communication is realized by a communication board card.
The test case execution module analyzes an upper computer command from an input test case and sends the upper computer command to the test station upper computer module, generates a code bit setting instruction for the simulation module according to the content of the test case, and sends an expected result obtained by executing the test case to the result judgment module; the test case execution module is used for reading in the test case of the input file, analyzing the operation of each step in the test case, analyzing the jump period of the key parameter after each step is executed, and executing the analyzed command, namely, the automatic test system supports real-time tracking of various parameter forms to the period for positioning various key parameters.
And after receiving the upper computer command, the test station upper computer module generates an execution command for the adjacent station lower computer module and the test station lower computer module, and simultaneously monitors the execution states of the adjacent station lower computer module and the test station lower computer module, wherein the upper computer module is used for realizing a human-computer interface. And the upper computer module displays the station coordinates according to the station data and displays the real-time state of the current station equipment according to the interface code bits sent by the lower computer. The upper computer module can convert the upper computer command analyzed by the automatic test module into an upper computer communication code position and then sends the command to the lower computer module.
The simulation module sets code bits of all external interfaces according to the code bit setting instruction, and the test station lower computer module performs interlocking operation on external interface information acquired from the simulation module and interface information transmitted from the adjacent station lower computer module according to the execution command; the adjacent station lower computer module and the test station lower computer module send real-time operation data results of the execution commands to the result judgment module periodically; the result judging module compares a real-time operation data result with the expected result and judges a test result, namely, the simulation module realizes the simulation of the interface states of the interlocking system and the external subsystem in a software mode, the simulation module sets an independent data block according to the interface files of the interlocking system and the external subsystem, independently runs logic, and can simulate the state of input code bits sent by the external subsystem according to the operation result of the interlocking lower computer module through a configuration file.
And further, the lower computer module runs the compiled ADS file (Application Data Structure) to perform logic operation, the lower computer module runs Data of a plurality of stations, each station independently starts a thread, and interaction of code bits between adjacent stations and lower computers is realized through inter-thread communication, preferably. The main cycle of the lower computer module is modifiable, the main cycle can be modified according to actual project requirements, and the jumping cycles after time parameter delay under different main cycles are different. The ADS file is a binary file which is generated by compiling an interlocking communication interface file and an interlocking rule file and can directly run in an operation processor of a lower computer; the main operating cycle is the time for the lower computer arithmetic processor to complete the logic program once.
The result judging module is used for judging and recording the operation result of the lower computer, checking the operation result of the lower computer in each period one by one according to the parameter reference obtained by analyzing the test case executing module and the expected parameter change under the corresponding reference, judging the operation result and recording the operation result into the log file and the result judging file in detail.
In the scheme, the simulation module is used for simulating an interface of an external subsystem for communication to the interlocking system, and the test station upper computer module is used for simulating an upper computer of the interlocking system, serving as a man-machine interface, issuing an operation command to the test station lower computer module and performing interface display according to the state code bits sent by the test station lower computer module; the test station lower computer module is also called an interlocking machine, is used for simulating a lower computer of an interlocking system, is used for carrying out interlocking logic operation according to a command sent by the test station upper computer module and state information sent by other external subsystems through the simulation module, and is the core of the interlocking system; the test case execution module, the test station upper computer module, the simulation module, the result judgment module, the test station lower computer module and the plurality of adjacent station lower computer modules are integrated in the automatic test system, the test case execution module reads in a test case file and analyzes the test case file, the analyzed upper computer interface command code bits are sent to the lower computer through the upper computer module to be executed, the analyzed simulated external interface code bit state is sent to the simulation module, the external interface code bits are set to a specified state through the simulation module, and the lower computer module carries out interlocking operation according to the command received from the upper computer, the external interface information collected by the simulation module and the interface information transmitted from the lower computer of an adjacent station field. And the result judging module acquires the data of real-time operation in each period from the lower computer, compares the expected results defined in the case executing module and judges the test result.
Example 2
Corresponding to the technical solution of the automatic test system in embodiment 1, this embodiment further provides an automatic test method for interlocking rules based on test cases, as shown in fig. 2, including a data input step, a function analysis step, a case execution step, and a result determination step.
Specifically, as shown in fig. 3, in the data input step, the test case execution module reads and detects the test case file and the data file of the tested station from the specified path, that is, reads the station data file and the test case file in the specified path, the system checks the validity of the data and the test case file definition to complete station initialization, the lower computer of the test station and the lower computers of the neighboring stations periodically send station display information to the upper computer of the test station, and the upper computer displays real-time station information according to the received code bits, so as to summarize and display the test process and view the result in time.
In the function analysis step, the test case file read in the data input step is processed through a test case execution module, all test cases in the test case file are read, the expected jump of the key parameter in each test case is obtained, and the function of the corresponding operation step in all the test cases is analyzed to obtain the operation instruction corresponding to each test case; the method comprises the following steps that a test case file comprises a plurality of test cases, each test case stores a plurality of operation commands in a function form, and the operation commands are analyzed to form operation instructions which are executed step by step on a lower computer; after a lower computer of the test station executes a certain step of the operation instruction, an expected code bit change is needed to prove whether the execution of the operation of the step is successful and whether the operation is in accordance with the expectation, and the key parameter is the proof of the expected change after the operation is executed, so that the key parameter corresponding to each operation step in the operation instruction is periodically analyzed to obtain the excitation period of each key parameter, namely the execution period of each operation step is obtained, the execution period of each operation instruction and the test case thereof is correspondingly obtained, and the operation instruction in the corresponding test case is gradually issued to the lower computer of the test station according to the excitation period of the key parameter; the operation instruction comprises a plurality of operation steps with a sequence, the test case comprises a plurality of function commands, and each function command corresponds to one operation step.
Specifically, the cycle in the periodic analysis refers to an operation cycle of the interlock system, that is, a time for the interlock system to perform a complete operation, where the complete operation includes that the interlock system receives an external code bit change, sends all received information to the lower computer, the lower computer performs a complete operation according to all updated external code bits, and the lower computer outputs a result obtained by the operation to the external system; the external code bits include upper computer commands.
The operation of each step in the test case is defined as an abstract function in a pseudo code form, the test case execution module performs function analysis according to the rule defined by the constrained function, the analyzed function can be directly converted into an instruction of an upper computer and issued to a lower computer module through the upper computer for operation execution or converted into external interface code bit information, the external interface code bit is set to be in a designated state through a simulation module, and after each step of operation execution, the key parameter needing to be monitored in the step needs to be periodically analyzed. In order to accurately grasp the excitation time of each parameter
More preferably, in the function parsing step, the test case execution module parses the function into three categories:
in the first type, the function is an operation instruction function of an upper computer of the test station, the test case execution module directly resolves the function into operation code bit information of an interface between the upper computer and a lower computer of the test station, and then when the step corresponding to the operation instruction is executed, the upper computer module directly issues a command to the lower computer for execution; the operation commands of the upper computer comprise a route transaction command, a route cancel command or a general person solve command, a turnout operation command, various functional button commands and the like.
The second type is that the function is used for setting the state of the code bit of the external interface except the upper computer interface of the test station, the external code bit transmitted to the lower computer of the tested interlocking system by the external subsystem is directly set to be in a specified state and used for simulating the code bit of the communication between the interlocking system and other subsystems, the interlocking system carries out logic operation according to the state of the external code bit, and the external subsystem comprises a ZC subsystem, a CC subsystem, trackside equipment and other subsystems in adjacent stations and in interlocking relation with the station field; in order to enhance the scene simulation of actual operation, the state of the code bit input by the external interface can be locked and unlocked, or one-key simulation communication interruption or communication recovery is performed on the external interface; the external code bit is transmitted to the lower computer module through a simulation system (equivalent to an actual interface part and an external subsystem part) for logical operation, and the upper computer does not participate in the communication of the external code bit and only displays the state according to the state code bit sent by the lower computer.
In the third category: the function is a function for setting the system state, and the function is analyzed into an instruction for simulating the restart of the tested interlocking system, the function can simulate the restart of the interlocking system under various working conditions, and the response of the test system after the restart is on the safety side.
Analyzing and tracking key parameters of operation steps, after each step of operation is performed, a jump level (changed from 0 to 1 or from 1 to 0) of a parameter designated state is used as a reference for subsequent parameter tracking; when the parameter is subjected to expected jump in a plurality of cycles of executing operation, timing other key parameters by using the current cycle of the reference parameter state meeting the expected state change, and taking jump cycles of other key parameters as calculation references, thereby realizing accurate test card control. In the case execution step, in order to ensure the flexibility of key parameter tracking, the tracking reference may be changed, and after the tracking reference is changed, all the key parameters after the new reference parameter start tracking with the expected transition period of the new reference parameter as the tracking origin. Specifically, the time parameter in the operation logic is delayed at the beginning of the jump period of the reference parameter, and jump occurs after the delay for a specified time. For the time parameter, the test case execution module firstly converts the time value of the Delay into a specified period (T _ Delay/T _ CYCLE) according to a specific time value (T _ Delay) and a main period (T _ CYCLE) of the current system operation, namely, all the parameters with the periodic change and the parameters with the time change are converted into one dimension to perform real-time code bit monitoring. For a test case, the situation that after a certain operation, a certain key variable cannot jump any more in a plurality of cycles is also involved. For this type of critical parameter tracking, a cycle number (T _ WAIT) may be given in which the parameter remains in a pre-existing state (0-0 or 1-1) at all times. The test case execution module analyzes the instruction and the tracking parameter in the test case through the logic analysis mode. All critical parameters to be tracked can be resolved to the excitation/de-excitation timing accurate to the number of cycles.
In the case executing step, the lower computer of the test station executes according to the operation instructions issued step by step in the function analyzing step, specifically, but not limited to, acquiring and responding to states of trackside scattered equipment such as emergency ESP closing, staff protection switches SPKS, partition doors PD, screen doors PDKJ, flood gates FDG, car buckling and the like by interlocking, responding to information sent by a vehicle-mounted CC and a zone controller ZC system by interlocking, responding to interlocked objects such as turnouts, approaches and the like of the upper computer/ATS operation instructions, and recording data of code bit jumping of the lower computer of the test station when executing each step of the corresponding operation instructions according to an excitation period of key parameters. When the interlocking system based on the boolean logic performs the interlocking operation, a large number of intermediate variables are operated, and data of code bit jump is the intermediate variable which leads to the final output, that is, the data of code bit jump is the intermediate variable which leads to the final output when the interlocking system based on the boolean logic performs the interlocking operation, for example, the route is established (always end command issue LRC =1, LXS = 1), after a series of operations, it is shown that a route locking signal is open (LXJ-SBO = 1), which is not directly obtained in the middle, LRC =1, LXS =1, after the interlocking check that various conditions are satisfied, the auxiliary starting parameter LRKJ jumps (jumps from 0 to 1), the terminal parameter LZJ jumps (jumps from 0 to 1), the starting parameter LKJ jumps (jumps from 0 to 1), and further the intra-segment-side segment locking permission parameter ljlsbsjc jumps (jumps from 0 to 1), the sections allow locking, the locking parameter section-QJJ (jump from 0 to 1), the section-XLJ, the section-SLJ jump (jump from 1 to 0), and the signal open check parameter-LXJCHK jump (jump from 1 to 0), wherein the parameters LRKJ, llzj, LKJ, ljsbjc, QJJ, XLJ, SLJ, LXJCHK all count intermediate parameters, i.e., data for code bit jumps.
And the result judging step is to check the code bit jumping data of each test case recorded in the case executing step one by one with the expected jumping of the key parameters in the corresponding test case obtained in the function analyzing step, and if the code bit jumping data of any test case is not in accordance with the expected jumping, the corresponding test case is considered to be failed to execute.
To facilitate understanding, a more specific example is given here for illustration:
the above table is a command schematic of a specific test case, where X05B is the name of an entry end signal, X09B is the name of an entry end signal, and G09B, G11B, and G13B are the names of the entry inside segments; the system comprises an X05B-LRC parameter, an X09B-LXS parameter and an X05B-LRKJ parameter, wherein the X05 3583-LRC parameter and the X09B-LXS parameter are respectively route establishment request commands which are issued by an upper computer and take X05B as a route starting end and X09B as a route terminal, and the X05B-LRKJ parameter is an auxiliary relay starting parameter (for route auxiliary establishment) for route establishment of an X05B starting end signal machine; G09B-SJ, G11B-SJ and G13B-SJ respectively represent the locking parameters of the sections in the route; G09B-STDJ, G11B-STDJ and G13B-STDJ respectively represent the direction locking parameters of the section in the route; X05B-LXJ-SBO is a signal opening parameter output to the outdoor signal equipment X05B.
The ROUTE command refers to handling a train ROUTE, handling the train ROUTE with an X05B signal machine as a starting end and an X09B signal machine as a terminal, analyzing the command, and analyzing the ROUTE command into upper computer interface application code bit ROUTE end-to-end commands X05B-LRC and X09B-LXS, namely when the step of the use case is executed, sending the end-to-end commands X05B-LRC and X09B-LXS to a lower computer.
Analyzing a specific period of parameter tracking when the tested interlocking system transacts an access to the upper computer, namely an X05B-LRC parameter, an X09B-LXS parameter and an X05B-LRKJ parameter; the upper computer sends a jump of 0-1 in a cycle of a starting end command X05B-LRC =1 (hereinafter referred to as the cycle); the block locking parameters G09B-SJ, G11B-SJ and G13B-SJ jump by 1-0 in the period; jumping of 0-1 occurs in the next period by the direction parameters G09B-STDJ, G11B-STDJ and G13B-STDJ of the section in the route; the X05B-LXJ-SBO parameter transformation tracking reference is G09B-STDJ parameters, tracking is started when the G09B-STDJ parameters jump to 1, and jump of 0-1 occurs to the X05B-LXJ-SBO parameters after T _ QD second delay.
Tracking of excitation time of key parameters needs to be controlled by a unified CYCLE number, for example, T _ QD =1s, and a main operation CYCLE T _ CYCLE of a lower computer is 250ms, then X05B-LXJ-SBO parameters jump 0-1 after 4 CYCLEs (T _ QD/T _ CYCLE = 4) of G09B-STDJ =1, where the time value T _ QD represents delay time of system output, and T _ CYCLE represents the main operation CYCLE of the lower computer.
And (4) checking the recorded key parameter jump data with the expected jump of the example, and completing the test to obtain a test result.
Claims (10)
1. The utility model provides an interlock rule automatic test system based on test case which characterized in that: the system comprises a test case execution module, a test station upper computer module, a simulation module, a result judgment module, a test station lower computer module and a plurality of adjacent station lower computer modules;
the test case execution module analyzes an upper computer command from an input test case and sends the upper computer command to the test station upper computer module, generates a code bit setting instruction for the simulation module according to the content of the test case, and sends an expected result obtained by executing the test case to the result judgment module;
after receiving the upper computer command, the test station upper computer module generates an execution command for the adjacent station lower computer module and the test station lower computer module, and simultaneously monitors the execution states of the adjacent station lower computer module and the test station lower computer module;
the simulation module sets code bits of all external interfaces according to the code bit setting instruction, and the test station lower computer module performs interlocking operation on external interface information acquired from the simulation module and interface information transmitted from the adjacent station lower computer module according to the execution command; the adjacent station lower computer module and the test station lower computer module send real-time operation data results of the execution commands to the result judgment module periodically; and the result judging module compares the real-time operation data result with the expected result and judges the test result.
2. The automatic test system for interlocking rules based on test cases according to claim 1, characterized in that: the simulation module is used for simulating an interface of an external subsystem for communicating with the interlocking system, and the test station upper computer module is used for simulating an upper computer of the interlocking system, serving as a man-machine interface, issuing an operation command to the test station lower computer module and carrying out interface display according to status code bits sent by the test station lower computer module; the test station lower computer module is used for simulating a lower computer of the interlocking system and carrying out interlocking logic operation according to a command sent by the test station upper computer module and state information sent by other external subsystems through the simulation module.
3. An interlocking rule automatic test method based on test cases is characterized in that: the method comprises a data input step, a function analysis step, a use case execution step and a result judgment step;
the data input step comprises the steps of reading and detecting a test case file and a data file of a tested station yard from a specified path through a test case execution module, periodically sending station yard display information to an upper computer of the test station by a lower computer of the test station and a lower computer of an adjacent station, and displaying real-time station yard information by the upper computer according to received code bits;
in the function analysis step, the test case file read in the data input step is processed through a test case execution module, all test cases in the test case file are read, the expected jump of the key parameter in each test case is obtained, and the function of the corresponding operation step in all the test cases is analyzed to obtain the operation instruction corresponding to each test case; periodically analyzing the key parameters corresponding to each operation step in the operation instruction to obtain the excitation period of each key parameter, and gradually issuing the operation instruction in the corresponding test case to a lower computer of the test station according to the excitation period of the key parameters;
in the case executing step, the lower computer of the test station executes according to the operation instructions issued step by step in the function analyzing step, and records the code bit jumping data of the lower computer of the test station when executing each step of the corresponding operation instructions according to the excitation period of the key parameter;
and in the result judging step, the code bit jumping data of each test case recorded in the case executing step is checked one by one with the expected jumping of the key parameters in the corresponding test case obtained in the function analyzing step, and if the code bit jumping data of any test case does not accord with the expected jumping, the corresponding test case is considered to be failed to be executed.
4. The method for automatically testing the interlocking rule based on the test case as claimed in claim 3, wherein: in the function analysis step, the cycle in the periodic analysis refers to the operation cycle of the interlocking system, namely the time for the interlocking system to perform one complete operation, wherein the one complete operation comprises that the interlocking system receives the external code bit change, all received information is sent to a lower computer, the lower computer performs one complete operation according to all updated external code bits, and the lower computer outputs the result obtained by the operation to the external system; the external code bits include upper computer commands.
5. The method for automatically testing the interlocking rule based on the test case as claimed in claim 3 or 4, wherein: in the function analysis step, the operation instruction comprises a plurality of operation steps with a sequence, the test case comprises a plurality of function commands, and each function command corresponds to one operation step.
6. The method according to claim 3, wherein in the step of analyzing the function, the test case execution module analyzes the function into three categories, specifically:
in the first type, the function is an operation instruction function of an upper computer of the test station, the test case execution module directly resolves the function into operation code bit information of an interface between the upper computer and a lower computer of the test station, and then when the step corresponding to the operation instruction is executed, the upper computer module directly issues a command to the lower computer for execution;
and the second type is that the function is used for setting the state of the code bit of the external interface except the upper computer interface of the test station, and the external code bit which is transmitted to the lower computer of the tested interlocking system by an external subsystem is directly set to be in a specified state for simulating the code bit of the communication between the interlocking system and other subsystems, and the interlocking system carries out logic operation according to the state of the external code bit.
In the third category: and if the function is a function for setting the system state, resolving the function into an instruction for simulating the restart of the tested interlocking system.
7. The method for automatically testing the interlocking rule based on the test case as claimed in claim 6, wherein: the operation commands of the upper computer comprise a route transaction command, a route cancel command or a general solution command, a turnout operation command and various functional button commands.
8. The method for automatically testing the interlocking rule based on the test case according to the claim 6 or 7, characterized in that: the external subsystems comprise a ZC subsystem, a CC subsystem, trackside equipment and other subsystems in adjacent stations and in interlocking relation with the station piece.
9. The method for automatically testing the interlocking rule based on the test case as claimed in claim 3, wherein: in the use case executing step, the code bit jumping data is an intermediate variable which is finally output when the interlocking operation is carried out by an interlocking system based on Boolean logic.
10. The method for automatically testing the interlocking rule based on the test case as claimed in claim 3, wherein: in the result judging step, after the test case is considered to be failed to execute, the subsequent operation steps are skipped and the test case is directly ended, and the executed test result and all the running information in the test case range cached in the parameter recording interface are saved in a rtf file format.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110511344.9A CN113268415B (en) | 2021-05-11 | 2021-05-11 | Automatic interlocking rule testing system and method based on test cases |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110511344.9A CN113268415B (en) | 2021-05-11 | 2021-05-11 | Automatic interlocking rule testing system and method based on test cases |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113268415A true CN113268415A (en) | 2021-08-17 |
| CN113268415B CN113268415B (en) | 2024-06-28 |
Family
ID=77230397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110511344.9A Active CN113268415B (en) | 2021-05-11 | 2021-05-11 | Automatic interlocking rule testing system and method based on test cases |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113268415B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113501034A (en) * | 2021-09-09 | 2021-10-15 | 卡斯柯信号(北京)有限公司 | Test log generation method and device for railway signal system |
| CN113771919A (en) * | 2021-11-12 | 2021-12-10 | 卡斯柯信号(北京)有限公司 | Urban rail project interlocking dual-computer test method based on interlocking simulation system |
| CN115649238A (en) * | 2022-10-31 | 2023-01-31 | 北京瑞威信通科技有限公司 | Interlocking logic operation monitoring software for computer interlocking system |
| CN118618455A (en) * | 2024-08-14 | 2024-09-10 | 卡斯柯信号(北京)有限公司 | Method and device for acquiring control logic in trackside signal control system |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103885439A (en) * | 2014-03-21 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Automated testing system for railway signal computer interlocking system |
| CN103885879A (en) * | 2014-03-26 | 2014-06-25 | 卡斯柯信号有限公司 | Script parsing method used for automatic interlocking-software testing platform system |
| KR101414720B1 (en) * | 2013-05-31 | 2014-07-04 | 한국철도기술연구원 | Functional safety testing device for train control system software and the method thereof |
| CN104516818A (en) * | 2014-12-29 | 2015-04-15 | 北京四方继保自动化股份有限公司 | Automatic testing system and method both applicable to compiler in logical configuration software |
| WO2016137035A1 (en) * | 2015-02-25 | 2016-09-01 | 슈어소프트테크주식회사 | Test case generation device and method, and computer-readable recording medium for recording program for executing same |
| CN107451064A (en) * | 2017-08-16 | 2017-12-08 | 北京车和家信息技术有限责任公司 | Automatic test approach, device, computer equipment and readable storage medium storing program for executing |
| CN107562625A (en) * | 2017-08-30 | 2018-01-09 | 安徽天达网络科技有限公司 | One kind is used for automatic Test Simulation System of Computer Interlocking Software and its method |
| CN107992020A (en) * | 2017-11-08 | 2018-05-04 | 交控科技股份有限公司 | A kind of interlocking Auto-Test System and method based on big data |
| CN110798372A (en) * | 2019-01-28 | 2020-02-14 | 通号城市轨道交通技术有限公司 | Data testing method and device |
| CN112131094A (en) * | 2019-06-25 | 2020-12-25 | 比亚迪汽车工业有限公司 | Method and device for testing track signal system software and storage medium |
| CN112164272A (en) * | 2020-11-06 | 2021-01-01 | 卡斯柯信号(成都)有限公司 | Signal simulation system and simulation method of tramcar signal system |
| CN112198815A (en) * | 2020-12-04 | 2021-01-08 | 卡斯柯信号(北京)有限公司 | Interlocking function simulation automatic test method and system |
| WO2021027852A1 (en) * | 2019-08-14 | 2021-02-18 | 比亚迪股份有限公司 | Train signal system and linkage method therefor |
| CN112416715A (en) * | 2020-11-25 | 2021-02-26 | 卡斯柯信号有限公司 | Computer interlocking performance test system based on operation scene |
| CN112527683A (en) * | 2020-12-24 | 2021-03-19 | 卡斯柯信号有限公司 | Automatic interface test system for computer interlocking system and application |
| CN112765020A (en) * | 2021-01-15 | 2021-05-07 | 通号万全信号设备有限公司 | Automatic testing method of computer interlocking system |
-
2021
- 2021-05-11 CN CN202110511344.9A patent/CN113268415B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101414720B1 (en) * | 2013-05-31 | 2014-07-04 | 한국철도기술연구원 | Functional safety testing device for train control system software and the method thereof |
| CN103885439A (en) * | 2014-03-21 | 2014-06-25 | 上海富欣智能交通控制有限公司 | Automated testing system for railway signal computer interlocking system |
| CN103885879A (en) * | 2014-03-26 | 2014-06-25 | 卡斯柯信号有限公司 | Script parsing method used for automatic interlocking-software testing platform system |
| CN104516818A (en) * | 2014-12-29 | 2015-04-15 | 北京四方继保自动化股份有限公司 | Automatic testing system and method both applicable to compiler in logical configuration software |
| WO2016137035A1 (en) * | 2015-02-25 | 2016-09-01 | 슈어소프트테크주식회사 | Test case generation device and method, and computer-readable recording medium for recording program for executing same |
| CN107451064A (en) * | 2017-08-16 | 2017-12-08 | 北京车和家信息技术有限责任公司 | Automatic test approach, device, computer equipment and readable storage medium storing program for executing |
| CN107562625A (en) * | 2017-08-30 | 2018-01-09 | 安徽天达网络科技有限公司 | One kind is used for automatic Test Simulation System of Computer Interlocking Software and its method |
| CN107992020A (en) * | 2017-11-08 | 2018-05-04 | 交控科技股份有限公司 | A kind of interlocking Auto-Test System and method based on big data |
| CN110798372A (en) * | 2019-01-28 | 2020-02-14 | 通号城市轨道交通技术有限公司 | Data testing method and device |
| CN112131094A (en) * | 2019-06-25 | 2020-12-25 | 比亚迪汽车工业有限公司 | Method and device for testing track signal system software and storage medium |
| WO2021027852A1 (en) * | 2019-08-14 | 2021-02-18 | 比亚迪股份有限公司 | Train signal system and linkage method therefor |
| CN112164272A (en) * | 2020-11-06 | 2021-01-01 | 卡斯柯信号(成都)有限公司 | Signal simulation system and simulation method of tramcar signal system |
| CN112416715A (en) * | 2020-11-25 | 2021-02-26 | 卡斯柯信号有限公司 | Computer interlocking performance test system based on operation scene |
| CN112198815A (en) * | 2020-12-04 | 2021-01-08 | 卡斯柯信号(北京)有限公司 | Interlocking function simulation automatic test method and system |
| CN112527683A (en) * | 2020-12-24 | 2021-03-19 | 卡斯柯信号有限公司 | Automatic interface test system for computer interlocking system and application |
| CN112765020A (en) * | 2021-01-15 | 2021-05-07 | 通号万全信号设备有限公司 | Automatic testing method of computer interlocking system |
Non-Patent Citations (1)
| Title |
|---|
| 延旭: "计算机联锁软件仿真测试方法研究", 中国优秀硕士电子期刊网, no. 01, 15 January 2020 (2020-01-15), pages 138 - 2289 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113501034A (en) * | 2021-09-09 | 2021-10-15 | 卡斯柯信号(北京)有限公司 | Test log generation method and device for railway signal system |
| CN113501034B (en) * | 2021-09-09 | 2021-12-24 | 卡斯柯信号(北京)有限公司 | Test log generation method and device for railway signal system |
| CN113771919A (en) * | 2021-11-12 | 2021-12-10 | 卡斯柯信号(北京)有限公司 | Urban rail project interlocking dual-computer test method based on interlocking simulation system |
| CN115649238A (en) * | 2022-10-31 | 2023-01-31 | 北京瑞威信通科技有限公司 | Interlocking logic operation monitoring software for computer interlocking system |
| CN118618455A (en) * | 2024-08-14 | 2024-09-10 | 卡斯柯信号(北京)有限公司 | Method and device for acquiring control logic in trackside signal control system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113268415B (en) | 2024-06-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113268415B (en) | Automatic interlocking rule testing system and method based on test cases | |
| CN106802862B (en) | Automatic test platform for safety key software of train operation control system | |
| Bernardeschi et al. | A formal verification environment for railway signaling system design | |
| CN112000557B (en) | Automatic testing device for rail transit signal system | |
| US20170236234A1 (en) | Risk management method and system for a land transporation system | |
| Damm et al. | Verification of a radio-based signaling system using the STATEMATE verification environment | |
| CN109857087A (en) | A kind of urban rail zone controller system hardware is in ring test system | |
| CN112722016B (en) | Automatic test system and method for rail transit train automatic control system | |
| Wu et al. | Scenario-based modeling of the on-board of a satellite-based train control system with colored petri nets | |
| Tsuji et al. | Prioritizing scenarios based on STAMP/STPA using statistical model checking | |
| Iliasov et al. | Practical verification of railway signalling programs | |
| Cichocki et al. | Formal support for fault modelling and analysis | |
| Kadakolmath et al. | A survey on formal specification and Verification of smart mass transit railway interlocking system | |
| Morley | Safety assurance in interlocking design | |
| CN115892146A (en) | Automatic test method for interactive code bits of interlocking system and external system interface | |
| Kumar et al. | Model based TTCN-3 testing of industrial automation systems—First results | |
| Zheng et al. | Generating test cases from requirements: A case study in railway control system domain | |
| CN212433629U (en) | Automatic test system of railway system | |
| CN112306039B (en) | Debugging method and system for full-electronic interlocking system | |
| Bonfiglio et al. | Composable Framework Support for Software-FMEA through Model Execution | |
| Sanseviero et al. | UML based reverse engineering for the verification of railway control logics | |
| Calame et al. | TTCN-3 testing of hoorn-kersenboogerd railway interlocking | |
| Wang et al. | Test suite generation for ctcs-3 train control system based on taio and mutation theory | |
| Gao et al. | An Edge Computing-Based Paltform of Railway Signalling System On-site Digital Smart Test | |
| Arabestani et al. | Precise definition of the single-track level crossing in radio-based operation in UML notation and specification of safety requirements |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |