CN113259088B - Reconfigurable data path oriented to stream cipher algorithm - Google Patents
Reconfigurable data path oriented to stream cipher algorithm Download PDFInfo
- Publication number
- CN113259088B CN113259088B CN202110542855.7A CN202110542855A CN113259088B CN 113259088 B CN113259088 B CN 113259088B CN 202110542855 A CN202110542855 A CN 202110542855A CN 113259088 B CN113259088 B CN 113259088B
- Authority
- CN
- China
- Prior art keywords
- reconfigurable
- data
- array
- bit
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/177—Initialisation or configuration control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a reconfigurable data path oriented to a stream cipher algorithm, which relates to the field of hardware information security and comprises a reconfigurable feedback shift register array, a tap extraction network, a reconfigurable operation unit array, feedback data selection, key stream data selection, a data storage module and configuration information. The reconfigurable feedback shift register array realizes cascade connection of different modes among registers and shift with different directions and different granularities; the tap extraction network realizes the extraction of taps at different positions; the reconfigurable operation unit array processes the data stream; selecting feedback data; selecting key stream data; the data storage module stores data in the execution process of the stream cipher algorithm, including initial data, intermediate result data and key stream; configuration information configuration management and task mapping scheduling. The invention can meet the requirement of one information security solution on the processing of various stream cipher algorithm data streams under the condition of ensuring certain processing speed.
Description
Technical Field
The invention relates to the field of hardware information security, in particular to a reconfigurable data path oriented to a stream cipher algorithm.
Background
With the rapid development and wide application of communications and networks, massive confidential information is transmitted every day, a cryptographic algorithm is a necessary condition for ensuring confidentiality and integrity of information, especially, the application environment of a stream cryptographic algorithm is more and more wide, stream cryptographic is generally used for protecting communication data in secure network communications, especially in the fields of military, government departments and the like, like an A5/1 algorithm of a GSM system, SNOW3G and ZUC algorithms used for mobile communications in 3GPP standards, RC4 algorithms adopted by standard protocols of security mechanisms WEP, SSL/TLS and the like specified in IEEE802.11, E0 algorithms used for Bluetooth encryption systems, and currently very wide Chacha20 algorithms used, a Chacha20 algorithm and a Poly message authentication code of Bernstein are replaced with RC4 in TLS, a Chacha20-Poly1305AEAD cryptographic suite is already standardized in the 1.3, and Cha20 is also used for FreeBSD, openBSD, netBSD, linux kernels and other various operation systems. Various stream cipher algorithms may be used in a security protocol or application to ensure confidentiality and integrity of information, so flexibility in implementation of the stream cipher algorithm is an important indicator.
The traditional implementation mode of the stream cipher algorithm generally comprises a general processor and an application specific integrated circuit, and the general processor is utilized to realize high flexibility, but has low speed and low energy efficiency; the use of application specific integrated circuits allows for low power consumption but low flexibility. The reconfigurable computing cipher processor is an implementation mode of a stream cipher algorithm which can solve the problems of low energy efficiency of a general processor and insufficient flexibility of an application specific integrated circuit, and the reconfigurable data path is a core of the reconfigurable computing cipher processor.
Disclosure of Invention
The invention designs a reconfigurable data path oriented to a stream cipher algorithm, thereby ensuring the data path processing realized by a plurality of stream cipher algorithms and generating a key stream. From the perspective of application and protocol, the reconfigurable data path facing the stream cipher algorithm can meet the requirement of one information security solution for processing the data streams of a plurality of stream cipher algorithms under the condition of ensuring a certain processing speed.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
the invention provides a reconfigurable data path for a stream cipher algorithm, which comprises a reconfigurable feedback shift register array, a tap extraction network, a reconfigurable operation unit array, feedback data selection, key stream data selection, a data storage module and configuration information.
Further, the reconfigurable feedback shift register array is used for realizing cascade connection of different modes among registers and shifting of different directions and different granularities; the tap extraction network is used for extracting taps at any different positions in the reconfigurable feedback shift register array; the reconfigurable operation unit array is used for processing the stream cipher operation data stream; the feedback data selection is used for selecting data to be fed back from the output end of the reconfigurable operation unit array; the key stream data selection is used for selecting key stream data from the output end of the reconfigurable operation unit array; the data storage module is used for storing data to be operated, intermediate result data generated by the reconfigurable operation unit array and key stream data generated by a stream cipher algorithm, which are read from the outside; the configuration information is used for configuration management and task mapping scheduling.
Further, the reconfigurable feedback shift register array comprises 16 64-bit shift register arrays, each 64-bit shift register array comprises 64 1-bit registers, each 1-bit register selects a data input source through a 4-to-1 multiplexer, the input sources can come from feedback input, other stages of registers, an upper stage of registers and an initialization data end, the whole reconfigurable feedback shift register array comprises 1024 1-bit registers and 1024 4-to-1 multiplexers, cascade connection of different modes among the registers and shift with different directions and different granularity are realized mainly according to configuration information, when the reconfigurable feedback shift register array is used as a 1-bit chain, each row of the reconfigurable feedback shift register array is transversely connected, the output of each register with the number 63 is connected to the input end of a register with the number 0 of the next 64-bit shift register array, when the shift register is used as an 8-bit chain, 8bit operation granularity shift registers are formed by 8 1bit registers in the transverse direction, each 64bit shift register array comprises 8bit shift registers, shifting of the 8bit registers is realized by adopting a longitudinal shifting direction, the output of each register with the number of 56-63 is connected to the input end of a register with the number of 0-7 of the next 64bit shift register array, when the shift register is used as a 16bit chain, 16 1bit registers in each two rows form a 16bit operation granularity shift register, each 64bit shift register array comprises 4 16bit shift registers, shifting of the 16bit registers is realized by adopting a longitudinal shifting direction, the output of each register with the number of 56-63 is connected to the input end of a register with the number of 0-7 of the next 64bit shift register array, when the shift register is used as a 32bit chain, the 32 1bit registers in every four rows form a shift register with 32bit operation granularity, each 64bit shift register array comprises 2 32bit shift registers, the shift of the 32bit registers is realized by adopting a longitudinal shift direction, the output of each register with the number of 56-63 is connected to the input end of the register with the number of 0-7 of the next 64bit shift register array, and the 16 64bit shift register arrays can be cut into a plurality of chains in integer multiples of 64 bits according to requirements.
Further, the tap extraction network comprises 4 multiplexers of 128 selection 1, 1 multiplexer of 32 selection 1, 2 multiplexers of 4 selection 1, 1 multiplexer of 2 selection 1, four splicing modules, when the tap extraction network extracts, each 64bit shift register array in the reconfigurable feedback shift register array is divided into 8 groups by taking 8 bits as a group, so the whole reconfigurable feedback shift register array is divided into 16 x 8, namely 128 8 bits, extraction is carried out by taking 8 bits of groups as the minimum unit, each channel is extracted by utilizing the multiplexer of 128 selection 1, 48 bits are spliced into 32 bits by utilizing the splicing module, then the 32 bits are output according to the operation granularity of a specific stream cipher algorithm, if the operation granularity is 1bit, the 32 bits are extracted by utilizing the multiplexer of 32 selection 1, then the 32 bits are extracted by utilizing the high granularity of the multiplexer of the 32 selection 1bit, then the 4 bits are extracted by utilizing the high granularity of the 4 bits of the multiplexer of the 32 selection 1, and the 4 bits are extracted by utilizing the high granularity of the 4 bits of the 3 bit, if the 4 bits are extracted by utilizing the high granularity of the 4 bits of the 3 bit, and the 4 bits are extracted by utilizing the high-granularity of the 4bit of the 32 extraction module, and the 4 bits are extracted by the high-granularity of the 32bit of the 32, if the 4 bits are extracted by the high-granularity of the 4bit of the 32, the 3 is extracted by the 4bit, and the 4bit is directly extracted by the high-granularity of the 3, and the 4bit of the 3 bit of the 32bit of the 3, and the 3 bit is extracted by the 3, and the high-granularity of the 4bit is extracted.
Further, the reconfigurable operation unit array is composed of 12 rows and 4 columns of reconfigurable operation units (PEs), 3 heterogeneous lookup table units (LUTs) and an interconnection network between the rows of the reconfigurable operation units (PEs), each reconfigurable operation unit (PE) comprises a Logic Operation Unit (LOU), an arithmetic operation unit (AU) and 3 different functional units of a Shift Unit (SU), each 4 rows of reconfigurable operation units (PEs) are used as a group to share one heterogeneous lookup table unit (LUT), logic operation, arithmetic operation, shift operation and S-box operation in a stream cipher algorithm can be realized, each reconfigurable operation unit (PE) has 4 32bit inputs in0, in1, in2, in3 and 1 32bit outputs out, a 32bit register Reg is arranged at the output end of each reconfigurable operation unit (PE) for caching calculation results, data extracted by the tap extraction network is sent to the reconfigurable operation unit array, the function of the reconfigurable operation unit array is configured with configuration information, the reconfigurable operation unit array can be sequentially executed, and the reconfigurable operation unit array can be driven to execute the same as a feedback key array after the input of the data is set up by the dedicated operation unit array, or the dedicated operation array can be executed as a feedback key array.
Further, the feedback data selection includes 1 multiplexer of 48-1 for selecting the data to be fed back from the output terminals of 48 reconfigurable operation units (PEs) of the reconfigurable operation unit array, and feeding back the data to the reconfigurable feedback shift register array to continue to participate in the subsequent operation.
Further, the key stream data selection includes 1-48-1 multiplexer for selecting the generated key stream data from the outputs of 48 reconfigurable operation units (PEs) of the reconfigurable operation unit array.
The data storage module further comprises an input data storage, an internal data cache and a key stream storage, wherein the input data storage is used for storing various data in a stream cipher algorithm, specifically, the input data storage is used for storing data which is read from the outside and is to participate in operation, the internal data cache is used for storing intermediate result data generated by the reconfigurable operation unit array, and the key stream storage is used for storing key stream data and outputting the key stream data to the outside.
Further, the configuration information comprises configuration information for the reconfigurable feedback shift register array, configuration information for the tap extraction network and configuration information for the reconfigurable operation unit array, and is mainly responsible for configuration management and task mapping scheduling, and the configuration information is respectively sent to the reconfigurable feedback shift register array, the tap extraction network and the reconfigurable operation unit array, so that the configuration of different cascade modes and different directions and different granularity shifts of the reconfigurable feedback shift register array, the configuration of tap extraction at different positions of the tap extraction network and the switching configuration of different functions of the reconfigurable operation unit in the reconfigurable operation unit array are realized.
Compared with the prior art, the invention has the beneficial effects that: the method can ensure that more kinds of stream cipher algorithms process the data streams of the stream cipher algorithm on the reconfigurable data path facing the stream cipher algorithm, and improves the implementation flexibility of the stream cipher algorithm. From the perspective of protocols or applications requiring multiple stream cipher algorithms, the requirements of one information security solution on the multiple stream cipher algorithms can be met under the condition of ensuring a certain processing speed.
Drawings
FIG. 1 is a block diagram of a reconfigurable data path for a stream cipher algorithm according to the present invention.
Fig. 2 is a block diagram of a reconfigurable feedback shift register array according to the present invention.
Fig. 3 is a diagram of a tap extraction network according to the present invention.
Fig. 4 is a block diagram of a reconfigurable operation unit array according to the present invention.
Reference numerals illustrate: reg denotes a register, numbers 1, 2, 3, …, 64 denote a 1-bit register, respectively, 1-64 are connected by arrows to integrally denote a 64-bit shift register array, FSR1, FSR2, FSR3, …, FSR16 denote a 64-bit shift register array, respectively, MUX (128-1) denotes a 128-1 multiplexer, MUX (32-1) denotes a 32-1 multiplexer, MUX (4-1) denotes a 4-1 multiplexer, MUX (2-1) denotes a 2-1 multiplexer, PE1, PE2, PE3, …, PE48 denote a reconfigurable operation unit, LUT denote heterogeneous lookup table units, LOU denote a logic operation unit, AU denote an arithmetic operation unit, and SU denote a shift unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. These embodiments are merely for explaining the technical principle of the invention, and are not intended to limit the scope of the invention.
Please refer to fig. 1: referring to fig. 1, the present invention provides a reconfigurable data path for a stream cipher algorithm, which includes a reconfigurable feedback shift register array, a tap extraction network, a reconfigurable operation unit array, feedback data selection, key stream data selection, an input data memory, an internal data cache, a key stream memory, and configuration information. The data to be involved in the operation is transmitted to an input data memory for storage, in the process of executing a reconfigurable data path, a reconfigurable feedback shift register reads the data from the input data memory according to configuration information, a tap extraction network extracts the data from the reconfigurable feedback shift register according to the configuration information, the extracted data is transmitted to a reconfigurable operation unit array for operation, the reconfigurable operation unit array acquires the configuration information and then is driven by a data stream for execution, if the data needs to be fed back, the data to be fed back is selected from the output end of the reconfigurable operation unit array through feedback data selection, the feedback is fed back to the reconfigurable feedback shift register array to continue to participate in subsequent operation, after the operation is finished, the key stream data is selected from the output end of the reconfigurable operation unit array through key stream data selection, and the key stream data is stored in the key stream memory, and the data is output to the outside.
Please refer to fig. 2: as shown in fig. 2, the reconfigurable feedback shift register array of the present invention includes 16 shift register arrays of 64 bits, input data of each register numbered 1, 2, 3, …, 64 is selected from other registers, previous stage registers, feedback input, and input data memories through a multiplexer MUX of 1-by-4, the reconfigurable feedback shift register array realizes cascade connection of different modes and shift of different directions and different granularities among shift registers mainly according to configuration information, supports 4 operation granularities of 1bit, 8bit, 16bit, 32bit, and when used as a 1bit chain, each row of the reconfigurable feedback shift register array is laterally connected, and output of each register numbered 63 is connected to input end of a register numbered 0 of the next 64bit shift register array; when the shift register is used as an 8-bit chain, 8 single-bit shift registers are transversely formed into 8-bit operation granularity shift registers, each 64-bit shift register array comprises 8-bit shift registers, shifting of the 8-bit registers is realized by adopting a longitudinal shifting direction, and the output of each register with the number of 56-63 is connected to the input end of a register with the number of 0-7 of the next 64-bit shift register array; when the shift register is used as a 16-bit chain, 16 single-bit shift registers in every two rows form a shift register with 16-bit operation granularity, each 64-bit shift register array comprises 4 16-bit shift registers, shifting of the 16-bit registers is realized by adopting a longitudinal shifting direction, and the output of each register with the number of 56-63 is connected to the input end of a register with the number of 0-7 of the next 64-bit shift register array; when the multi-chain type multi-bit shift register is used as a 32-bit chain, 32 single-bit shift registers in every four rows form a shift register with the granularity of 32-bit operation, each 64-bit shift register array comprises 2 32-bit shift registers, shifting of the 32-bit registers is realized by adopting a longitudinal shifting direction, the output of each register with the number of 56-63 is connected to the input end of a register with the number of 0-7 of the next 64-bit shift register array, the 16 64-bit shift register arrays can be cut into multiple chains in an integer multiple of 64 bits according to requirements, the feedback input of the reconfigurable feedback shift register array is output data of a reconfigurable data path, and the reconfigurable feedback shift register array can finish cascading of different modes among the shift registers and shifting with different directions and different granularities through configuration information.
Please refer to fig. 3: as shown in fig. 3, when the tap extraction network extracts, each of the 64-bit shift register arrays FSR1, FSR2, FSR3, …, FSR16 in the reconfigurable feedback shift register array is divided into 8 groups by taking 8 bits as a group, so that the whole reconfigurable feedback shift register array is totally divided into 16×8, i.e. 128 8 bits, extracted by taking 8 bits of the group as the minimum unit, four ways of extraction are divided, each way is that one 8bit is extracted from 128 8 bits by a multiplexer MUX, four ways are extracted by 48 bits altogether, then spliced into 32bit outputs, then the 32bit outputs are extracted and selected again according to the operation granularity of a specific stream cipher algorithm, if the operation granularity is 1bit, 1bit is extracted from the 32bit outputs by the multiplexer MUX, then, the high-order complementary 0 is spliced into new 32bit output, if the operation granularity is 8 bits, the 8 bits are extracted in the 32bit output through a multiplexer MUX, then the high-order complementary 0 is spliced into the new 32bit output, if the operation granularity is 16 bits, the 16 bits are extracted in the 32bit output, then the high-order complementary 0 is spliced into the new 32bit output, if the operation granularity is 32 bits, the 32 bits extracted at the beginning are directly output, the specific 32 bits are selected and output through the multiplexer MUX, the data extracted by a tap extraction network are sent into a reconfigurable operation unit array for operation, the number of the tap extraction network extraction is consistent with the number of the input interfaces of the reconfigurable operation unit, and the tap extraction network completes the extraction of taps at any different positions through configuration information.
Please refer to fig. 4: as shown in fig. 4, the reconfigurable operation unit array is composed of 12 rows and 4 columns of reconfigurable operation units (PE 1, PE2, …, PE 48), 3 heterogeneous lookup table units (LUT) and an interconnection network among the rows of reconfigurable operation units (PE), each 4 rows of PEs as a PE group share one heterogeneous lookup table unit (LUT), each reconfigurable operation unit (PE) has 4 32-bit inputs in0, in1, in2, in3 and 1 32-bit outputs out, and four 32-bit inputs in0, in1, in2, in3 are selected from the outputs of the other reconfigurable operation units (PE), heterogeneous lookup table units (LUT) and tap extraction network through a multiplexer MUX, each reconfigurable operation unit (PE) comprises 3 different functional units of a Logic Operation Unit (LOU), an arithmetic operation unit (AU) and a Shift Unit (SU), and a 32-bit register Reg is set at the output end of each reconfigurable operation unit (PE) for calculating the result. The configuration information configures the function and task execution sequence of the reconfigurable operation unit array, and the reconfigurable operation unit array is driven to execute by the data stream like an application specific integrated circuit after the configuration is completed.
In summary, the present invention is only the preferred embodiments, but the scope of the invention is not limited thereto, and any person skilled in the art should be able to apply equally to the present invention, and all changes and modifications made according to the technical solution and the inventive concept thereof are included in the scope of the present invention.
Claims (4)
1. The reconfigurable data circuit for the stream cipher algorithm is characterized by comprising a reconfigurable feedback shift register array, a tap extraction network, a reconfigurable operation unit array, feedback data selection, key stream data selection and a data storage module; the reconfigurable feedback shift register array is used for realizing cascade connection of different modes among registers and shift with different directions and different granularities; the tap extraction network is used for extracting taps at any different positions; the reconfigurable operation unit array is used for processing the stream cipher operation data stream; the feedback data selection is used for selecting data to be fed back from the output end of the reconfigurable operation unit array, and feeding back the data to be fed back to the reconfigurable feedback shift register array; the key stream data is selected to be used for selecting the key stream data from the output end of the reconfigurable operation unit array; the data storage module comprises an input data memory, an internal data cache and a key stream memory, wherein the input data memory is used for storing data which is read from the outside and is to participate in operation, the internal data cache is used for storing intermediate result data generated by a reconfigurable operation unit array, and the key stream memory is used for storing key stream data generated by a stream cipher algorithm;
the reconfigurable feedback shift register array comprises 16 64-bit shift register arrays, each 64-bit shift register array comprises 64 1-bit registers, each 1-bit register array selects a data input source through a 4-bit selector, each 1-bit register has a data output port, the reconfigurable feedback shift register array supports 1-bit, 8-bit, 16-bit and 32-bit operation granularity, when the reconfigurable feedback shift register array is used as a 1-bit chain, each row of the reconfigurable feedback shift register array is transversely connected, the output of each register with the number of 63 is connected to the input end of a register with the number of 0 of the next 64-bit shift register array, when the reconfigurable feedback shift register array is used as an 8-bit chain, each 1-bit register array comprises 8-bit shift registers, a longitudinal shift direction 8-bit shift register is adopted, each of the 1-bit shift register array is a single-bit register with the number of 63, when the output of each 64-bit register array is a single-bit register with the number of 32-bit array is adopted, the longitudinal shift 2-bit register array is respectively connected to the input end of each of the 64-bit array, when the two-bit register array is used as a single-bit register with the number of 32-bit array is adopted, the longitudinal shift array is connected to the input end of each of the 64-bit register array, and the two-bit register array is used as a single-bit register with the number of 32-bit register with the number of 64-bit register array is respectively, and the number of 64-bit register with the number of 64, and the 8-bit shift register array is respectively, and the 8, and the shift register with the 8-bit shift register with the granularity. The output of each register with the number of 56-63 is connected to the input end of the register with the number of 0-7 of the next 64-bit shift register array, and 16 64-bit shift register arrays can be cut into a plurality of chains in integer multiples of 64 bits according to requirements;
the tap extraction network comprises 4 multiplexers of 128 selection 1, 1 multiplexers of 32 selection 1, 2 multiplexers of 4 selection 1, 1 multiplexers of 2 selection 1 and four splicing modules, when the tap extraction network extracts, each 64bit shift register array in the reconfigurable feedback shift register array is divided into 8 groups by taking 8 bits as a group, the whole reconfigurable feedback shift register array is divided into 16 multiplied by 8, namely 128 8 bits, extraction is carried out by taking 8 bits of a packet as a minimum unit, four paths of extraction are respectively carried out by extracting one 8bit from the 128 8 bits by utilizing the 128 selection 1 multiplexers, 48 bits are extracted from the four paths of extraction, the 48 bits are spliced into 32bit output by the splicing modules, the 32bit output is selected again according to the operation granularity of a specific stream cipher algorithm, if the operation granularity is 1bit, extracting 1bit from the 32bit output by using a multiplexer of 32 option 1, then splicing the 32bit output into a new 32bit output by using a high-order complementary 0 of a splicing module, if the operation granularity is 8 bits, extracting 8 bits from the 32bit output by using a multiplexer of 4 option 1, then splicing the 32bit output into a new 32bit output by using a high-order complementary 0 of the splicing module, if the operation granularity is 16 bits, extracting 16 bits from the 32bit output by using a multiplexer of 2 option 1, then splicing the 32bit output into a new 32bit output by using a high-order complementary 0 of the splicing module, directly outputting the 32bit to be extracted, and finally selecting 32bit data which is required to be fed into a reconfigurable operation unit array to participate in operation from the 4 32bit outputs by using a multiplexer of 4 option 1, wherein the number of tap networks is consistent with the number of input interfaces of the reconfigurable operation units.
2. The reconfigurable data circuit for the stream cipher algorithm according to claim 1, wherein the reconfigurable operation unit array is composed of 12 rows of 4 columns of reconfigurable operation units PE, 3 heterogeneous look-up table unit LUTs and an interconnection network between the rows of the reconfigurable operation units PE, each reconfigurable operation unit PE includes logic operation units LOU, arithmetic operation units AU and shift units SU 3 different functional units, each 4 rows of reconfigurable operation units PE is used as a group to share one heterogeneous look-up table unit LUT, logic operation, arithmetic operation, shift operation and S-box operation in the stream cipher algorithm can be realized, each reconfigurable operation unit PE has 4 32bit inputs in0, in1, in2, in3 and 1 32bit outputs out, the 4 32bit inputs in0, in1, in2, in3 respectively select data input sources through 4 multiplexers, a 32bit register Reg is set at the output end of each reconfigurable operation unit PE as a group to share one heterogeneous look-up table unit LUT, the reconfigurable operation unit PE can be used as a feedback sequence to execute the reconfigurable operation array, the reconfigurable operation array can be extracted, or the reconfigurable operation array can be used as a feedback sequence to execute the reconfigurable operation array, and the reconfigurable operation can be used as a feedback sequence to execute the reconfigurable operation array.
3. The reconfigurable data circuit for a stream cipher algorithm according to claim 1, wherein the feedback data selection includes 1 multiplexer of 48-1 for selecting the data to be fed back from the output terminals of 48 reconfigurable operation units PE of the reconfigurable operation unit array, and feeding back to the reconfigurable feedback shift register array to continue to participate in the subsequent operation.
4. The reconfigurable data circuit for a stream cipher algorithm according to claim 1, wherein the key stream data selection includes 1 multiplexer of 48-1 for selecting the generated key stream data from the outputs of 48 reconfigurable operation units PE of the reconfigurable operation unit array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110542855.7A CN113259088B (en) | 2021-05-19 | 2021-05-19 | Reconfigurable data path oriented to stream cipher algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110542855.7A CN113259088B (en) | 2021-05-19 | 2021-05-19 | Reconfigurable data path oriented to stream cipher algorithm |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113259088A CN113259088A (en) | 2021-08-13 |
| CN113259088B true CN113259088B (en) | 2023-10-20 |
Family
ID=77182616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110542855.7A Active CN113259088B (en) | 2021-05-19 | 2021-05-19 | Reconfigurable data path oriented to stream cipher algorithm |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113259088B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114217858B (en) * | 2022-02-21 | 2022-06-07 | 深圳云豹智能有限公司 | Data processing circuit, system and data processing method |
| CN114217857B (en) * | 2022-02-21 | 2022-06-07 | 深圳云豹智能有限公司 | Data processing circuit, system and data processing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912501A (en) * | 2016-05-06 | 2016-08-31 | 东南大学—无锡集成电路技术研究所 | SM4-128 encryption algorithm implementation method and system based on large-scale coarseness reconfigurable processor |
| CN112564891A (en) * | 2020-12-11 | 2021-03-26 | 清华大学无锡应用技术研究院 | Sequence cipher algorithm computing system based on feedback shift register array |
| CN112579516A (en) * | 2020-12-24 | 2021-03-30 | 清华大学无锡应用技术研究院 | Reconfigurable processing unit array |
| CN112613080A (en) * | 2020-12-16 | 2021-04-06 | 哈尔滨理工大学 | Reconfigurable array unit and array for lightweight block cipher algorithm |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2715544B1 (en) * | 2011-06-03 | 2022-12-21 | Exelis Inc. | Method and system for embedded high performance reconfigurable firmware cipher |
| US9449257B2 (en) * | 2012-12-04 | 2016-09-20 | Institute Of Semiconductors, Chinese Academy Of Sciences | Dynamically reconstructable multistage parallel single instruction multiple data array processing system |
-
2021
- 2021-05-19 CN CN202110542855.7A patent/CN113259088B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105912501A (en) * | 2016-05-06 | 2016-08-31 | 东南大学—无锡集成电路技术研究所 | SM4-128 encryption algorithm implementation method and system based on large-scale coarseness reconfigurable processor |
| CN112564891A (en) * | 2020-12-11 | 2021-03-26 | 清华大学无锡应用技术研究院 | Sequence cipher algorithm computing system based on feedback shift register array |
| CN112613080A (en) * | 2020-12-16 | 2021-04-06 | 哈尔滨理工大学 | Reconfigurable array unit and array for lightweight block cipher algorithm |
| CN112579516A (en) * | 2020-12-24 | 2021-03-30 | 清华大学无锡应用技术研究院 | Reconfigurable processing unit array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113259088A (en) | 2021-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113259088B (en) | Reconfigurable data path oriented to stream cipher algorithm | |
| USRE44697E1 (en) | Encryption processor with shared memory interconnect | |
| US8625781B2 (en) | Encrypton processor | |
| CA2375749A1 (en) | Scalable cryptographic engine | |
| US8693681B2 (en) | Kasumi cipher executable instructions and circuitry | |
| US7653196B2 (en) | Apparatus and method for performing RC4 ciphering | |
| CN107181586B (en) | Reconfigurable S-box circuit structure | |
| GB2367461A (en) | Encryption apparatus using Data Encryption Standard (DES) | |
| CN108183790B (en) | AES encryption device, chip and system | |
| CN116094711B (en) | Post quantum lattice password hardware optimization structure based on instruction set | |
| CN111563281B (en) | Processor supporting multiple encryption and decryption algorithms and implementation method thereof | |
| Nadjia et al. | Aes ip for hybrid cryptosystem rsa-aes | |
| JPH10333569A (en) | Cipher processor, ic card and cipher processing method | |
| CN108400866B (en) | Coarse-grained reconfigurable cipher logic array | |
| CN108494547B (en) | AES encryption system and chip | |
| Rais et al. | Efficient hardware realization of advanced encryption standard algorithm using Virtex-5 FPGA | |
| CN108768615B (en) | ASIC chip implementation method of hash algorithm under same frame | |
| CN113922949B (en) | Cryptographic coprocessor based on CLEFIA-SHA3 | |
| Khan et al. | Area–time efficient implementation of nist lightweight hash functions targeting IoT applications | |
| Rais et al. | A novel FPGA implementation of AES-128 using reduced residue of prime numbers based S-Box | |
| WO2022120999A1 (en) | Feedback shift register array-based sequence cipher algorithm computing system | |
| TWI776474B (en) | Circuit module of single round advanced encryption standard | |
| WO2023040595A1 (en) | Chip, and method for generating message authentication code | |
| KR102348802B1 (en) | AES encryption and decryption circuit | |
| CN113343276B (en) | Encryption method of light-weight block cipher algorithm GCM based on generalized two-dimensional cat mapping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |