CN108400866B - Coarse-grained reconfigurable cipher logic array - Google Patents

Abstract

The application provides a coarse-grained reconfigurable array, comprising: the reconfigurable processing unit comprises 10 reconfigurable processing unit BPUs, wherein adjacent BPUs are interconnected through a connector CB, and terminals, which are not interconnected with other BPUs, in each BPU are connected with the CB; the CBs are interconnected through a switch box SB of a bidirectional interconnection structure to form an outer Mesh topological structure. The BPU includes: a reconfigurable processor BP; the BP comprises: and the input of each RCE is from an input interconnection network, and the operation result of each RCE is output through an output interconnection network to form an inner layer full interconnection topological structure. The Mesh + full interconnection double-layer topological structure can meet the mapping requirements of cryptographic algorithms with different structures, and simultaneously, hardware resources consumed by interconnection can be greatly reduced.

Description

Coarse-grained reconfigurable cipher logic array

Technical Field

The application relates to the field of cryptography, in particular to a coarse-grained reconfigurable cipher logic array.

Background

The symmetric cryptographic algorithm is an important cryptographic operation system and is widely applied to the field of information security, and the conventional symmetric cryptographic algorithm implementation method mainly comprises five modes of general processor implementation, customized ASIC design implementation, special instruction processor implementation, FPGA implementation and reconfigurable cryptographic logic array implementation.

However, for cryptographic operations, the first four ways described above all have certain disadvantages: the general processor lacks an arithmetic unit facing symmetric cryptographic processing, so that the execution efficiency is not high. Most of the customized ASICs are realized by one or more algorithms, the directivity is too strong, and the safety and the life cycle are greatly reduced. The special instruction processor is designed and realizes a special operation unit facing a symmetric cryptographic algorithm, overcomes the defects of a general processor, improves the cryptographic processing performance to a certain extent, but is influenced by data correlation and semiconductor technology, and the realization mode of the special instruction processor achieves the bottleneck in the single-core cryptographic processing performance and is difficult to meet the requirement of high-speed secure data transmission. The FPGA is mainly designed for the general field, an operation unit facing a symmetric cryptographic algorithm is also lacked, and meanwhile, the algorithm configuration process is complicated due to overlarge configuration information.

The reconfigurable cipher logic array can better overcome the defects. However, the existing reconfigurable cipher logic array cannot take both cipher mapping capability and hardware resource overhead into consideration.

Disclosure of Invention

The application provides a coarse-grained reconfigurable cipher logic array, and aims to solve the problem of considering both cipher mapping capability and hardware resource overhead.

In order to achieve the above object, the present application provides the following technical solutions:

a coarse-grained reconfigurable array comprising:

10 reconfigurable processing units (BPUs);

adjacent BPUs are interconnected through a connector CB, and terminals, which are not interconnected with other BPUs, in each BPU are connected with the CB; the CBs are interconnected through a switch box SB of a bidirectional interconnection structure;

the BPU includes: a reconfigurable processor BP;

the BP comprises: and the input of each RCE is from an input interconnection network, and the operation result of each RCE is output through an output interconnection network.

Optionally, the BPU further includes:

a reconfigurable S box unit BPU _ S and a reconfigurable key storage unit BPU _ K;

the interconnection between the adjacent BPUs through the connector CB comprises the following steps:

the BP, BP and BPU _ S, BP and BPU _ K, and BPU _ S and BPU _ K are interconnected by connectors CB.

Optionally, the BPUs are distributed in two rows, where the first row includes one BPU _ S and four BPs, and the second row includes one BPU _ K and four BPs.

Optionally, the method may be characterized in that,

the basic processing granularity of any BP is 32 bits, and the processing granularity of the BP on the same line is 128 bits;

the BPU _ S in the first row is connected with eight BPs in the row and the next row through long connecting lines, receives data from adjacent CBs and is used for realizing S box operation;

the BPU _ K in the second row is connected with eight BPs in the row and the previous row through long connection lines and receives data from adjacent CBs for realizing storage and distribution of keys.

Optionally, the BP includes:

the reconfigurable cipher operation system comprises a reconfigurable cipher operation element RCE, an input interconnection network and an output interconnection network, wherein the input interconnection network and the output interconnection network are designed by adopting a Crossbar full interconnection structure.

Optionally, the RCE includes:

the arithmetic type reconfigurable cipher operation element RCE _ AL is used for realizing arithmetic type operation in the coarse-granularity reconfigurable cipher logic array;

a permutation type reconfigurable cipher operation element RCE _ BP for realizing permutation type operation in the coarse-granularity reconfigurable cipher logic array;

the logic type reconfigurable cipher operation element RCE _ LG is used for realizing logic type operation in the coarse-granularity reconfigurable cipher logic array;

and the nonlinear reconfigurable cipher operation element RCE _ NF is used for realizing the nonlinear operation in the coarse-granularity reconfigurable cipher logic array.

Optionally, the RCE is connected to the output interconnection network through a bypassable register;

and the operation result of the RCE is output to the output interconnection network after a stage is registered or not registered by the bypass register.

A coarse-grained reconfigurable array comprising:

at least two coarse grain reconfigurable arrays as claimed in claim 1, wherein each BPU between adjacent coarse grain reconfigurable arrays as claimed in claim 1 is interconnected by a connector CB.

The coarse-grained reconfigurable array comprises: the reconfigurable processing unit comprises 10 reconfigurable processing unit BPUs, wherein adjacent BPUs are interconnected through a connector CB, and terminals, which are not interconnected with other BPUs, in each BPU are connected with the CB; the CBs are interconnected through a switch box SB of a bidirectional interconnection structure to form an outer Mesh topological structure. The BPU includes: a reconfigurable processor BP; the BP comprises: and the input of each RCE is from an input interconnection network, and the operation result of each RCE is output through an output interconnection network to form an inner layer full interconnection topological structure. The Mesh + full interconnection double-layer topological structure can meet the mapping requirements of cryptographic algorithms with different structures, and simultaneously, hardware resources consumed by interconnection can be greatly reduced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a coarse-grained reconfigurable array disclosed in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a BP in a coarse-grained reconfigurable array disclosed in an embodiment of the present application;

fig. 3 is a schematic structural diagram of another coarse-grained reconfigurable array disclosed in the embodiment of the present application.

Detailed Description

The symmetric cryptographic algorithm mainly comprises two categories of block cryptographic algorithm and sequence cryptographic algorithm, wherein the block cryptographic algorithm generally comprises Feistel structure, SP structure, L-M structure and MISTY structure, the sequence cryptographic algorithm is divided into self-control mode, other control mode, mutual control mode and the like, and the complex structural characteristics of the symmetric cryptographic algorithm cause the difficulty in mapping.

If the cost of hardware overhead is considered in the coarse-grained reconfigurable array, the complicated interconnection relationship inside the cryptographic algorithm is difficult to satisfy, and the situation that the algorithm is difficult to map is caused. If the array size is increased to satisfy the mapping of the cryptographic algorithm, the overhead is exponentially increased. It can be seen that, for the existing coarse-grained reconfigurable array, the mapping requirement of the cryptographic algorithm and the hardware overhead are incompatible contradictions.

The coarse-grained reconfigurable array disclosed by the embodiment of the application aims to solve the contradiction, and adopts a double-layer network to realize an external-layer MESH internal-layer fully-interconnected topological structure, so that the mapping capability of the array structure and the hardware resource overhead are balanced, and the encryption and decryption processing of a symmetric cryptographic algorithm can be efficiently realized.

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 1 is a coarse-grained reconfigurable array disclosed in an embodiment of the present application, including: 10 Reconfigurable Processing units (BPU), wherein the BPU is an operation structure set which is designed by adopting a Reconfigurable technology and faces to cryptographic algorithm Processing.

BPUs contain three types in total: the Reconfigurable system comprises a Reconfigurable S box unit (BPU _ S), a Reconfigurable key storage unit (BPU _ K) and a Reconfigurable Processor (BP), wherein the Reconfigurable processing unit comprises four types of Reconfigurable password operation elements (detailed description is given later). In fig. 1, BP1_1, BP1_2 … BP1_4, BP2_1 … BP2_4 are BPs. BPU _ S1_1 is BPU _ S, BPU _ K2_1 is BPU _ K.

In fig. 1, adjacent BPUs (i.e., BP and BPU _ S, BP and BPU _ K, and BPU _ S and BPU _ K) are interconnected by connectors (Connect Box, CB). Terminals of the respective BPUs not interconnected with other BPUs are connected to the CB, for example, in fig. 1, left and upper terminals of BPU _ S1_1 are connected to the CB, and right and upper terminals of BPU1_4 are adjacent to the CB. The CBs are interconnected by a Switch Box (SB) of a bidirectional interconnection structure. The above connections form a 2D-Mesh topology.

In fig. 1, the basic processing granularity of the BPs 1_1 to BP2_4 is 32 bits, and the BPs on the same row can be cascaded to realize 128-bit wide operation. The BPU _ S1_1 is connected with BP1_ 1-BP 2_4 through a long connecting line, and can also receive data from adjacent CBs for realizing S-box operation.

The BPU _ K2_1 and the BPU _ S1_1 are connected with the BPs 1_ 1-2 _4 through long connecting lines, and can also receive data from adjacent CBs, and are mainly used for storing and distributing keys.

The above interconnected BPUs, CBs and SBs form the outer layer of the coarse-grained reconfigurable array.

The inner layer structure of the coarse-grained reconfigurable array is a specific structure of BP, as shown in fig. 2, and includes: the Reconfigurable Cryptographic operation elements (RCEs) of 4 types (including an arithmetic Reconfigurable Cryptographic operation Element RCE _ AL, a permutation Reconfigurable Cryptographic operation Element RCE _ BP, a logic Reconfigurable Cryptographic operation Element RCE _ LG and a nonlinear Reconfigurable Cryptographic operation Element RCE _ NF) are Input from an Input interconnection Network (Input Network), and the operation result of each RCE is selected by a first-level bypassable register (Data Flip-Flop, DFF) to be registered or not and then Output to an Output interconnection Network (Output Network). The input and output interconnection network adopts a Crossbar full interconnection structure design to meet the interconnection requirements of any input and output. The DFF selects the basis of registering or not registering as follows: the performance of algorithm mapping is related to the number of algorithm mapping steps and the delay of the maximum key path of the algorithm, wherein the maximum key path of the algorithm is a combination of each RCE key path, the DFF selects to register so that the number of algorithm mapping steps is increased and the delay of the maximum key path is possibly reduced, and the DFF does not select to register so that the number of algorithm mapping steps is reduced and the delay of the maximum key path is possibly increased, so that whether the DFF is registered or not needs to be selected according to an actual algorithm mapping scene, and higher algorithm mapping implementation performance is obtained.

In conclusion, the double-layer topological structure of the coarse-granularity reconfigurable cipher logic array 'Mesh + full interconnection' can meet the mapping requirements of cipher algorithms with different structures, and simultaneously can greatly reduce hardware resources consumed by interconnection.

The specific implementation principle and process of the functions of the BPU, CB, and SB can be referred to in the prior art, and are not described herein.

In the process of research, the applicant obtains the following four conclusions about the symmetric cryptographic algorithm through the analysis and research of the existing symmetric cryptographic algorithm:

(1) the basic operation types are various. A number of basic operation types are included in symmetric cryptographic algorithms, such as and, or, not, xor, shift, permute, S-box substitution, arithmetic add/subtract, modulo add/subtract, arithmetic multiply, modulo multiply, finite field multiply, non-linear boolean functions, feedback shift registers, etc. Meanwhile, most of the symmetric cryptographic algorithms are unsigned integer arithmetic, floating point and fixed point type arithmetic do not exist, and negative numbers generally do not appear in the arithmetic.

(2) The same operation type has various modes. Each basic operation type in the symmetric cryptographic algorithm has more than one operation mode, for example, the shift operation can be divided into left shift and right shift according to the shift direction, can be divided into logic shift and cyclic shift according to the shift type, and can be divided into fixed length shift and variable length shift according to the shift digit; s-box substitutions also include common types such as 4-4S boxes, 6-4S boxes, 8-8S boxes, 8-32S boxes, etc., as well as special types such as 13-8S boxes, 11-8S boxes, etc. The different operation modes of the same operation type enable basic operations in the symmetric cryptographic algorithm to be more diversified.

(3) The basic operation processing granularity is various. The basic operation processing granularity in the symmetric cryptographic algorithm mainly comprises the granularity based on bytes, half words, double words, four words and the like, is similar to the operation mode of basic operation, has no essential difference on the operation method in different processing granularities, and can realize large bit width operation through the cascade connection of small bit width operation. However, in terms of hardware implementation, the cascade connection of small bit width operation will cause the increase of interconnection resources, and the implementation of small bit width operation by using a large bit width operation unit will cause the waste of hardware resources. Therefore, it is important to reasonably plan the processing granularity of the basic arithmetic unit.

(4) The non-linear boolean functions and term orders are centered on the lower orders. The sequence cipher algorithm in the symmetric cipher algorithm is mostly realized by combining a feedback shift register and a nonlinear Boolean function, the series number of the common feedback shift register is usually more than 64, but the number of feedback taps participating in nonlinear Boolean function operation, namely the number of nonlinear Boolean functions and terms, is mostly less than 8, and the number of terms of a few algorithms is more than 10.

Most of the existing cryptographic chips are designed and realized based on one or more cryptographic algorithms, and the basic operation units have strong pertinence, namely, each basic operation unit corresponds to an operation link in the algorithm. The basic operation unit realized by the method has higher processing performance, but the flexibility is greatly reduced, so that a large number of basic operation units are required in the cryptographic chip, powerful support is provided for the realization of the cryptographic algorithm, a large number of hardware resources are consumed, huge system power consumption is brought, and secondary development of the chip is not facilitated.

According to the conclusion, the reconfigurable symmetric cryptographic algorithm operation unit is designed according to the following principle:

(1) and aiming at the same basic operation type, the differences and the connection among different operation modes are researched so as to realize the reconfiguration of the same basic operation type.

(2) The characteristics of the realization structure of the reconfigurable basic operation unit are researched aiming at different basic operation types, so that basic operation units with similar structures are integrated to realize the reconfiguration of different basic operation types.

According to the design principle, in fig. 2, the arithmetic reconfigurable cipher operation element RCE _ AL is mainly used for implementing arithmetic operations in the coarse-grained reconfigurable cipher logic array, including arithmetic addition and subtraction, modulo addition and subtraction, arithmetic multiplication, modulo multiplication, finite field multiplication, and the like. The permutation type reconfigurable cipher operation element RCE _ BP is mainly used for realizing permutation type operation in a coarse-granularity reconfigurable cipher logic array, and comprises operations of bit permutation, byte permutation, shift, insertion and extraction and the like. The logic type reconfigurable cipher operation element RCE _ LG is mainly used for realizing logic type operation in a coarse-grained reconfigurable cipher logic array, and comprises basic logic operation such as AND, OR, NOT, XOR and the like, complex logic operation such as a three-input Boolean function, a linear feedback shift register and the like, and derivative operation thereof. The nonlinear reconfigurable cipher operation element RCE _ NF is mainly used for realizing nonlinear operations in coarse-grained reconfigurable cipher logic arrays, including nonlinear Boolean function and nonlinear feedback shift register operations.

In accordance with the above principles, in addition to the above setting of RCE, BPU _ S shown in fig. 1 may be set to the following functions: the reconfigurable S-box operation unit is arranged on the basis of 8-8 RAM, and can support 4-4, 6-4, 8-8 and 8-32 types of S-boxes through four groups of cascades.

In the research process of the applicant, the applicant also finds that the performance of certain algorithms which are not mapped to the reconfigurable cipher elements with the maximum path delay is greatly reduced if the reconfigurable cipher elements with the maximum path delay are used as the critical path delay of the whole array because the reconfigurable cipher elements in the coarse-granularity reconfigurable cipher logic array have different design complexity and the critical path delay difference is large.

Based on this, as shown in fig. 2, a bypassable register structure DFF is added between the interconnected output of the reconfigurable cryptographic elements and the output network. Since the key path delay is the path delay between two adjacent registers, if the registers are bypassed, the critical path delay is correspondingly increased, but due to the reduction of the operation period, if the product of the operation period of the algorithm multiplied by the maximum critical path is reduced, the mapping performance of the algorithm is improved.

The coarse-grained reconfigurable cipher logic array shown in fig. 1 is a basic array structure proposed in the present application, and the basic array structure can be expanded.

Fig. 3 is a coarse-grained reconfigurable cipher logic array topology with a scale of 4 × 4, which includes 20 BPUs, where the BPUs include 4 types of reconfigurable cipher operation elements RCE, BPU _ S is a reconfigurable S box unit, BPU _ K is a reconfigurable key storage unit, and BP is a reconfigurable processor. The connection relationship between the BPUs can be seen in fig. 1, and is not described herein.

The basic processing granularity of the BPUs 1_ 1-4 _4 is 32 bits, and the BPUs on the same line can be cascaded to realize 128-bit wide operation. The BPU _ S1_1 is connected with the BPUs 1_ 1-2 _4 through long connecting lines, and can also receive data from adjacent CBs for realizing S box operation. Similarly, the BPU _ S3_1 is connected to the BPUs 3_1 to 4_4 via long lines, and can receive data from adjacent CBs to implement S-box operation. The BPU _ K2_1 is connected with the BPU _ S1_1 in the same way, and the BPU _ K4_1 is connected with the BPU _ S3_1 in the same way, and is mainly used for storing and distributing keys.

To sum up, the coarse-grained reconfigurable array disclosed in the embodiment of the present application adopts a two-layer network to implement a topology structure in which an outer MESH layer and an inner MESH layer are fully interconnected. The outer layer realizes the connection of all reconfigurable processing units through CB and SB, and realizes the interconnection of different reconfigurable processing units through the path configuration of CB and SB. The inner layer adopts a Crossbar structure to realize the full interconnection of the reconfigurable password operation elements. Meanwhile, a special reconfigurable cipher operation element is designed for the symmetric cipher algorithm, and the expansion of the existing symmetric cipher algorithm and the future cipher algorithm can be effectively supported. In addition, the array topology realized by the invention is a frequency-variable topology structure, a bypass output register structure is designed and realized, and the invention can work at the optimal working frequency aiming at different cipher mapping schemes so as to realize the maximum data throughput rate.

The flow of the coarse-grained reconfigurable array mapping password shown in fig. 1 or fig. 3 comprises the following steps:

1. the symmetric cryptographic algorithm is converted into a dataflow graph.

2. And mapping the algorithm data flow graph to a coarse-grained reconfigurable cipher logic array (each reconfigurable operation element selects and registers one-level output).

The basic process of mapping is as follows:

and converting each operation in the data flow diagram into a corresponding reconfigurable operation unit type, and mapping in a certain BPU in the coarse-grained reconfigurable array according to a breadth-first mapping algorithm. When a mapping conflict occurs, the operation is mapped to the adjacent BPUs, and meanwhile, the interconnection between the BPUs is mapped according to the shortest path algorithm.

The mapping relation is determined according to the operation types supported by the operator type and the five types of reconfigurable operations in the symmetric cryptographic algorithm, and if the operation types of the operator type and the five types of reconfigurable operations are the same, the mapping relation can exist.

3. And adjusting whether each bypassable register registers or not, and calculating the algorithm performance in the corresponding mapping mode.

4. And selecting a mapping scheme with the best algorithm performance for mapping.

The functions described in the method of the embodiment of the present application, if implemented in the form of software functional units and sold or used as independent products, may be stored in a storage medium readable by a computing device. Based on such understanding, part of the contribution to the prior art of the embodiments of the present application or part of the technical solution may be embodied in the form of a software product stored in a storage medium and including several instructions for causing a computing device (which may be a personal computer, a server, a mobile computing device or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (5)

1. A coarse-grained reconfigurable array, comprising:

10 reconfigurable processing units (BPUs);

adjacent BPUs are interconnected through a connector CB, and terminals, which are not interconnected with other BPUs, in each BPU are connected with the CB; the CBs are interconnected through a switch box SB of a bidirectional interconnection structure;

the BPU includes: a reconfigurable processor BP;

the BP comprises: reconfigurable password operation elements RCE, wherein the input of each RCE is from an input interconnection network, and the operation result of each RCE is output through an output interconnection network;

wherein the BPU further comprises:

a reconfigurable S box unit BPU _ S and a reconfigurable key storage unit BPU _ K;

the interconnection between the adjacent BPUs through the connector CB comprises the following steps:

the BP, the BP and the BPU _ S, the BP and the BPU _ K and the BPU _ S and the BPU _ K are interconnected through connectors CB;

the BPUs are distributed into two rows, wherein the first row comprises one BPU _ S and four BPs, and the second row comprises one BPU _ K and four BPs;

wherein the content of the first and second substances,

the basic processing granularity of any BP is 32 bits, and the processing granularity of the BP on the same line is 128 bits;

the BPU _ S in the first row is connected with eight BPs in the row and the next row through long connecting lines, receives data from adjacent CBs and is used for realizing S box operation;

the BPU _ K in the second row is connected with eight BPs in the row where the BPU _ K is located and the previous row through long connecting lines, and receives data from adjacent CBs for realizing storage and distribution of keys.

2. The coarse grain reconfigurable array of claim 1, wherein the BP comprises:

the reconfigurable cipher operation system comprises a reconfigurable cipher operation element RCE, an input interconnection network and an output interconnection network, wherein the input interconnection network and the output interconnection network are designed by adopting a Crossbar full interconnection structure.

3. The coarse grain reconfigurable array of claim 2, wherein the RCE comprises:

the arithmetic type reconfigurable cipher operation element RCE _ AL is used for realizing arithmetic type operation in the coarse-granularity reconfigurable cipher logic array;

a permutation type reconfigurable cipher operation element RCE _ BP for realizing permutation type operation in the coarse-granularity reconfigurable cipher logic array;

the logic type reconfigurable cipher operation element RCE _ LG is used for realizing logic type operation in the coarse-granularity reconfigurable cipher logic array;

and the nonlinear reconfigurable cipher operation element RCE _ NF is used for realizing the nonlinear operation in the coarse-granularity reconfigurable cipher logic array.

4. The coarse grain reconfigurable array of claim 2, wherein the RCEs are connected to the output interconnect network through bypassable registers;

and the operation result of the RCE is output to the output interconnection network after a stage is registered or not registered by the bypass register.

5. A coarse-grained reconfigurable array, comprising:

at least two coarse grain reconfigurable arrays as claimed in claim 1, wherein each BPU between adjacent coarse grain reconfigurable arrays as claimed in claim 1 is interconnected by a connector CB.

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