CN108400866A - A kind of restructural cryptologic array of coarseness - Google Patents
A kind of restructural cryptologic array of coarseness Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
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Abstract
This application provides a kind of coarse-grained reconfigurable arrays, including：It is interconnected by connector CB between 10 reconfigurable processing units BPU, adjacent each BPU, is not connect with CB with the terminal of other BPU interconnection in each BPU；It is interconnected by two-way interconnection structure switch enclosure SB between each CB, the above composition outer layer Mesh topological structures.The BPU includes：Reconfigurable processor BP；The BP includes：The input of restructural crypto-operation element RCE, each RCE come from input interference networks, and the operation result of each RCE constitutes internal layer full-mesh topology structure by exporting interference networks output.The double-deck topological structure of " Mesh+ is totally interconnected " can not only meet the mapping demand of different structure cryptographic algorithm, meanwhile, it can be greatly reduced and interconnect consumed hardware resource.
Description
Technical field
This application involves field of cryptography more particularly to a kind of restructural cryptologic arrays of coarseness.
Background technology
Symmetric cryptographic algorithm is widely used in information security field as a kind of important crypto-operation system, existing right
Title cryptographic algorithms' implementation method mainly has general processor to realize, customization ASIC design is realized, dedicated instruction processor is realized,
FPGA is realized and restructural cryptologic array realizes five kinds of modes.
But for crypto-operation, above-mentioned preceding four kinds of modes all have certain deficiency：Wherein, general processor is because of it
Lack the arithmetic element handled towards symmetric cryptography, execution efficiency is not high.ASIC is customized mostly towards a certain or certain several calculation
Method realizes that directive property is too strong, and safety and life cycle all substantially reduce.Dedicated instruction processor has been designed and Implemented towards right
The special arithmetic unit for claiming cryptographic algorithm, overcomes the defect of general processor, improves Cipher Processing to a certain extent
Can, but influenced by data correlation and semiconductor technology, the realization method of dedicated instruction processor is in monokaryon Cipher Processing
On energy, bottleneck is had reached, it is difficult to meet high-speed secure data transfer demands.FPGA is mainly directed towards general field design, same to lack
The weary arithmetic element towards symmetric cryptographic algorithm, meanwhile, configuration information amount is excessive to cause its algorithm configuration process complicated.
Restructural cryptologic array can preferably overcome above-mentioned deficiency.However, existing restructural cryptologic battle array
Row can not take into account password mapping ability and hardware resource cost.
Invention content
This application provides a kind of restructural cryptologic arrays of coarseness, it is therefore intended that how solution takes into account password mapping
The problem of ability and hardware resource cost.
To achieve the goals above, this application provides following technical schemes：
A kind of coarse-grained reconfigurable array, including：
10 reconfigurable processing unit BPU；
Be interconnected by connector CB between adjacent each BPU, in each BPU not with other BPU interconnection terminal with
CB connections；It is interconnected by two-way interconnection structure switch enclosure SB between each CB；
The BPU includes：Reconfigurable processor BP；
The BP includes：The input of restructural crypto-operation element RCE, each RCE come from input interference networks, each RCE
Operation result pass through export interference networks output.
Optionally, the BPU further includes：
Reconfigurable S-box unit B PU_S and restructural key storing unit BPU_K；
Between adjacent each BPU by connector CB be interconnected including：
It is carried out between each BP, BP and BPU_S, between BP and BPU_K and by connector CB between BPU_S and BPU_K
Interconnection.
Optionally, the BPU is distributed as two rows, wherein the first row includes BPU_S and four BP, and the second row includes
One BPU_K and four BP.
Optionally, which is characterized in that
The basic handling granularity of any one BP is 32 bits, and the processing granularity with the BP in a line is 128 bits；
BPU_S in the first row by long line be expert at and rear a line in eight BP connect, and receive and come from phase
The data of adjacent CB, for realizing S box operations；
BPU_K in second row by long line be expert at and previous row in eight BP connect, and receive and come from phase
The data of adjacent CB, for realizing the storage and distribution for key.
Optionally, the BP includes：
Restructural crypto-operation element RCE, input interference networks and output interference networks, the input interference networks and institute
It states output interference networks and uses the totally interconnected structure designs of Crossbar.
Optionally, the RCE includes：
The restructural crypto-operation element RCE_AL of arithmetic class, for realizing in the restructural cryptologic array of the coarseness
Arithmetic class operation；
The restructural crypto-operation element RCE_BP of class is replaced, for realizing in the restructural cryptologic array of the coarseness
Displacement class operation；
The restructural crypto-operation element RCE_LG of logic class, for realizing in the restructural cryptologic array of the coarseness
Logic class operation；
The non-linear restructural crypto-operation element RCE_NF of class, for realizing the restructural cryptologic array of the coarseness
In non-linear class operation.
Optionally, the RCE by can bypass register be connected with the output interference networks；
The operation result of the RCE bypass register deposit or can not deposit after level-one output to the output by described
Interference networks.
A kind of coarse-grained reconfigurable array, including：
At least two coarse-grained reconfigurable arrays described in claim 1, adjacent coarseness described in claim 1 can
Each BPU between restructuring array is interconnected by connector CB.
Coarse-grained reconfigurable array described herein, including：10 reconfigurable processing units BPU, adjacent each BPU it
Between be interconnected by connector CB, in each BPU not with other BPU interconnection terminal connect with CB；Pass through between each CB
Two-way interconnection structure switch enclosure SB interconnection, the above composition outer layer Mesh topological structures.The BPU includes：Reconfigurable processor BP；
The BP includes：The input of restructural crypto-operation element RCE, each RCE come from input interference networks, the operation knot of each RCE
Fruit constitutes internal layer full-mesh topology structure by exporting interference networks output.The double-deck topological structure of " Mesh+ is totally interconnected " is not only
It disclosure satisfy that the mapping demand of different structure cryptographic algorithm, meanwhile, it can be greatly reduced and interconnect consumed hardware resource.
Description of the drawings
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of application for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of coarse-grained reconfigurable array disclosed in the embodiment of the present application；
Fig. 2 is the structural schematic diagram of the BP in coarse-grained reconfigurable array disclosed in the embodiment of the present application；
Fig. 3 is the structural schematic diagram of another coarse-grained reconfigurable array disclosed in the embodiment of the present application.
Specific implementation mode
Symmetric cryptographic algorithm includes mainly block cipher and stream cipher algorithm two major classes, wherein block cipher
Generally by Feistel structures, SP structures, L-M structures and MISTY structure compositions, stream cipher is divided into as automatic control, its control, cross complaint
Isotype, the design feature of symmetric cryptographic algorithm complexity cause the difficulty in mapping.
Coarse-grained reconfigurable array is then difficult to meet complicated inside cryptographic algorithm if it is considered that hardware spending cost
Interconnected relationship, the case where to cause algorithm to be difficult to map.And if increasing array scale to meet the mapping of cryptographic algorithm,
Then can expense exponentially be increased.As it can be seen that for existing coarse-grained reconfigurable array, the mapping of cryptographic algorithm needs
It is the contradiction that can not be reconciled to ask with hardware spending.
Coarse-grained reconfigurable array disclosed in the embodiment of the present application, it is therefore intended that above-mentioned contradiction is solved, using double-layer network
Realize a kind of topological structure that outer layer MESH internal layers interconnect entirely, balanced array structure mapping ability and hardware resource cost,
So as to efficiently realize that symmetric cryptographic algorithm encryption and decryption is handled.
Below in conjunction with the attached drawing in the embodiment of the present application, technical solutions in the embodiments of the present application carries out clear, complete
Site preparation describes, it is clear that described embodiments are only a part of embodiments of the present application, instead of all the embodiments.It is based on
Embodiment in the application, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall in the protection scope of this application.
Fig. 1 is a kind of coarse-grained reconfigurable array disclosed in the embodiment of the present application, including：10 reconfigurable processing units
(Block Reconfigurable Processing Unit, BPU), wherein BPU be using Reconfiguration Technologies design towards
The operating structure collection of cryptographic algorithm processing.
BPU includes three types altogether：Reconfigurable S-box unit (BPU_S), restructural key storing unit (BPU_K) and
Reconfigurable processor (Block Reconfigurable Processor, BP), wherein reconfigurable processing unit include four classes again
Restructural crypto-operation element (follow-up to be described in detail).In Fig. 1, BP1_1, BP1_2 ... BP1_4, BP2_1 ... BP2_4 BP.
BPU_S1_1 is BPU_S, BPU_K2_1 BPU_K.
In Fig. 1, between adjacent each BPU (between i.e. each BP, BP and BPU_S, between BP and BPU_K and BPU_S with
Between BPU_K) it is interconnected by connector (Connect Box, CB).In each BPU not with other BPU interconnection terminal with
CB connections, for example, in Fig. 1, the left side of BPU_S1_1 and upper terminal are connected with CB, BPU1_4 right hand terminals and upside and CB phases
It is adjacent.It is interconnected by two-way interconnection structure switch enclosure (Switch Box, SB) between each CB.The above connection forms a 2D-
The topological structure of Mesh.
In Fig. 1, the basic handling granularity of BP1_1~BP2_4 is 32 bits, and realization 128 can be cascaded with the BP in a line
Bit bit wide operation.BPU_S1_1 is attached by long line with BP1_1~BP2_4, while can also be received from adjacent C B
Data, for realizing S box operations.
BPU_K2_1 and BPU_S1_1 is attached by long line with BP1_1~BP2_4, while can also be received from phase
The data of adjacent CB are mainly used for the storage and distribution of key.
BPU, CB and the SB being connected with each other above constitute the outer layer of coarse-grained reconfigurable array.
The endothecium structure of coarse-grained reconfigurable array is the concrete structure of BP, as shown in Fig. 2, including：4 classes are restructural close
Code operational element (Reconfigurable Cryptographic Element, RCE) (including the restructural crypto-operation of arithmetic class
Element RCE_AL, the restructural crypto-operation element RCE_BP of displacement class, the restructural crypto-operation element RCE_LG of logic class and non-
The restructural crypto-operation element RCE_NF of linear class), the input of each RCE comes from input interference networks (Input Network),
The operation result of each RCE through level-one can bypass register (Data Flip-Flop, DFF) choose whether deposit after output to export
Interference networks (Output Network).Input, output interference networks use the totally interconnected structure designs of Crossbar, are appointed with meeting
The interconnection needs of meaning input, output.Wherein, DFF select to deposit or the foundation do not deposited for：The performance and algorithm of Algorithm mapping
It maps step number and algorithm maximum critical path delay is related, wherein algorithm maximum critical path is the group of each RCE critical paths again
It closes, DFF selection deposits will be such that Algorithm mapping step number increases and maximum critical path delay may be made to reduce, and DFF does not select to post
Depositing will be such that Algorithm mapping step number reduces and maximum critical path delay may be made to increase, it is therefore desirable to map field according to actual algorithm
Whether scape selects the deposit to DFF, performance is realized to obtain higher Algorithm mapping.
The double-deck topological structure of the restructural cryptologic array " Mesh+ is totally interconnected " of coarseness in summary can not only
Meet the mapping demand of different structure cryptographic algorithm, meanwhile, it can be greatly reduced and interconnect consumed hardware resource.
The specific implementation principle and process of the function of above BPU, CB and SB, may refer to the prior art, no longer superfluous here
It states.
Applicant in the course of the study, by the analysis and research to existing symmetric cryptographic algorithm, obtains about symmetrical
Following four conclusions of cryptographic algorithm：
(1) basic operation type class is various.A large amount of basic operation type is contained in symmetric cryptographic algorithm, such as with,
Or non-, exclusive or, displacement, displacement, the replacement of S boxes, arithmetic plus/minus method, mould plus/minus method, arithmetic multiplication, modular multiplication, finite field multiplier,
Non-linear Boolean function, feedback shift register etc..Meanwhile symmetric cryptographic algorithm is mostly signless integer arithmetic, is not deposited
Generally be not in negative in floating-point and fixed point type operation, and in operation.
(2) same arithmetic type pattern is various.Each basic operation type in symmetric cryptographic algorithm all exists more than
A kind of operation mode is moved to left and is moved to right as shift operation can be divided into according to direction of displacement, can be divided into according to shift-type
Logical shift and cyclic shift can be divided into regular length displacement and variable length shift according to shift amount；The replacement of S boxes is also wrapped
Common type such as 4-4S boxes, 6-4S boxes, 8-8S boxes, 8-32S boxes etc. and specific type such as 13-8S boxes, 11-8S boxes etc. are contained.
The nonidentity operation pattern of same arithmetic type keeps the basic operation in symmetric cryptographic algorithm more diversified.
(3) basic operation processing granularity is various.Basic operation processing granularity in symmetric cryptographic algorithm mainly contains base
In byte, half-word, word, double word and four word equigranulars, similar with the operation mode of basic operation, different processing granularities are in operation
The difference of essence is had no in method, meanwhile, big bit wide operation can be realized by the cascade of small bit wide operation.But in hardware realization
On, the increase of ICR interconnection resource is caused using the grade joint conference of small bit wide operation, and big bit wide arithmetic element is used to realize small bit wide fortune
The waste of hardware resource can then be brought by calculating.Therefore, make rational planning for basic processing unit processing granularity it is most important.
(4) non-linear Boolean function concentrates on low order with item number.Stream cipher algorithm in symmetric cryptographic algorithm is adopted more
Combine realization with non-linear Boolean function with feedback shift register, common feedback shift register series often 64 grades with
On, but the feedback tap number, that is, non-linear Boolean function for participating in non-linear Boolean function operation is less than mostly with item number
8 times, a small number of algorithms are more than 10 times with item number.
Existing password chip is mostly based on a certain or certain several cryptographic algorithm design and realizes that basic processing unit has
Extremely strong specific aim, i.e. each basic processing unit all correspond to an operation link in algorithm.It is real in this way
Existing basic processing unit has higher process performance, but can have a greatly reduced quality in flexibility so that is needed inside crypto chip
A large amount of basic processing unit is wanted, is provided strong support for the realization of cryptographic algorithm, to consume a large amount of hardware resource and band
Carry out huge system power dissipation, while being unfavorable for the secondary development of the chip.
According to above-mentioned conclusion, restructural symmetric cryptographic algorithm arithmetic element is designed according to following principle：
(1) it is directed to identical basic operation type, difference between its nonidentity operation pattern is studied and contacts, it is identical to realize
Basic operation type it is restructural.
(2) it is directed to different basic operation types, studies the feature in its realization structure, to which structure is similar basic
Arithmetic element is integrated, to realize the restructural of different basic operation types.
According to above-mentioned design principle, in Fig. 2, the restructural crypto-operation element RCE_AL of arithmetic class is mainly used for realizing coarse grain
Spend the arithmetic class operation in restructural cryptologic array, including arithmetic addition and subtraction, mould addition and subtraction, arithmetic multiplication, modular multiplication and
The operations such as finite field multiplier.The displacement restructural crypto-operation element RCE_BP of class is mainly used for realizing that the restructural password of coarseness is patrolled
Collect the operations such as the displacement class operation in array, including bit permutation, byte substitution, displacement, insertion extraction.Logic class is restructural close
Code operational element RCE_LG be mainly used for realize the restructural cryptologic array of coarseness in logic class operation, including with or
The basic logic operations such as non-, exclusive or, three input the operations of the complex logics such as Boolean function and linear feedback shift register and its spread out
Raw operation.The non-linear restructural crypto-operation element RCE_NF of class is mainly used for realizing in the restructural cryptologic array of coarseness
Non-linear class operation, including non-linear Boolean function, nonlinear feedback shift register generic operation.
BPU_S shown in Fig. 1 can also be set to other than carrying out above-mentioned setting to RCE according to mentioned above principle
Following functions：Reconfigurable S-box arithmetic element is configured based on the RAM of 8-8, and 4-4,6- can be supported by four groups of cascades
4, the S boxes of five type of 8-4,8-8 and 8-32.
Applicant also found in the course of the study, due to each restructural password in the restructural cryptologic array of coarseness
Element design complexities are different, and critical path delay differs greatly, according to the restructural cryptographic element of maximum path delay
As the critical path delay of entire array, then for certain algorithms for being not mapped to the element, performance will substantially reduce.
Based on this, as shown in Fig. 2, being added to and can bypass between the interconnection output and output network of restructural cryptographic element
Register architecture DFF.Since key path delay is the path delay between calculating two adjunct registers, if register is bypassed,
Critical path delay accordingly increases, but due to the reduction of execution cycle, if the execution cycle of algorithm be multiplied by maximum critical path it
Product becomes smaller, then the mapping performance of algorithm will be promoted.
The restructural cryptologic array of coarseness shown in FIG. 1 is a kind of basic array structure that the application proposes, at this
In basic array structure, it can be extended.
Fig. 3 is the restructural cryptologic array topology of coarseness that scale is 4x4, includes 20 BPU altogether, wherein
BPU includes the restructural crypto-operation element RCE of 4 classes, and BPU_S is Reconfigurable S-box unit, and BPU_K is restructural key storage list
Member, BP are reconfigurable processor.Connection relation between each BPU can be found in Fig. 1, and which is not described herein again.
The basic handling granularity of BPU1_1~BPU4_4 is 32 bits, can be cascaded with the BPU in a line and realize 128 bits
Bit wide operation.BPU_S1_1 is attached by long line with BPU1_1~BPU2_4, while can also be received from adjacent C B's
Data, for realizing S box operations.Likewise, BPU_S3_1 is attached by long line with BPU3_1~BPU4_4, while
It can receive the data from adjacent C B, for realizing S box operations.BPU_K2_1 is identical as BPU_S1_1 connection types, BPU_K4_
1 is identical as BPU_S3_1 connection types, is mainly used for the storage and distribution of key.
In conclusion coarse-grained reconfigurable array disclosed in the embodiment of the present application, is realized using double-layer network outside one kind
The totally interconnected topological structure of layer MESH internal layers.Outer layer realizes the connection of each reconfigurable processing unit by CB and SB, by right
The path of CB and SB configures, and realizes the interconnection of different reconfigurable processing units.Internal layer is realized and can be weighed using crossbar fabric
Structure crypto-operation element it is totally interconnected.Meanwhile devising dedicated restructural crypto-operation element, energy for symmetric cryptographic algorithm
Enough extensions for effectively supporting existing symmetric cryptographic algorithm and future cryptographic algorithm.In addition, the array topology that the present invention is realized is
A kind of topological structure of changeable frequency, output deposit structure can be bypassed by having designed and Implemented, for different password mapping schemes,
The present invention can be operated in frequency optimum traffic, to realize maximum data throughput.
The flow of Fig. 1 or shown in Fig. 3 coarse-grained reconfigurable arrays mapping password includes the following steps：
1, symmetric cryptographic algorithm is converted into data flow diagram.
2, algorithm data flow graph is mapped into the restructural cryptologic array of coarseness (each restructural operational element selects
Deposit level-one output).
The basic process that it is mapped is as follows：
Each operation in data flow diagram is converted to corresponding reconfigurable arithmetic unit type, according to breadth First mapping algorithm
It is mapped in a certain BPU in coarse-grained reconfigurable array.When there is mapping conflict, operation is mapped into neighbouring BPU,
Simultaneously according to the interconnection between shortest path first Mapping B PU.
Mapping relations are the operation classes supported with the restructural operation of five classes according to the operator type in symmetric cryptographic algorithm
What type determined, mapping relations may be present if the two arithmetic type is identical.
3, adjustment respectively can bypass register deposit whether, and calculate the algorithm performance under correspondence mappings pattern.
4, the best mapping scheme of Algorithms of Selecting performance is mapped.
If the function described in the embodiment of the present application method is realized in the form of SFU software functional unit and as independent production
Product are sold or in use, can be stored in a computing device read/write memory medium.Based on this understanding, the application is real
Applying the part of a part that contributes to existing technology or the technical solution can be expressed in the form of software products,
The software product is stored in a storage medium, including some instructions are used so that a computing device (can be personal meter
Calculation machine, server, mobile computing device or network equipment etc.) execute each embodiment the method for the application whole or portion
Step by step.And storage medium above-mentioned includes：USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), with
Machine accesses various Jie that can store program code such as memory (RAM, Random Access Memory), magnetic disc or CD
Matter.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with it is other
The difference of embodiment, just to refer each other for same or similar part between each embodiment.
The foregoing description of the disclosed embodiments enables professional and technical personnel in the field to realize or use the application.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can in other embodiments be realized in the case where not departing from spirit herein or range.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (8)
1. a kind of coarse-grained reconfigurable array, which is characterized in that including：
10 reconfigurable processing unit BPU；
It is interconnected by connector CB between adjacent each BPU, is not connected with CB with the terminal of other BPU interconnection in each BPU
It connects；It is interconnected by two-way interconnection structure switch enclosure SB between each CB；
The BPU includes：Reconfigurable processor BP；
The BP includes：The input of restructural crypto-operation element RCE, each RCE come from input interference networks, the fortune of each RCE
Result is calculated by exporting interference networks output.
2. coarse-grained reconfigurable array according to claim 1, which is characterized in that the BPU further includes：
Reconfigurable S-box unit B PU_S and restructural key storing unit BPU_K；
Between adjacent each BPU by connector CB be interconnected including：
It is carried out mutually between each BP, BP and BPU_S, between BP and BPU_K and by connector CB between BPU_S and BPU_K
Even.
3. coarse-grained reconfigurable array according to claim 2, which is characterized in that the BPU is distributed as two rows, wherein
The first row includes BPU_S and four BP, and the second row includes BPU_K and four BP.
4. coarse-grained reconfigurable array according to claim 3, which is characterized in that
The basic handling granularity of any one BP is 32 bits, and the processing granularity with the BP in a line is 128 bits；
BPU_S in the first row by long line with its be expert at and rear a line in eight BP connect, and receive and come from
The data of adjacent C B, for realizing S box operations；
BPU_K in second row by long line with its be expert at and previous row in eight BP connect, and receive from adjacent
The data of CB, for realizing the storage and distribution for key.
5. according to claim 1-4 any one of them coarse-grained reconfigurable arrays, which is characterized in that the BP includes：
Restructural crypto-operation element RCE, input interference networks and output interference networks, input interference networks and described defeated
Go out interference networks and uses the totally interconnected structure designs of Crossbar.
6. coarse-grained reconfigurable array according to claim 5, which is characterized in that the RCE includes：
The restructural crypto-operation element RCE_AL of arithmetic class, for realizing the calculation in the restructural cryptologic array of the coarseness
Art class operation；
The restructural crypto-operation element RCE_BP of class is replaced, for realizing setting in the restructural cryptologic array of the coarseness
Change class operation；
The restructural crypto-operation element RCE_LG of logic class, for realizing patrolling in the restructural cryptologic array of the coarseness
Collect class operation；
The non-linear restructural crypto-operation element RCE_NF of class, for realizing in the restructural cryptologic array of the coarseness
Non-linear class operation.
7. coarse-grained reconfigurable array according to claim 5, which is characterized in that the RCE is by can bypass register
It is connected with the output interference networks；
The operation result of the RCE bypass register deposit or can not deposit after level-one output to output interconnection by described
Network.
8. a kind of coarse-grained reconfigurable array, which is characterized in that including：
At least two coarse-grained reconfigurable arrays described in claim 1, adjacent coarseness described in claim 1 are restructural
Each BPU between array is interconnected by connector CB.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034920A (en) * | 2019-04-09 | 2019-07-19 | 中国人民解放军战略支援部队信息工程大学 | The mapping method and device of the restructural cryptologic array of coarseness |
| CN111158636A (en) * | 2019-12-03 | 2020-05-15 | 中国人民解放军战略支援部队信息工程大学 | Reconfigurable computing structure and routing addressing method and device of multiply-accumulate computing processing array |
| CN113129961A (en) * | 2021-04-21 | 2021-07-16 | 中国人民解放军战略支援部队信息工程大学 | Configuration circuit for local dynamic reconstruction of cipher logic array |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100357884C (en) * | 2004-10-14 | 2007-12-26 | 国际商业机器公司 | Method, processor and system for processing instructions |
| CN105912501A (en) * | 2016-05-06 | 2016-08-31 | 东南大学—无锡集成电路技术研究所 | SM4-128 encryption algorithm implementation method and system based on large-scale coarseness reconfigurable processor |
-
2018
- 2018-03-01 CN CN201810171213.9A patent/CN108400866B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100357884C (en) * | 2004-10-14 | 2007-12-26 | 国际商业机器公司 | Method, processor and system for processing instructions |
| CN105912501A (en) * | 2016-05-06 | 2016-08-31 | 东南大学—无锡集成电路技术研究所 | SM4-128 encryption algorithm implementation method and system based on large-scale coarseness reconfigurable processor |
Non-Patent Citations (6)
| Title |
|---|
| BIN LIU等: ""Parallel AES Encryption Engines for Many-Core Processor Arrays"", 《IEEE》 * |
| 冯晓等: ""面向分组密码的可重构异构多核并行处理架构"", 《电子学报》 * |
| 李伟等: ""A High Energy-Efficient Reconfigurable VLIW Symmetric Cryptographic Processor with Loop Buffer Structure and Chain Processing Mechanism"", 《IEEE》 * |
| 杨晓辉: "面向分组密码处理的可重构设计技术研究", 《中国优秀硕士学位论文全文数据库，信息科技辑》 * |
| 赵宗国等: ""基于3D-Mesh互连网络的粗粒度逻辑阵列研究"", 《电子技术应用》 * |
| 陈韬等: ""一种基于流处理框架的可重构分簇式分组密码处理结构模型"", 《电子与信息学报》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110034920A (en) * | 2019-04-09 | 2019-07-19 | 中国人民解放军战略支援部队信息工程大学 | The mapping method and device of the restructural cryptologic array of coarseness |
| CN111158636A (en) * | 2019-12-03 | 2020-05-15 | 中国人民解放军战略支援部队信息工程大学 | Reconfigurable computing structure and routing addressing method and device of multiply-accumulate computing processing array |
| CN111158636B (en) * | 2019-12-03 | 2022-04-05 | 中国人民解放军战略支援部队信息工程大学 | Reconfigurable computing structure and routing addressing method and device of computing processing array |
| CN113129961A (en) * | 2021-04-21 | 2021-07-16 | 中国人民解放军战略支援部队信息工程大学 | Configuration circuit for local dynamic reconstruction of cipher logic array |
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|---|---|
| CN108400866B (en) | 2021-02-02 |
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