CN113258928B - Delay phase locking system and method based on digital pre-adjustment - Google Patents
Delay phase locking system and method based on digital pre-adjustment Download PDFInfo
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Abstract
The invention discloses a digital pre-regulation based delay phase-locked system, which comprises a delay phase-locked module, a digital pre-regulation module and a starting module, wherein the delay phase-locked module comprises a delay unit, the voltage of the input end of the delay unit is the starting voltage generated by the starting module during starting, the delay unit and the digital pre-regulation module form a feedback loop, the digital pre-regulation module generates a regulation code for regulating the delay unit according to the phase difference between a system input clock signal and a system output feedback signal, and the delay unit closes the digital pre-regulation module and the starting module after working at an optimal working point under the regulation of the regulation code, so that the delay phase-locked module enters a delay phase-locked loop working mode. The invention adjusts the delay unit according to the frequency of the input clock signal and the manufacturing process condition of the circuit, thereby eliminating the influence of the factors on the delay phase-locked loop; meanwhile, as the delay unit always works near the optimal working point, the delay range provided by the delay unit can be limited, so that harmonic locking cannot be generated.
Description
Technical Field
The invention relates to the technical field of delay-locked loops, in particular to a digital pre-adjustment based delay-locked loop system and a digital pre-adjustment based delay-locked loop method.
Background
A delay locked loop circuit is one of circuits frequently used for a clock source portion in an integrated circuit, and outputs an input clock signal with a delay of one cycle after passing through a delay unit, thereby obtaining a plurality of clock signals having a fixed phase difference between the input clock signal and an output clock signal. The most commonly used delay-locked loop circuit in chips today is the charge pump delay-locked loop structure. This type of circuit suffers from several disadvantages: 1. the input range is limited, and the delay unit can only work in the range of half to twice of the designed delay value; 2. the influence of process variation is large, and the typical delay difference of the delay unit under the fast and slow process conditions is large; 3. harmonic locking conditions are prone to occur, causing systematic errors.
Disclosure of Invention
The invention aims to provide a delay phase locking system and method based on digital pre-adjustment.
The technical scheme adopted by the invention is as follows: constructing a digital pre-regulation based delay phase-locked system, which comprises a delay phase-locked module, a digital pre-regulation module and a starting module, wherein the delay phase-locked module comprises a delay unit, the input end of the digital pre-regulation module is connected to a system input clock signal and a system output feedback signal, and the output end of the digital pre-regulation module is connected to the control end of the delay unit; the starting module is connected to the input end of the delay unit, the output end of the delay unit outputs the system output feedback signal, when the delay unit is started, the voltage of the input end of the delay unit is the starting voltage generated by the starting module, the delay unit and the digital pre-adjusting module form a feedback loop under the control of the starting voltage, the digital pre-adjusting module generates an adjusting code for adjusting the delay unit according to the phase difference between a system input clock signal and the system output feedback signal, and the delay unit works at an optimal working point under the adjustment of the adjusting code and then closes the digital pre-adjusting module and the starting module, so that the delay phase-locked loop module enters a delay phase-locked loop working mode.
In the delay phase-locked system based on digital preconditioning provided by the invention, the digital preconditioning module comprises a digital phase discriminator and a successive comparison logic, wherein the input end of the digital phase discriminator circuit is connected to a system input clock signal and a system output feedback signal; the reset end of the digital phase discriminator circuit is connected with the reset output end of the successive comparison logic; the output end of the digital phase discriminator circuit is connected to the input end of the successive comparison logic; the output end of the successive comparison logic is connected with the control end of the delay unit; the digital phase discriminator generates a stepping signal, a data signal and an end signal according to the phase difference of a system input clock signal and a system output feedback signal; the successive comparison logic determines each bit of the adjustment code in turn based on the step signal, the data signal, and the end signal.
In the delay phase-locked system based on digital preconditioning provided by the invention, the digital preconditioning module comprises a digital phase discriminator and a successive comparison logic, wherein the input end of the digital phase discriminator circuit is connected to a system input clock signal and a system output feedback signal; the reset end of the digital phase discriminator circuit is connected with the reset output end of the successive comparison logic; the output end of the digital phase discriminator circuit is connected to the input end of the successive comparison logic; and the output end of the successive comparison logic is connected with the control end of the delay unit.
In the digital pre-adjustment based delay phase locking system provided by the invention, the digital phase discriminator circuit comprises a first trigger, a second trigger, a third trigger, a fourth trigger, a fifth trigger, a sixth trigger, a first OR gate, a second OR gate, a NOR gate, a phase inverter, a first delay unit, a second delay unit and a four-frequency-division circuit; the input end of the first trigger is connected with a power supply, the clock end of the first trigger is connected with a system input clock signal, the reset end of the first trigger is connected with the reset end of the digital phase discriminator, and the output end of the first trigger is connected with the input ends of the second trigger and the fourth trigger; a clock end of the second trigger is connected with a system input clock signal, a reset end of the second trigger is connected with an output end of the first OR gate, and an output end of the second trigger is connected with an input end of the first delay unit; the input end of the third trigger is connected with the output end of the first delay unit, the clock end of the third trigger is connected with a system input clock signal, the reset end of the third trigger is connected with the reset end of the digital phase discriminator, and the output end of the third trigger is connected with the input end of the nor gate; a clock end of the fourth trigger is connected with a system output feedback signal, a reset end of the fourth trigger is connected with an output end of the second or gate, and an output end of the fourth trigger is connected with an input end of the second delay unit; the input end of the fifth trigger is connected with the output end of the second delay unit, the clock end of the fifth trigger is connected with a system input clock signal, the reset end of the fifth trigger is connected with the reset end of the digital phase discriminator, and the output end of the fifth trigger is connected with the input end of the nor gate; the input end of the sixth trigger is connected with the output end of the nor gate, the clock end of the sixth trigger is connected with the output end of the quarter-frequency circuit, and the reset end of the sixth trigger is connected with the reset end of the digital phase discriminator; the input end of the first or gate is respectively connected with the output end of the second delay unit and the reset end of the digital phase discriminator, and the output end of the first or gate is connected with the reset end of the second trigger; the input end of the second or gate is respectively connected with the output end of the first delay unit and the reset end of the digital phase discriminator, and the output end of the second or gate is connected with the reset end of the fourth trigger; the input end of the inverter is connected with the output end of the NOR gate; the input end of the four-frequency-division circuit is connected with a system input clock signal, and the output end of the four-frequency-division circuit is connected with the clock end of the sixth trigger.
In the digital pre-conditioning based delay phase-locked system provided by the invention, the delay phase-locked system further comprises a switch connected between the starting module and the delay unit.
In the digital pre-adjustment based delay phase-locked system provided by the invention, the starting voltage is one half of the power supply voltage.
According to another aspect of the present invention, there is also provided a delay locking method according to the digital pre-conditioning based delay locking system as described above, comprising the steps of:
the delay unit, the digital pre-adjusting module and the starting module of the delay phase locking module are activated;
under the control of the starting voltage generated by the starting module, the delay unit generates a system output feedback signal;
the digital pre-adjusting module generates adjusting codes for adjusting the delay units according to the phase difference of a system input clock signal and a system output feedback signal; and
and the delay unit works at an optimal working point under the regulation of the regulation code and then closes the digital pre-regulation module and the starting module, so that the delay phase-locked module enters a delay phase-locked loop working mode.
In the delay phase locking method provided by the present invention, the step of generating the adjusting code for adjusting the delay unit by the digital pre-adjusting module according to the phase difference between the system input clock signal and the system output feedback signal comprises:
the digital phase discriminator generates a stepping signal, a data signal and an end signal according to the phase difference of a system input clock signal and a system output feedback signal;
the successive comparison logic determines each bit of the adjustment code in turn based on the step signal, the data signal, and the end signal.
The delay phase locking system and method based on digital pre-adjustment have the following beneficial effects: when the delay phase-locked system based on digital preconditioning provided by the invention works, the digital preconditioning module, the delay unit and the starting module are activated firstly; the voltage of the input end of the delay unit is the starting voltage generated by the starting module, and is generally one half of the power supply voltage; thus, the delay unit and the digital pre-regulation module form a feedback loop under the condition of fixed control voltage; the digital pre-adjusting module changes the configuration code output to the delay unit according to the phase difference of the system input clock signal and the system output feedback signal so as to adjust the working point, the delay range and the like of the delay unit and enable the delay unit to work in the optimal state; and then the digital pre-regulation module and the starting module are closed, and the phase discriminator and the charge pump are activated to convert into a classical delay phase-locked loop working mode. The invention can adjust the delay unit according to the frequency of the input clock signal and the manufacturing process condition of the circuit, thereby eliminating the influence of the factors on the delay phase-locked loop; meanwhile, as the delay unit under each specific configuration code always works near the optimal working point, the delay range provided by the delay unit can be limited, and harmonic locking can not be generated.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
fig. 1 is an overall connection diagram of a digital pre-conditioning based delay phase locking system provided by the invention;
FIG. 2 is a connection diagram of the digital pre-conditioning module shown in FIG. 1;
fig. 3 is a connection diagram of the digital phase detector shown in fig. 2;
fig. 4 is a signal timing diagram of the digital pre-conditioning module shown in fig. 1.
The digital phase detector comprises a 1-digital pre-adjusting module, a 2-starting module, a 3-phase detector, a 4-charge pump, a 5-delay unit, a 6-filter capacitor, a 7-switch, an 11-digital phase detector, 12-successive comparison logic, 101-a first trigger, 102-a second trigger, 103-a third trigger, 104-a fourth trigger, 105-a fifth trigger, 106-a sixth trigger, 201-a first OR gate, 202-a second OR gate, 203-a NOR gate, 204-an inverter, 301-a first delay unit, 302-a second delay unit and 303-a four-frequency-division circuit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a delay locked loop circuit using a digital pre-adjustment technology, which solves a series of problems of small input range, large influence of process, easy harmonic locking and the like in the existing circuit.
Fig. 1 is an overall connection diagram of a digital preconditioning based delay phase-locked system provided by the invention. As shown in fig. 1, the digital pre-conditioning based delay phase locking system provided by the present invention includes a delay phase locking module, a digital pre-conditioning module 1 and a start-up module 2. The delay phase-locked module adopts a classical delay phase-locked loop circuit and comprises a phase discriminator 3, a charge pump 4, a delay unit 5 and a filter capacitor 6. A switch 7 is connected between the start module 2 and the delay unit 5. A system input clock signal (CLKIN) and a system output feedback signal (CLKO) are connected with the input end of the phase detector 3; the phase detector 3 compares the phase difference of CLKIN and CLKO to generate its UP (hereinafter UP) and down (hereinafter DN) output signals; UP and DN signals are connected with the input end of the charge pump 4; the charge pump 4 controls the output control voltage (hereinafter referred to as VCTRL) to increase or decrease according to the value of UP or DN; VCTRL is connected to the input control end of the delay unit 5 after being filtered by the filter capacitor 6; the delay control unit 5 changes its delay time according to the VCTRL voltage value, thereby changing the phase of the CLKO signal; the CLKO signal is feedback connected to the input of the phase detector 3, and the system forms a feedback loop. The digital pre-regulation module 1, the starting module 2 and the switch 7 form a digital pre-regulation loop: the CLKIN and CLKO signals are connected to the input of the digital pre-conditioning module 1; the digital pre-adjusting module 1 generates a control CODE (hereinafter, referred to as CODE) according to the phase difference between CLKIN and CLKO; the CODE is connected to the control terminal of the delay unit 5; the delay unit 5 adjusts its delay time according to the change of CODE, thereby changing the phase of the CLKO signal; the CLKO signal is feedback connected to the input of the digital pre-conditioning module 1, the system forming a feedback loop.
When the delay phase-locked system based on digital preconditioning provided by the invention works, the digital preconditioning module, the delay unit and the starting module are activated firstly; the voltage of the input end of the delay unit is the starting voltage generated by the starting module, and is generally one half of the power supply voltage; thus, the delay unit and the digital pre-regulation module form a feedback loop under the condition of fixed control voltage; the digital pre-adjusting module changes the configuration code output to the delay unit according to the phase difference of the system input clock signal and the system output feedback signal so as to adjust the working point, the delay range and the like of the delay unit and enable the delay unit to work in the optimal state; and then the digital pre-regulation module and the starting module are closed, and the phase discriminator and the charge pump are activated to convert into a classical delay phase-locked loop working mode. The invention can adjust the delay unit according to the frequency of the input clock signal and the manufacturing process condition of the circuit, thereby eliminating the influence of the factors on the delay phase-locked loop; meanwhile, as the delay unit under each specific configuration code always works near the optimal working point, the delay range provided by the delay unit can be limited, and harmonic locking can not be generated.
FIG. 2 is a connection diagram of the digital pre-conditioning module shown in FIG. 1; as shown in fig. 2, the digital pre-conditioning module includes a digital phase detector 11 and successive comparison logic 12; the CLKIN and CLKO are connected to an input terminal of the digital phase detector 11, and the digital phase detector 11 generates a STEP signal (hereinafter referred to as STEP), a DATA signal (hereinafter referred to as DATA) and an END signal (hereinafter referred to as END) according to a phase difference of the CLKIN and CLKO; the STEP, DATA, and END signals are connected to the inputs of successive comparison logic 12; the successive comparison logic 12 determines each bit CODE value (logic "1" or "0") in sequence according to the signal values of STEP, DATA and END, and returns a reset signal (hereinafter referred to as RST) after determining each bit CODE value, and the reset signal RST is connected to the reset END of the digital phase discriminator 11; the digital pre-conditioning module ENDs operation when the CODE values are all asserted, or the END signal is a logic "1".
Fig. 3 is a connection diagram of the digital phase detector shown in fig. 2; fig. 4 is a signal timing diagram of the digital pre-conditioning module shown in fig. 1. As shown in fig. 3, the digital phase detector includes a first flip-flop 101, a second flip-flop 102, a third flip-flop 103, a fourth flip-flop 104, a fifth flip-flop 105, a sixth flip-flop 106, a first or gate 201, a second or gate 202, a nor gate 203, an inverter 204, a first delay unit 301, a second delay unit 302, and a quarter-frequency circuit 303. The phase discrimination process is as follows:
after the first rising edge of CLKIN, the first flip-flop 101 transmits a logic "1" at the input to the output, i.e., the inputs of the second flip-flop 102 and the fourth flip-flop 104; the second flip-flop 102, the first delay unit 301 and the third flip-flop 103 form an input signal chain; after the second rising edge and the third rising edge of CLKIN, the logic '1' is respectively transmitted to the output ends of the second trigger and the third trigger to complete the input signal chain transmission;
the fourth flip-flop 104, the second delay unit 302 and the fifth flip-flop 105 form an output signal chain; after the first rising edge of CLKO and the third rising edge of CLKIN, the logic '1' will be transmitted to the output ends of the fourth and fifth flip-flops respectively, thus completing the transmission of the output signal chain;
when the first rising edge of CLKO lags the second rising edge of CLKIN, the input signal chain may complete the transmission, while the fourth flip-flop 104 is reset by the second or gate 202 to cut off the output signal transmission chain when the logic "1" is transmitted to the first delay cell 301;
when the first rising edge of CLKO leads the second rising edge of CLKIN, the output signal chain may complete the transmission, while the second flip-flop 102 is reset by the first or gate 201 to cut off the input signal transmission chain when the logic "1" is transmitted to the second delay cell 302;
when the transmission of the input signal chain or the output signal chain is completed, a logic "1" is transmitted to one input end of the nor gate 203, so that the output end thereof is a logic "0", and a STEP signal of a logic "1" is output through the inverter 204;
the output value of the third flip-flop 103 is output as a DATA signal, where DATA outputs a logic "1" when the input signal chain completes transmission, and DATA outputs a logic "0" when the output signal chain completes transmission;
when the STEP signal outputs a logic "1", that is, the CLKIN rises for the third time, the successive comparison logic 12 in fig. 2 reads the DATA value and returns a logic "1" pulse of the RST to reset the digital phase detector 11 for the next phase detection; each phase discrimination will cause successive comparison logic 12 to determine a one-bit CODE; the digital preconditioning process ends after the CODE CODEs are all determined.
Particularly, when the phase difference between CLKIN and CLKO is smaller than the delay time of the first delay unit 301 or the second delay unit 302, a logic "1" is transmitted to the outputs of the first delay unit and the second delay unit in sequence, so that the first or gate 201 and the second or gate 202 output a logic "1", the second flip-flop 102 and the fourth flip-flop 104 are reset at the same time, and the input signal chain and the output signal chain are all cut off; in this case, the STEP signal is still logic "0" when the third rising edge of the CLKIN signal arrives, and the phase discrimination will continue; the fourth rising edge of the CLKIN signal will cause the output of the divide-by-four circuit 303 to appear as a rising edge that is transmitted to the clock terminal of the sixth flip-flop 106; the input terminal of the sixth flip-flop 106 is all logic "0", and thus logic "1" appears, and this logic "1" is transmitted to the output terminal of the sixth flip-flop 106 and is output to the successive comparison logic 12 in fig. 2 as an END signal, so that the digital pre-adjustment process is terminated early, and at this time, the CODE value output by the successive comparison logic 12 is the final value.
The working process of the delay phase-locking system based on digital pre-adjustment provided by the invention is as follows:
1) firstly, when a system is started, firstly, a digital pre-conditioning module 1, a starting module 2 and a delay unit 5 are activated; the switch 7 is in a closed state, so that the starting voltage output by the starting module is clamped to VCTRL, and the general clamping voltage is one half of the power supply voltage; the VCTRL voltage and the initial CODE value (generally, the intermediate value, i.e., the highest bit is logic "1", and the other bits are logic "0") control the delay of the delay unit, so that the output of the delay unit is a signal CLKO having a certain phase difference with CLKIN; the CLKIN and CLKO signals are used as input to be accessed into a digital pre-adjusting module 1; the digital pre-adjusting module 1 adjusts and outputs CODE according to the phase difference; the system is in a digital preconditioning mode.
2) With reference to fig. 2, 3 and 4, the whole digital preconditioning mode will be described by taking a three-bit CODE as an example; three bits of CODE are given an initial value of 100, and three times of phase discrimination are needed to determine all CODE values; as shown in fig. 4, the first rising edge of CLKO leads the second rising edge of CLKIN at the first phase-check; when CLKIN rises for the third time, the output signal chain composed of the fourth flip-flop 104, the second delay unit 302, and the fifth flip-flop 105 in fig. 3 completes transmission, so that the STEP signal is logic "1" and the DATA signal is logic "0"; in fig. 2, after receiving the STEP signal "1", the successive comparison logic 12 determines that the CODE initial value "100" is higher according to the DATA value "0", modifies it to "010", and returns the RST pulse to reset the digital phase detector 11 to start the second phase detection; the first rising edge of CLKO lags the second rising edge of CLKIN during the second phase-identifying; at the third rising edge of CLKIN, the input signal chain composed of the second flip-flop 101, the first delay unit 301, and the third flip-flop 103 in fig. 3 completes transmission, so that the STEP signal is logic "1", and the DATA signal is logic "1"; in fig. 2, after receiving the STEP signal "1", the successive comparison logic 12 determines that the CODE value "010" is low according to the DATA value "1", modifies it to "011", and returns the RST pulse to reset the digital phase detector 11 to start phase detection for the third time; the first rising edge of CLKO leads the second rising edge of CLKIN during the third phase-identifying; when CLKIN rises for the third time, the output signal chain composed of the fourth flip-flop 104, the second delay unit 302, and the fifth flip-flop 105 in fig. 3 completes transmission, so that the STEP signal is logic "1" and the DATA signal is logic "0"; after receiving the STEP signal "1", the successive comparison logic 12 in fig. 2 determines that the CODE value "011" is higher according to the DATA value "0", and modifies it to "010", until all three-bit CODE CODEs are determined, and the digital pre-adjustment process is finished. Specifically, if the phase difference between CLKIN and CLKO is smaller than the delay time of the first delay unit 301 (or the second delay unit 302) in a certain phase detection, both the input signal chain and the output signal chain in the digital phase detector 11 are reset and cannot complete transmission; at the third rising edge of CLKIN, the STEP signal is still "0", and the phase discrimination continues; at the fourth rising edge of CLKIN, the digital phase detector 11 sends out an END signal of "1" through the internal quarter-frequency circuit 303 and the sixth flip-flop 106, thereby ending the digital preconditioning process early.
3) After the digital pre-adjusting process is finished, the system enters a classic delay phase-locked loop working mode; as shown in fig. 1, the digital pre-conditioning module 1 and the starting module 2 are closed, and the switch 7 is opened; the phase discriminator 3, the charge pump 4 and the delay unit 5 are activated; wherein the delay unit 5 has been given a specific CODE to be in an optimal operating state during digital preconditioning based on the frequency of the input signal and the manufacturing process of the circuit; the control voltage is given to the initial voltage held by the filter capacitor, typically one-half of the supply voltage; the delay unit 5 can output the CLKO signal having a phase difference close to one cycle from the CLKIN in this state; the phase detector 3 adjusts UP and DN signals through phase discrimination of the CLKIN and the CLKO and controls the charge pump 4; because the phase difference is already close to the target value, the charge pump 4 only needs a short time to adjust the voltage of VCTRL to the final value (very close to the initial voltage), so that the delay locked loop locks.
4) If the frequency of the input clock signal CLKIN needs to be changed, the delay locked loop circuit is reset, and the above steps are repeated.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (6)
1. The digital pre-regulation based delay phase-locked system is characterized by comprising a delay phase-locked module, a digital pre-regulation module and a starting module, wherein the delay phase-locked module comprises a delay unit, the input end of the digital pre-regulation module is connected to a system input clock signal and a system output feedback signal, and the output end of the digital pre-regulation module is connected to the control end of the delay unit; the starting module is connected to the input end of the delay unit, the output end of the delay unit outputs the system output feedback signal, when the delay unit is started, the voltage of the input end of the delay unit is the starting voltage generated by the starting module, the delay unit and the digital pre-adjusting module form a feedback loop under the control of the starting voltage, the digital pre-adjusting module generates an adjusting code for adjusting the delay unit according to the phase difference of a system input clock signal and the system output feedback signal, and the delay unit closes the digital pre-adjusting module and the starting module after working at an optimal working point under the adjustment of the adjusting code, so that the delay phase-locked loop module enters a delay phase-locked loop working mode; the digital preconditioning module comprises a digital phase discriminator and a successive comparison logic, wherein the input end of the digital phase discriminator circuit is connected to a system input clock signal and a system output feedback signal; the reset end of the digital phase discriminator circuit is connected with the reset output end of the successive comparison logic; the output end of the digital phase discriminator circuit is connected to the input end of the successive comparison logic; the output end of the successive comparison logic is connected with the control end of the delay unit; the digital phase discriminator generates a stepping signal, a data signal and an end signal according to the phase difference of a system input clock signal and a system output feedback signal; the successive comparison logic determines each bit of the adjustment code in turn based on the step signal, the data signal, and the end signal.
2. The digital preconditioning-based delay phase-locked system of claim 1, wherein the delay phase-locked module further comprises a phase detector, a charge pump and a filter capacitor, wherein an input terminal of the phase detector is connected to a system input clock signal and a system output feedback signal, and an output terminal of the phase detector is connected to the input terminal of the charge pump; the output end of the charge pump is simultaneously connected to the anode of the filter capacitor and the input end of the delay unit; the negative electrode of the filter capacitor is grounded; the output end of the delay unit is also connected with the input end of the phase discriminator.
3. The digital pre-conditioning based delay phase locking system according to claim 1, wherein the digital phase detector circuit comprises a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, a first or gate, a second or gate, a nor gate, an inverter, a first delay unit, a second delay unit and a four-frequency divider circuit; the input end of the first trigger is connected with a power supply, the clock end of the first trigger is connected with a system input clock signal, the reset end of the first trigger is connected with the reset end of the digital phase discriminator, and the output end of the first trigger is connected with the input ends of the second trigger and the fourth trigger; a clock end of the second trigger is connected with a system input clock signal, a reset end of the second trigger is connected with an output end of the first OR gate, and an output end of the second trigger is connected with an input end of the first delay unit; the input end of the third trigger is connected with the output end of the first delay unit, the clock end of the third trigger is connected with a system input clock signal, the reset end of the third trigger is connected with the reset end of the digital phase discriminator, and the output end of the third trigger is connected with the input end of the nor gate; a clock end of the fourth trigger is connected with a system output feedback signal, a reset end of the fourth trigger is connected with an output end of the second or gate, and an output end of the fourth trigger is connected with an input end of the second delay unit; the input end of the fifth trigger is connected with the output end of the second delay unit, the clock end of the fifth trigger is connected with a system input clock signal, the reset end of the fifth trigger is connected with the reset end of the digital phase discriminator, and the output end of the fifth trigger is connected with the input end of the nor gate; the input end of the sixth trigger is connected with the output end of the nor gate, the clock end of the sixth trigger is connected with the output end of the quarter-frequency circuit, and the reset end of the sixth trigger is connected with the reset end of the digital phase discriminator; the input end of the first or gate is respectively connected with the output end of the second delay unit and the reset end of the digital phase discriminator, and the output end of the first or gate is connected with the reset end of the second trigger; the input end of the second or gate is respectively connected with the output end of the first delay unit and the reset end of the digital phase discriminator, and the output end of the second or gate is connected with the reset end of the fourth trigger; the input end of the inverter is connected with the output end of the NOR gate; the input end of the four-frequency-division circuit is connected with a system input clock signal, and the output end of the four-frequency-division circuit is connected with the clock end of the sixth trigger.
4. The digital preconditioning-based delay locked phase system of claim 1, further comprising a switch connected between the startup module and the delay cell.
5. The digital preconditioning-based delay locked phase system of claim 1, wherein the startup voltage is one-half of a supply voltage.
6. A delay locking method of a delay locking system based on digital pre-adjustment according to any one of claims 1-5, characterized by comprising the following steps:
the delay unit, the digital pre-adjusting module and the starting module of the delay phase locking module are activated;
under the control of the starting voltage generated by the starting module, the delay unit generates a system output feedback signal;
the digital pre-adjusting module generates adjusting codes for adjusting the delay units according to the phase difference of a system input clock signal and a system output feedback signal; and
the delay unit works at an optimal working point under the regulation of the regulation code, and then the digital pre-regulation module and the starting module are closed, so that the delay phase-locked module enters a delay phase-locked loop working mode;
the step of the digital pre-conditioning module generating conditioning codes for conditioning the delay cells based on a phase difference of a system input clock signal and a system output feedback signal comprises:
the digital phase discriminator generates a stepping signal, a data signal and an ending signal according to the phase difference of a system input clock signal and a system output feedback signal;
the successive comparison logic determines each bit of the adjustment code in turn based on the step signal, the data signal, and the end signal.
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