CN113257881A

CN113257881A - Display substrate and display device

Info

Publication number: CN113257881A
Application number: CN202110742219.9A
Authority: CN
Inventors: 龙春平; 李盼
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2021-08-13
Anticipated expiration: 2041-07-01
Also published as: CN113257881B

Abstract

The disclosure provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a substrate, a first conducting layer, an insulating layer and a second conducting layer which are sequentially stacked, wherein the first conducting layer and the second conducting layer can be overlapped through a through hole penetrating through the insulating layer. Because the side wall of the via hole extends in a stepped manner along the direction far away from the substrate base plate, at least part of the side wall is an arc surface with a tangent line intersected with the substrate base plate, and the size of the opening of the via hole close to the substrate base plate side is smaller than that of the opening far away from the substrate base plate side, the gradient of the side wall of the via hole is gentle. Furthermore, the first conductive layer and the second conductive layer are in lap joint, and good product yield is ensured.

Description

Display substrate and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

An organic light-emitting diode (OLED) display substrate is widely used in various display devices due to its advantages of self-luminescence, small thickness, light weight, high luminous efficiency, and the like.

In the related art, the OLED display substrate generally includes: the substrate comprises a substrate base plate, a first conducting layer, an insulating layer and a second conducting layer, wherein the first conducting layer, the insulating layer and the second conducting layer are sequentially stacked on one side of the substrate base plate, and the first conducting layer is in lap joint with the second conducting layer through a through hole penetrating through the insulating layer. And, the cross-section of the via is generally rectangular.

However, since the cross section of the via hole in the related art is rectangular, the slope of the sidewall of the via hole is steep, which is not favorable for the overlapping of the first conductive layer and the second conductive layer, thereby affecting the yield of the product.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate and a display device, which can solve the problem that the product yield is influenced because the slope of the side wall of a via hole is steep and the first conducting layer and the second conducting layer are not in lap joint in the related technology. The technical scheme is as follows.

In one aspect, a display substrate is provided, the display substrate including:

a substrate base plate;

the first conducting layer, the insulating layer and the second conducting layer are positioned on one side of the substrate base plate and are sequentially stacked;

the second conducting layer is electrically connected with the first conducting layer through the through hole;

the side wall of the through hole extends in a stepped manner along the direction away from the substrate base plate, at least part of the side wall of the through hole is an arc surface, the tangent line of the arc surface is intersected with the substrate base plate, the through hole is close to the orthographic projection of the opening on one side of the substrate base plate on the substrate base plate, and the through hole is located in the orthographic projection of the opening on one side of the substrate base plate on the substrate base plate.

Optionally, the arc surface is convex towards a direction close to the second conductive layer.

Optionally, the insulating layer includes: at least two sub-insulating layers sequentially stacked along a direction far away from the substrate base plate;

the via hole includes: and the sub-via holes are communicated with each other and penetrate through each layer of the sub-insulating layer.

Optionally, the insulating layer includes: the first sub-insulating layer, the second sub-insulating layer and the third sub-insulating layer are sequentially stacked along the direction far away from the substrate base plate;

the via hole includes: the first sub-via hole, the second sub-via hole and the third sub-via hole are communicated with each other and penetrate through the first sub-insulating layer, the second sub-via hole and the third sub-via hole.

Optionally, the aperture of the first sub-via hole, the aperture of the second sub-via hole, and the aperture of the third sub-via hole are sequentially increased.

Optionally, in the sidewall of the second sub-via and the third sub-via, a sidewall of at least one sub-via is an arc surface.

Optionally, any cross section of the first sub-via hole is rectangular.

Optionally, a first cross section of the first sub via hole is rectangular, a second cross section of the first sub via hole is polygonal, and the first cross section is perpendicular to the second cross section;

wherein the polygon comprises first and second opposing sides, and third and fourth opposing sides; the first edge is connected with the third edge, the second edge is connected with the fourth edge, the first edge and the second edge are perpendicular to the substrate base plate, the third edge is perpendicular to the included angle of the substrate base plate, and the fourth edge is perpendicular to the included angle of the substrate base plate.

Optionally, the length of the orthographic projection of the third edge on the substrate base plate and the length of the orthographic projection of the fourth edge on the substrate base plate are both greater than or equal to 1 micrometer, and the first direction is parallel to the second cross section;

the distance between the connecting point of the third edge and the first conductive layer and the distance between the connecting point of the fourth edge and the second edge and the first conductive layer are both less than or equal to 1 micrometer;

and the included angle between the third edge and the first conducting layer and the included angle between the fourth edge and the first conducting layer are both smaller than 30 degrees.

Optionally, the length of the orthographic projection of the third edge on the substrate base plate and the length of the orthographic projection of the fourth edge on the substrate base plate are both greater than or equal to 1.5 micrometers, and the first direction is parallel to the second cross section;

the distance between the connecting point of the third edge and the first conductive layer and the distance between the connecting point of the fourth edge and the second edge and the first conductive layer are both less than or equal to 0.5 micrometer;

and the included angle between the third edge and the first conducting layer and the included angle between the fourth edge and the first conducting layer are both smaller than 20 degrees.

Optionally, the length of an orthographic projection of the third edge on the substrate base plate and the length of an orthographic projection of the fourth edge on the substrate base plate are both less than or equal to 2 micrometers, and the first direction is parallel to the second cross section;

the distance between the connecting point of the third edge and the first conductive layer and the distance between the connecting point of the fourth edge and the second edge and the first conductive layer are both less than or equal to 0.4 micrometer;

and the included angle between the third edge and the first conducting layer and the included angle between the fourth edge and the first conducting layer are both smaller than 15 degrees.

Optionally, the display substrate further includes: and the third conducting layer is positioned on one side of the first conducting layer, which is far away from the substrate base plate, and covers part or all of the side wall of the through hole.

Optionally, the sidewall of the via hole includes a first portion and a second portion oppositely arranged in a first direction, and a third portion and a fourth portion oppositely arranged in a second direction, and the first direction is perpendicular to the second direction;

wherein the third conductive layer covers the first and second portions of the sidewalls of the via.

Optionally, the third conductive layer further covers a third portion and a fourth portion of the sidewall of the via.

Optionally, the third conductive layer covers a sidewall of the second sub-via and a partial sidewall of the third sub-via included in the via.

Optionally, the third conductive layer further covers the first conductive layer.

the third conductive layer comprises a first conductive pattern and a second conductive pattern, the first conductive pattern is connected with the second conductive pattern, the first conductive pattern is located between the second sub-insulating layer and the third sub-insulating layer, and the second conductive pattern is not covered by the third sub-insulating layer.

Optionally, the third sub-insulating layer covers the second sub-insulating layer.

Optionally, the sidewall of the third conductive layer further has at least one groove, and a concave direction of the groove is parallel to the substrate.

Optionally, the sidewall of the third conductive layer has four grooves.

Optionally, the sidewall of the third conductive layer includes a first portion and a second portion that are disposed opposite to each other in the first direction, the first portion has two grooves, the second portion has two grooves, and the two grooves of the first portion and the two grooves of the second portion are opposite to each other two by two.

Optionally, in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.1 and less than 0.2, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.3;

and in the second direction, the ratio of the length of the groove to the maximum aperture of the first sub-via is less than 0.3.

Optionally, in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.05 and less than 0.15, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.25;

and in the second direction, the ratio of the length of the groove to the maximum aperture of the first sub-via is less than 0.25.

Optionally, in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.05 and less than 0.1, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.2;

and in the second direction, the ratio of the length of the groove to the maximum aperture of the first sub-via is less than 0.2.

Optionally, the display substrate further includes: a plurality of pixel circuits and a plurality of light emitting elements on the substrate; the pixel circuit includes: a switching circuit, a driving circuit and a storage circuit;

the switching circuit is respectively electrically connected with the grid line, the data line and the control end of the driving circuit, and the switching circuit is used for responding to a grid driving signal provided by the grid line and transmitting a data signal provided by the data line to the driving circuit;

the input end of the driving circuit is electrically connected with a driving power line, the output end of the driving circuit is electrically connected with a first pole of a light-emitting element, a second pole of the light-emitting element is electrically connected with a pull-down power line, and the driving circuit is used for responding to a driving power signal and the data signal provided by the driving power line and transmitting driving current to the light-emitting element;

the storage circuit is respectively electrically connected with the first electrode of the light-emitting element and the control end of the driving circuit, and the storage circuit is used for adjusting the potential of the first electrode of the light-emitting element and the potential of the control end of the driving circuit.

Optionally, the switching circuit includes: a switching transistor; the drive circuit includes: a drive transistor; the memory circuit includes: a storage capacitor;

the grid electrode of the switching transistor is electrically connected with the grid line, the first pole of the switching transistor is electrically connected with the data line, and the second pole of the switching transistor is electrically connected with the grid electrode of the driving transistor;

a first pole of the driving transistor is electrically connected with a driving power line, a second pole of the driving transistor is electrically connected with a first pole of one light-emitting element, and a second pole of the light-emitting element is electrically connected with a pull-down power line;

one end of the storage capacitor is electrically connected to the first electrode of the light emitting element, and the other end of the storage capacitor is electrically connected to the gate of the driving transistor.

Optionally, the first conductive layer includes the pull-down power line, and the second conductive layer includes the second pole of the light emitting element.

Optionally, the first conductive layer, the driving power line and the source and drain electrodes of the driving transistor are located on the same layer.

Optionally, the first conductive layer includes: the first conductive block and the second conductive block are sequentially stacked along the direction far away from the substrate base plate;

wherein the first conductive block is electrically connected to the second conductive block, and the second conductive block is electrically connected to the second conductive layer; the second conductive block, the driving power line and the source and drain electrodes of the driving transistor are located on the same layer.

Optionally, the display substrate further includes: a third conductive block located between the first conductive block and the second conductive block;

wherein the third conductive block is electrically connected to the first conductive block and the second conductive block, respectively.

Optionally, the display substrate further includes: a light shielding layer located at the same layer as the first conductive block;

wherein an orthographic projection of the light shielding layer on the substrate is overlapped with an orthographic projection of the driving transistor on the substrate.

Optionally, an orthographic projection of the light shielding layer on the substrate is further overlapped with an orthographic projection of the first electrode of the light emitting element on the substrate.

Optionally, the light shielding layer and the first conductive block are of an integral structure.

Optionally, the light shielding layer includes the data line.

Optionally, the display substrate further includes: the light reflecting layer is positioned on the same layer as the second conductive block;

wherein, the orthographic projection of the light reflecting layer on the substrate base plate is overlapped with the orthographic projection of the first pole of the light emitting element on the substrate base plate.

Optionally, the light reflecting layer and the second electrode of the driving transistor are of an integral structure.

Optionally, the display substrate further includes: and the interlayer insulating layer is positioned between every two adjacent metal layers.

Optionally, the switch transistor and the driving transistor are both transistors with a top gate structure.

Optionally, the switch transistor and the driving transistor are both bottom-gate transistors.

Optionally, the material of the first conductive layer comprises low carbon alloy steel, and the thickness of the first conductive layer is 500 angstroms;

alternatively, the material of the first conductive layer comprises copper, and the thickness of the first conductive layer is 4500 angstroms.

Optionally, the material of the second conductive layer includes silver or silicon oxide or indium tin oxide, and the thickness of the second conductive layer is 500 angstroms.

Optionally, the material of the first sub-insulating layer includes silicon oxide or silicon nitride, and the thickness of the first sub-insulating layer is 4000 angstroms.

Optionally, the material of the second sub-insulating layer includes polyimide, acrylic plastic, or resin, and the thickness of the second sub-insulating layer is 21000 angstroms.

Optionally, the material of the third sub-insulating layer includes polyimide, acrylic plastic, or resin, and the thickness of the third sub-insulating layer is 7000 angstroms.

In another aspect, there is provided a display device including: a power supply assembly, and a display substrate as described in the above aspect;

the power supply assembly is electrically connected with the display substrate and used for supplying power to the display substrate.

Optionally, the display device is an active matrix light emitting diode AMOLED display device.

The beneficial effects brought by the technical scheme provided by the embodiment of the disclosure at least can include:

a display substrate and a display device are provided. The display substrate comprises a substrate, a first conducting layer, an insulating layer and a second conducting layer which are sequentially stacked, and the first conducting layer and the second conducting layer can be overlapped through a through hole penetrating through the insulating layer. Because the side wall of the via hole extends in a stepped manner along the direction far away from the substrate base plate, at least part of the side wall is an arc surface with a tangent line intersected with the substrate base plate, and the size of the opening of the via hole close to the substrate base plate side is smaller than that of the opening far away from the substrate base plate side, the gradient of the side wall of the via hole is gentle. Furthermore, the first conductive layer and the second conductive layer are in lap joint, and good product yield is ensured.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure;

fig. 2 is a top view of a display substrate provided by an embodiment of the disclosure;

FIG. 3 is a cross-sectional view of the top view of FIG. 2 in a first direction;

FIG. 4 is a cross-sectional view of the top view of FIG. 2 in a second orientation;

FIG. 5 is a top view of another display substrate provided by embodiments of the present disclosure;

FIG. 6 is a cross-sectional view of the top view of FIG. 5 in a first direction;

fig. 7 is a top view of yet another display substrate provided by an embodiment of the present disclosure;

FIG. 8 is a cross-sectional view of the top view of FIG. 7 in a first direction;

FIG. 9 is another cross-sectional view of the top view of FIG. 7 in a first direction;

fig. 10 is a top view of yet another display substrate provided by an embodiment of the present disclosure;

FIG. 11 is a cross-sectional view in one direction of the top view of FIG. 10;

FIG. 12 is a cross-sectional view of the top view of FIG. 10 in another orientation;

FIG. 13 is a perspective view of the top view of FIG. 10 in one direction;

fig. 14 is a top view of yet another display substrate provided by an embodiment of the present disclosure;

FIG. 15 is a cross-sectional view of the top view of FIG. 14 in a first direction;

fig. 16 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure;

fig. 17 is a structural layout of a pixel circuit provided in the embodiment of the present disclosure;

fig. 18 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 19 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 20 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 21 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 22 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 23 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 24 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 25 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 26 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 27 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 28 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 29 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 30 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 31 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 32 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure;

fig. 33 is a schematic structural diagram of yet another display substrate provided in an embodiment of the disclosure;

fig. 34 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

Detailed Description

Technical solutions and advantages of the present disclosure will be made clearer in the following description of embodiments of the present disclosure with reference to the accompanying drawings.

The terminology used in the description of the embodiments of the present disclosure is for the purpose of describing the embodiments of the present disclosure only and is not intended to be limiting of the present disclosure. Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present disclosure belongs. The use of "first," "second," "third," and similar terms in the description and claims of the present disclosure are not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprise" or "comprises", and the like, means that the element or item listed before "comprises" or "comprising" covers the element or item listed after "comprising" or "comprises" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, which may also change accordingly when the absolute position of the object being described changes. Reference to "and/or" in embodiments of the disclosure means that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Fig. 1 is a schematic structural diagram of a display substrate according to an embodiment of the disclosure. As shown in fig. 1, the display substrate includes: the multilayer printed wiring board includes a base substrate 01, a first conductive layer 02, an insulating layer 03, and a second conductive layer 04 which are located on one side of the base substrate 01 and stacked in this order, and a via hole K0 which penetrates the insulating layer 03. The via hole K0 may be formed by etching the insulating layer 03 when the display substrate is manufactured.

The second conductive layer 04 is electrically connected to the first conductive layer 02 through the via hole K0, that is, as shown in fig. 1, the second conductive layer 04 may overlap the sidewall of the via hole K0 and extend all the way onto the first conductive layer 02 to be in contact with, that is, electrically connected to, the first conductive layer 02. As such, the insulating layer 03 with the via K0 can also be referred to as a conductive connection structure for effectively electrically connecting two conductive layers located at different layers.

With continued reference to fig. 1, the sidewall of the via hole K0 according to the embodiment of the disclosure extends in a step shape along the direction X1 away from the substrate base plate 01, and the sidewall of the via hole K0 is at least partially a curved surface (which may also be referred to as a curved surface with a continuously changing slope), and a tangent of the curved surface intersects with the substrate base plate 01. The orthogonal projection of the opening of via hole K0 on the side closer to substrate board 01 on substrate board 01 is within the orthogonal projection of the opening of via hole K0 on the side farther from substrate board 01 on substrate board 01. That is, the diameter of the opening of the via hole K0 on the side closer to the substrate base 01 is smaller than the diameter of the opening of the via hole K0 on the side farther from the substrate base 01.

Thus, as can be seen from fig. 1, the slope of the sidewall of the via hole K0 is generally gentle. Accordingly, even if the hole depth of the via hole K0 is large, the second conductive layer 04 connected to the via hole K is less likely to be broken or broken. In this manner, stable and reliable contact of the second conductive layer 04 with the first conductive layer 02 is ensured. In conjunction with fig. 1, the hole depth of the via K0 may refer to the height of the via K0 in the X1 direction.

In summary, the embodiment of the present disclosure provides a display substrate, which includes a substrate, a first conductive layer, an insulating layer, and a second conductive layer stacked in sequence, where the first conductive layer and the second conductive layer may be overlapped by a via penetrating through the insulating layer. Because the side wall of the via hole extends in a stepped manner along the direction far away from the substrate base plate, at least part of the side wall is an arc surface with a tangent line intersected with the substrate base plate, and the size of the opening of the via hole close to the substrate base plate side is smaller than that of the opening far away from the substrate base plate side, the gradient of the side wall of the via hole is gentle. Furthermore, the first conductive layer and the second conductive layer are in lap joint, and good product yield is ensured.

Optionally, referring to fig. 1, the arc surface described in the embodiment of the present disclosure protrudes toward the direction close to the second conductive layer 04. Of course, in some embodiments, the arc surface may also be convex in a direction away from the second conductive layer 04.

Optionally, in the embodiment of the present disclosure, the insulating layer 03 includes at least two sub-insulating layers sequentially stacked in a direction away from the base substrate 01. Accordingly, the via hole penetrating the insulating layer 03 includes: and the sub-via holes are communicated with each other and penetrate through each layer of the sub-insulating layer.

For example, fig. 2 shows a top view of a display substrate provided by an embodiment of the present disclosure. Fig. 3 shows a cross-sectional view of the top view shown in fig. 2 in a first direction AA'. Fig. 4 is a cross-sectional view of the top view shown in fig. 2 in the second direction BB'. The first direction AA 'and the second direction BB' are perpendicular to each other. As can be seen from fig. 2 to 4, the insulating layer 03 according to the embodiment of the present disclosure includes: a first sub insulating layer 031, a second sub insulating layer 032, and a third sub insulating layer 033 stacked in this order in a direction away from the base substrate 01.

Correspondingly, the via hole K0 described in the embodiment of the present disclosure includes: a first sub-via K01 communicating with each other and penetrating through the first sub-insulating layer 031, a second sub-via K02 penetrating through the second sub-insulating layer 032, and a third sub-via K03 penetrating through the third sub-insulating layer 033 (only shown in fig. 3).

The first sub-via K01 may be formed by etching the first sub-insulating layer 031 during the manufacture of the display substrate. The second sub-via K02 may be formed by etching the second sub-insulating layer 032 when the display substrate is manufactured. The third sub via hole K03 may be formed by etching the third sub insulating layer 033 when manufacturing the display substrate.

In addition, referring to fig. 3 and 4, it can be seen that the cross-sectional view in the first direction AA 'corresponding to the top view shown in fig. 2 is identical in structure to the cross-sectional view in the second direction BB'. Fig. 3 also shows a partially enlarged view including the first conductive layer 02, the first sub-insulating layer 031, and the second sub-insulating layer 032, an aperture d1 of the first sub-via K01 in the first direction AA ', and a length d2 of a portion of the first sub-via K01 on the side away from the substrate base plate 01 that is not blocked by the second sub-insulating layer 032 in the first direction AA'. Fig. 4 also shows a partially enlarged view including the first conductive layer 02 and the first sub-insulating layer 031, and an aperture d3 of the first sub-via K01 in the second direction BB'. d1 and d3 may be the same or different, and d2 is generally less than d1 and less than d 2.

Alternatively, in the embodiment of the present disclosure, the length of the flat surface of the first sub insulating layer 031 which is far from the substrate 01 side and is not blocked by the second sub insulating layer 032, the length d2 in the first direction AA ', and the length in the second direction BB' may be greater than or equal to 20 micrometers and less than or equal to 60 micrometers.

As can be seen by continuing to refer to fig. 3 and 4, the sidewalls of the second sub-via K02 and the sidewalls of the third sub-via K03 according to the embodiments of the present disclosure are both arc-shaped. And, in any direction, the aperture of the first sub-via hole K01, the aperture of the second sub-via hole K02, and the aperture of the third sub-via hole K03 are sequentially increased. For example, in connection with fig. 4, the aperture of the first sub-via K01 is identified by d3, the aperture of the second sub-via K02 is identified by d4, and the aperture of the third sub-via K03 is identified by d 5. As can be seen from the figure, the size relationship of d3, d4 and d5 satisfies: d3< d4< d 5.

The above only schematically illustrates the shape of the sidewall of the second sub-via K02 and the sidewall of the third sub-via K03. As for the first sub-via K01, as can be seen from fig. 3 and 4, its section in any direction, that is, any section thereof is rectangular.

For this structure, it can be considered that: the third sub-insulating layer 033 is formed with a plurality of first curved surfaces (i.e., curved surfaces shown in the drawing) having a continuously varying slope at the conductive connection structure, and the second sub-insulating layer 032 is formed with a plurality of second curved surfaces (i.e., curved surfaces shown in the drawing) having a continuously varying slope at the conductive connection structure, each of the first curved surfaces being connected to one of the second curved surfaces, and the slope of the connection point abruptly changes. The first sub-insulating layer 031 forms a plurality of flat surfaces at the conductive connection structure, each of which is connected to one of the second curved surfaces, and the slope of the connection is abrupt. The minimum height of the first curved surface from the substrate base plate 01 is greater than or equal to the maximum height of the second curved surface from the substrate base plate 01. The minimum height of the second curved surface from the substrate base plate 01 is greater than or equal to the maximum height of the flat surface from the substrate base plate 01. The flat surfaces in the respective directions expose the first conductive layer 02.

Or the first cross section of the first sub-via K01 is rectangular, the second cross section of the first sub-via K01 is polygonal, and the first cross section is perpendicular to the second cross section. Wherein the second cross section may be parallel to the first direction AA ', i.e. the second cross section may be a cross section in the first direction AA'. Accordingly, the first cross section may be parallel to the second direction BB ', i.e. the first cross section may be a cross section in the second direction BB'.

For example, fig. 5 shows a top view of another display substrate, and fig. 6 shows a cross-sectional view of the top view shown in fig. 5 in the first direction AA', that is, a second cross-section of the first sub-via K01 is shown. As can be seen from the top view shown in fig. 5, the cross section of the first sub-via K01 in the second direction BB', that is, the first cross section of the first sub-via K01, can refer to fig. 4, and will not be described again.

As can be seen in conjunction with fig. 5 and 6, the polygon includes first and/or second opposing sides L1, L2, and third and/or fourth opposing sides L3, L4.

The first side L1 is connected to the third side L3, the second side L2 is connected to the fourth side L4, the first side L1 and the second side L2 are perpendicular to the substrate 01, an included angle α between the third side L3 and the first conductive layer 02, and an included angle α between the fourth side L4 and the first conductive layer 02 are acute angles.

In addition, fig. 6 also shows a partially enlarged view including the second conductive layer 02 and the first sub-insulating layer 031, a length L1 of an orthogonal projection of the third side L3 on the substrate base plate 01, a distance h2 between a connection point of the fourth side L4 and the second side L2 and the first conductive layer 02, and an angle α between the third side L3 and the first conductive layer 02.

Optionally, with reference to fig. 3, the length L1 of the orthographic projection of the third side L3 on the substrate base plate 01, and/or the length L4 of the orthographic projection on the substrate base plate 01 are both greater than or equal to 1 micrometer and less than or equal to 3 micrometers. For example, the length L1 of the orthographic projection of the third side L3 on the substrate base plate 01 and/or the length of the orthographic projection of the fourth side L4 on the substrate base plate 01 are both greater than or equal to 1.5 micrometers and less than or equal to 2 micrometers. By setting the upper limit to 2 μm, it is possible to ensure that the first conductive layer 02 is effectively exposed, thereby ensuring sufficient contact between the second conductive layer 04 and the first conductive layer 02, and reducing the resistance. By setting the lower limit to 1.5 microns, the slope of the sidewall can be ensured to be long, which is beneficial to the continuity of the deposition of the second conductive layer 04 on the sidewall.

Optionally, with continued reference to fig. 3, a distance between a connection point of the third side L3 and the first side L1 and the first conductive layer 02, and/or a distance h1 between a connection point of the fourth side L4 and the second side L2 and the first conductive layer 02 are less than or equal to 1 micrometer. Alternatively, the distance between the connection point of the third side L3 and the first side L1 and the first conductive layer 02 and/or the distance h1 between the connection point of the fourth side L4 and the second side L2 and the first conductive layer 02 are each 0.5 μm or less. Alternatively, the distance between the connection point of the third side L3 and the first side L1 and the first conductive layer 02 and/or the distance h1 between the connection point of the fourth side L4 and the second side L2 and the first conductive layer 02 are each 0.4 μm or less. The smaller the pitch, the flatter the slope of the side wall, thereby facilitating the continuity of the deposition of the second conductive layer 04 on the side wall.

Optionally, with reference to fig. 3, an included angle α between the third side L3 and the first conductive layer 02 and an included angle between the fourth side L4 and the first conductive layer 02 are both smaller than 30 degrees. Alternatively, the included angle α between the third side L3 and the first conductive layer 02 and the included angle α between the fourth side L4 and the first conductive layer 02 are both less than 20 degrees. Alternatively, the included angle α between the third side L3 and the first conductive layer 02 and the included angle α between the fourth side L4 and the first conductive layer 02 are both less than 15 degrees. The smaller the angle, the gentler the slope of the side wall, thereby facilitating the continuity of the deposition of the second conductive layer 04 on the side wall.

In addition, with continuing reference to fig. 3, a ratio of a length L1 of an orthographic projection of the third side L3 on the substrate base plate 01 to a maximum aperture d1 of the first sub-via hole K01 in the first direction AA' (i.e., L1/d 1) is less than 0.1. The ratio of the distance h1 between the connection point of the third side L3 and the first side L1 and the first conductive layer 02 to the length L1 of the orthographic projection of the third side L3 on the substrate base plate 01, namely h1/L1, is less than 0.4.

As can be seen from fig. 5 and 6, the third side L3 and the fourth side L4 may also be referred to as a raised slope, and the raised slope may buffer the second conductive layer 04 overlapping the via hole K0, and may also be referred to as a buffer slope. The overlapping of the first conductive layer 02 and the second conductive layer 04 can be further facilitated.

Of course, in some embodiments, the first cross section of the first sub-via K01 may also be polygonal as shown in fig. 6. Alternatively, the sidewall of the first sub-via K01 may also be curved.

Fig. 7 is a top view of another display substrate provided in an embodiment of the disclosure. Fig. 8 is a cross-sectional view of the top view shown in fig. 7 in a first direction AA'. As can be seen from the top view shown in fig. 7, the cross section in the second direction BB' can refer to fig. 4, and is not described again.

As can be seen with reference to fig. 7 and 8, the display substrate 00 according to the embodiment of the present disclosure further includes: and a third conductive layer 05 positioned on the side of the first conductive layer 02 far away from the substrate base plate 01, wherein the third conductive layer 05 covers part or all of the side wall of the via hole K0.

For example, as can be seen from fig. 7 and 8, the sidewall of the via hole K0 includes a first portion and a second portion oppositely disposed in the first direction AA ', and a third portion and a fourth portion oppositely disposed in the second direction BB'. Wherein the third conductive layer 05 covers the first and second portions of the sidewalls of the via K0. And, a sidewall of the second sub-via K02 and a partial sidewall of the third sub-via K03 included in the via K0 are covered.

As can be seen from fig. 1, the second conductive layer 02 overlapping the via hole K0 can also contact the third conductive layer 05, which increases the contact area of the conductive layer and is beneficial to reducing the resistance. Based on this, in some embodiments, the third conductive layer 05 also covers the third and fourth portions of the sidewalls of the via K0, i.e., the third conductive layer 05 may cover most of the area of the sidewalls of the via K0. Furthermore, in some embodiments, the third conductive layer 05 also covers the first conductive layer 02.

Optionally, as described in conjunction with the embodiment corresponding to fig. 4, a difference between a minimum height of the first curved surface of the third sub-insulating layer 033 from the substrate base plate 01 and a minimum height of the second curved surface of the second sub-insulating layer 032 from the substrate base plate 01 may be less than 1.2 times of a thickness of the third conductive layer 05. The difference between the minimum height of the first curved surface from the substrate base 01 and the minimum height of the second curved surface connected thereto from the substrate base 01 may be greater than 10 times the thickness of the third conductive layer 05.

Alternatively, in combination with another cross section in the second direction BB' of the top view shown in fig. 7 shown in fig. 9, the third conductive layer 05 includes: a first conductive pattern 051 and a second conductive pattern 052, the first conductive pattern 051 being connected with the second conductive pattern 052. Also, the first conductive pattern 051 is located between the second sub-insulating layer 032 and the third sub-insulating layer 033, and the second conductive pattern 052 is not covered by the third sub-insulating layer 033.

Furthermore, referring to fig. 9, it can also be seen that the third sub-insulating layer 033 is shown to cover the second sub-insulating layer 032. That is, as described with reference to the embodiment corresponding to fig. 4, in the first direction AA', the first curved surface formed by the third sub-insulating layer 033 covers the second curved surface formed by the second sub-insulating layer 032. The third conductive layer 05 covers the second curved surface formed by the second sub-insulating layer 032, and the flat surface of the first sub-insulating layer 031 that is far away from the substrate 01 and is not blocked by the second sub-insulating layer 032.

Optionally, the layer structures described in the above embodiments may be formed by a patterning process, where the patterning process includes: exposed, developed, or etched (e.g., photolithographically). Accordingly, if the second conductive pattern 052 is not disposed at the slope portion (i.e., the side away from the substrate 01) of the second sub-insulating layer 032, the exposure depth of the photolithography process and the thickness of the photoresist at the slope or the boundary of the two layers may vary, and accordingly, the third conductive layer 05 may remain above the slope of the second sub-insulating layer 032.

Therefore, compared to the structure shown in fig. 8, the structure shown in fig. 9 can effectively reduce the alignment precision of the photolithography process for forming the third conductive layer 05 and the photolithography process for forming the insulating layers (including the second sub-insulating layer 032 and the third sub-insulating layer 033), reduce the residue of the third conductive layer 05 formed at the edge of the second sub-insulating layer 032 due to process errors, and reduce the residue of the third sub-insulating layer 033 formed at the edge of the second conductive pattern 052 due to process errors. Furthermore, the precision of forming each layer structure can be effectively ensured to be better.

Of course, in some embodiments, the cross section in the second direction BB 'may be the same as fig. 9, that is, the cross section in the second direction BB', and the third conductive layer 05 may also include: a first conductive pattern 051 and a second conductive pattern 052, the first conductive pattern 051 being connected with the second conductive pattern 052. Also, the first conductive pattern 051 is located between the second sub-insulating layer 032 and the third sub-insulating layer 033, and the second conductive pattern 052 is not covered by the third sub-insulating layer 033.

Fig. 10 illustrates a top view of still another display substrate provided by an embodiment of the present disclosure. Fig. 11 shows a cross section of the top view of fig. 10 in the direction CC'. Fig. 12 shows a cross-section of the top view of fig. 10 in the direction DD'. Fig. 13 shows a projection of the top view of fig. 10 in a first direction AA'. As can be seen from the top view shown in fig. 10, the cross section of the first direction AA 'can refer to fig. 9, and the cross section of the second direction BB' can refer to fig. 4, which are not repeated.

As can be seen from fig. 10 and 13, the sidewall of the third conductive layer 05 according to the embodiment of the disclosure further has at least one groove C0, and the recess direction of the groove C0 is parallel to the substrate base plate 01. Of these, a total of 4 grooves C0 are shown in fig. 10. The four recesses C0 are located in the first and second portions of the side wall and are positioned opposite each other two by two. By providing the groove C0, the side area of the third conductive layer 05 can be increased. Thus, the contact area between the third conductive layer 05 and a conductive layer (e.g., the second conductive layer 04) deposited over the third conductive layer 05 can be further increased, and the contact resistance can be effectively reduced.

Fig. 10 also identifies the length W of the groove C0 in the first direction AA 'and the length L in the second direction BB'.

Alternatively, referring to fig. 3, in the first direction AA', a ratio of the length W of the groove C0 to the maximum aperture d1 of the first sub-via K01 (i.e., W/d 1) is greater than 0.1 and less than 0.2, and a ratio of the length W of the groove C0 to the length d2 of the flat surface of the first sub-via K01 that is not shielded by the second sub-insulating layer 032 (i.e., W/d 2) is less than 0.3. Referring to fig. 4, in the second direction BB', a ratio of a length L of the groove C0 to a maximum aperture d3 of the first sub-via K01 penetrating the first sub-insulating layer 031 (i.e., L/d 3) is less than 0.3.

Alternatively, in the first direction AA', the ratio of the length W of the groove C0 to the maximum aperture d1 of the first sub-via K01 (i.e., W/d 1) is greater than 0.05 and less than 0.15, and the ratio of the length W of the groove C0 to the length d2 of the flat surface of the first sub-via K01 that is not shielded by the second sub-insulating layer 032 (i.e., W/d 2) is less than 0.25. Referring to fig. 4, in the second direction BB', a ratio of a length L of the groove C0 to a maximum aperture d3 of the first sub-via K01 penetrating the first sub-insulating layer 031 (i.e., L/d 3) is less than 0.25.

Alternatively, in the first direction AA', the ratio of the length W of the groove C0 to the maximum aperture d1 of the first sub-via K01 (i.e., W/d 1) is greater than 0.05 and less than 0.1, and the ratio of the length W of the groove C0 to the length d2 of the flat surface of the first sub-via K01 that is not shielded by the second sub-insulating layer 032 (i.e., W/d 2) is less than 0.2. Referring to fig. 4, in the second direction BB', a ratio of a length L of the groove C0 to a maximum aperture d3 of the first sub-via K01 penetrating the first sub-insulating layer 031 (i.e., L/d 3) is less than 0.2.

The smaller the ratio described in the above embodiment is, the closer the length of the groove C1 is to the thickness of the third conductive layer 05. Since the side area of the groove C1 is positively correlated with the thickness of the third conductive layer 05, the surface area of the third conductive layer 05 dug out at the groove C1 is approximately positively correlated with the length of the groove C1. As such, the side area of the groove C1 can be made larger than the surface area of the third conductive layer 05 that is dug away, whereby it can be facilitated to improve the contact resistance between the conductive layers.

With reference to fig. 13, the following description is made on a display substrate having a groove structure: the third conductive layer 05 may have a first side and a second side, which are indicated in fig. 13, in a direction perpendicular to the substrate base plate 01, the first side does not exceed the flat surface of the first sub-insulating layer 031 and is substantially parallel to the flat surface of the first sub-insulating layer 031. The second side surface is not parallel to the flat surface of the first sub-insulating layer 031, and includes at least one groove with a continuously varying slope. Fig. 13 shows a total of 2 grooves C0.

Referring to fig. 5, 7 and 10, fig. 14 is a plan view of still another display substrate, and fig. 15 is a cross-section of the plan view of fig. 14 in the CC' direction. As can be seen from the top view shown in fig. 14, fig. 6 and fig. 9 can be referred to for the cross section in the first direction AA ', and fig. 4 can be referred to for the cross section in the second direction BB', which are not repeated.

Optionally, the display substrate 00 according to the embodiment of the present disclosure further includes: a plurality of pixel circuits 06 and a plurality of light emitting elements 07 on the base substrate 01. Alternatively, as can be seen with reference to fig. 16, the pixel circuit 06 includes: a switch circuit 061, a drive circuit 062, and a memory circuit 063.

The switch circuit 061 is electrically connected to the gate line Scan, the Data line Data, and the control terminal of the driving circuit 062, and the switch circuit 061 is configured to transmit the Data signal provided by the Data line Data to the driving circuit in response to the gate driving signal provided by the gate line Scan.

The input terminal of the driving circuit 062 is electrically connected to a driving power line VDD, the output terminal of the driving circuit 062 is electrically connected to a first pole of one light emitting element 07, a second pole of the light emitting element 07 is electrically connected to a pull-down power line VSS, and the driving circuit 062 is configured to transmit a driving current to the light emitting element 07 in response to a driving power signal and a data signal supplied from the driving power line VDD.

The memory circuit 063 is electrically connected to the first electrode of the light-emitting element 07 and the control terminal of the drive circuit 062, respectively, and the memory circuit 063 adjusts the potential of the first electrode of the light-emitting element 07 and the potential of the control terminal of the drive circuit 062.

Optionally, as can be seen with continued reference to fig. 16, the switching circuit 061 includes: the switching transistor T1, the driving circuit 062, and the storage circuit 063 include a storage capacitor C1 drive the transistor T2. The gate of the driving transistor T2 is the control terminal of the driving circuit 062, the first pole of the driving transistor T2 may be the input terminal of the driving circuit 062, and the second pole of the driving transistor T2 may be the output terminal of the driving circuit 062.

The gate of the switching transistor T1 is electrically connected to the gate line Scan, the first electrode of the switching transistor T1 is electrically connected to the Data line Data, and the second electrode of the switching transistor T1 is electrically connected to the gate of the driving transistor T2.

A first electrode of the driving transistor T2 is electrically connected to the driving power supply line VDD, a second electrode of the driving transistor T2 is electrically connected to a first electrode of one light emitting element 07, and a second electrode of the light emitting element 07 is electrically connected to the pull-down power supply line VSS.

Alternatively, the first pole of the light emitting element 07 may be an anode, and correspondingly, the second pole of the light emitting element 07 is a cathode. Of course, in some embodiments, the first pole of the light emitting element 07 may also be a cathode, and correspondingly, the second pole of the light emitting element 07 may be an anode.

One end of the storage capacitor C1 is electrically connected to the first pole of the light emitting element 07, and the other end of the storage capacitor C1 is electrically connected to the gate of the driving transistor T2.

Alternatively, taking the structure shown in fig. 16 as an example, fig. 17 shows a structural layout of the circuit diagram shown in fig. 16. As can be seen with reference to fig. 17, the display substrate further includes signal lines (e.g., Data lines Data and pull-down power lines VSS) on the substrate 01 and extending in the first direction AA ', and signal lines (e.g., gate lines Scan) extending in the second direction BB'.

Alternatively, the minimum distance from the first side surface of the third conductive layer 05 described in the above embodiment to the signal line extending in the first direction AA 'is greater than or equal to 60 micrometers, and the minimum distance from the first side surface of the third conductive layer 05 to the signal line extending in the second direction BB' is greater than or equal to 20 micrometers.

Fig. 18 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure. As can be seen with reference to fig. 18, the first conductive layer 02 described in the above embodiment includes the pull-down power supply line VSS, and the second conductive layer 04 includes the second pole (i.e., cathode) of the light emitting element 07. Also, the first conductive layer 02 is located at the same layer as the driving power supply line VDD and the source and drain electrodes of a transistor (e.g., the driving transistor T2 shown in fig. 18).

Being on the same layer may mean: and forming a film layer for forming a specific pattern by using the same film forming process, and patterning the film layer by using the same mask plate through a one-time composition process to form a layer structure. Depending on the specific pattern, one patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or portions located at the "same layer" are made of the same material and are formed through the same patterning process. Therefore, the manufacturing process can be simplified, and the manufacturing cost can be saved.

In addition, fig. 18 also shows that the driving transistor T2 includes a gate electrode, a first electrode, a second electrode, an active layer electrically connected to the first electrode and the second electrode, an interlayer insulating layer between the gate electrode and the active layer, an interlayer insulating layer between the active layer and the first electrode and the second electrode, a first sub-insulating layer 031, a second sub-insulating layer 032, a third sub-insulating layer 033, an anode of the light emitting element 07, and a light emitting layer between the anode and the cathode of the light emitting element 07.

Fig. 19 is a schematic structural diagram of another display substrate according to an embodiment of the disclosure. With respect to the structure shown in fig. 18, as can be seen with reference to fig. 19, the first conductive layer 02 described in the embodiment of the present disclosure includes: a first conductive block 021 and a second conductive block 022 laminated in this order in a direction away from the base substrate 01. That is, the pull-down power line VSS may be formed of a double metal in parallel.

The first conductive pad 021 is electrically connected to the second conductive pad 022, and the second conductive pad 022 is electrically connected to the second conductive layer 04. Alternatively, as can be seen in fig. 18 and 19, the first conductive block 021 and the second conductive block 022 may be electrically connected through a via hole penetrating through the two interlayer insulating layers.

In the display substrates shown in fig. 18 and 19, the transistors each have a bottom gate structure.

Fig. 20 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure. As can be seen from fig. 20, the display substrate according to the embodiment of the present disclosure further includes: and a light-shielding layer 08 in the same layer as the first conductive block 021.

Alternatively, an orthographic projection of the light-shielding layer 08 on the base substrate 01 overlaps with an orthographic projection of the driving transistor T2 on the base substrate 01. Alternatively, referring to a further display substrate shown in fig. 21, the orthographic projection of the light-shielding layer 08 on the base substrate 01 is also overlapped with the orthographic projection of the first electrode (i.e., anode) of the light-emitting element 07 on the base substrate 01. Thus, effective light shielding can be achieved.

Optionally, fig. 22 is a schematic structural diagram of another display substrate provided in the embodiment of the present disclosure. Referring to fig. 22, the light shielding layer 08 is integrated with the first conductive block 021, i.e., formed by a single patterning process. Therefore, the manufacturing process can be further simplified, and the manufacturing cost can be saved.

It should be noted that, as can be seen from fig. 20 to 22, since the light-shielding layer 08 is disposed at the same layer position of the first conductive block 021, the gate of the driving transistor T2 can be adjusted to be above the active layer, and the structure can also be referred to as a top gate structure. In addition, in order to avoid signal interference between adjacent metal layers, an interlayer insulating layer is additionally added to the structure, compared with the structures shown in fig. 18 and 19.

Fig. 23 is a schematic structural diagram of another display substrate provided in the disclosed embodiments. As can be seen from fig. 23, the display substrate according to the embodiment of the present disclosure further includes: and a light reflecting layer 09 on the same layer as the second conductive bumps 022. An orthogonal projection of the light reflecting layer 09 on the base substrate 01 overlaps an orthogonal projection of the first electrode (i.e., anode) of the light emitting element 07 on the base substrate 01.

In addition, referring to fig. 23, it can also be seen that the light reflection layer 09 is integrated with the second pole of the driving transistor T2, i.e., can be formed through one patterning process. Therefore, the manufacturing process can be further simplified, and the manufacturing cost can be saved.

Fig. 24 is a schematic structural diagram of another display substrate provided in an embodiment of the disclosure. As can be seen from fig. 24, the display substrate according to the embodiment of the present disclosure further includes: and a third conductive block 023 positioned between the first conductive block 021 and the second conductive block 022.

The third conductive block 023 is electrically connected to the first conductive block 021 and the second conductive block 022, respectively. In other words, the pull-down power line VSS may be formed of three layers of metal in parallel.

In the display substrates shown in fig. 20 to 24, the gate electrode of the driving transistor T2 is located between the active layer and the first electrode. Of course, in some embodiments, as can be seen with reference to fig. 25 to 28, the gate of the driving transistor T2 of the top gate structure is at the same layer as the first and second poles. Accordingly, the light shielding layer 08 functions as the Data line Data. Fig. 27 and 28 also show the structure of the storage capacitor C1, relative to fig. 25 and 26. In this regard, the sectional views shown in fig. 25 and 27 are sectional views of the same region, and the sectional views shown in fig. 26 and 28 are sectional views of the same region.

Taking the cross section shown in fig. 9 as an example, fig. 29 shows a partial cross section in the first direction AA' further including the second conductive layer 04. Fig. 30 shows a partial cross-sectional view in the first direction AA' further including a second conductive layer 04. In fig. 30, as compared to fig. 29, the third conductive layer 05 also covers the first conductive layer 02. Fig. 31 to 33 respectively show partial sectional views in the first direction AA' further including a light emitting layer. Fig. 32 is a view showing that, as compared with fig. 31, the light-emitting layer covers the flat surface of the third conductive layer 05 on the side away from the substrate 01. In fig. 33, the third conductive layer 05 does not cover the first conductive layer 02 as compared with fig. 32.

Optionally, the material of the conductive layer according to the embodiment of the present disclosure may include at least one of the following metal materials: low carbon alloy steel MoTi, i.e., stainless steel material, copper Cu, molybdenum Mo, silver Ag, silicon oxide SiO, indium-tin oxide (ITO), indium-zinc oxide IZO. For example, the material of the first conductive layer 02 is MoTi or Cu, the thickness of the first conductive layer 02 made of MoTi is 500 angstroms (a), and the thickness of the first conductive layer 02 made of Cu is 4500A. The third conductive layer 05 is made of Mo or ITO, the thickness of the third conductive layer 05 made of Mo is 500A, and the thickness of the third conductive layer 05 made of ITO is 1100A. The second conductive layer 04 may be made of Ag, ITO, or IZO, and may have a thickness of 500A. The material of the first conductive block 021 can be SiO, and the thickness is 1500A. The material of the second conductive piece 022 is Mo or Cu, the thickness of the second conductive piece 022 is 500A, and the thickness of the second conductive piece 022 is 4100A.

Optionally, the active layer described in the embodiments of the present disclosure is made of indium gallium zinc oxide IGZO or low temperature polysilicon LTPS, and has a thickness of 300A.

Optionally, the material of the insulating layer according to the embodiment of the present disclosure may include at least one of the following materials: polyimide (PI), acrylic plastic (acrylic), resin (resin), silicon oxide SiO, silicon nitride SiN. For example, the material of the first sub-insulating layer 031 is SiO or SiN, and the thickness is 4000A. The material of the second sub-insulating layer 032 is PI or acrylic or resin, and the thickness is 21000A. The material of the third sub-insulating layer 033 is PI, acrylic, or resin, and has a thickness of 7000A. The rest of the insulating layer is made of SiO or SiN, and the thickness of the insulating layer is 1200A, 4000A or 5300A.

Alternatively, the thickness of the light emitting layer described in the embodiment of the present disclosure may be 2500A. It should be noted that the above definitions of thickness and material are only schematic illustrations.

Fig. 34 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 34, the display device includes: a power supply assembly 10, and a display substrate 00 as shown in the above figures. The power supply assembly 10 is electrically connected to the display substrate 00, and the power supply assembly 10 is used for supplying power to the display substrate 00.

Optionally, the display device is: an OLED display device, an active-matrix light-emitting diode (AMOLED) display device, a Liquid Crystal Display (LCD) device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator, or any other product or component having a display function. The AMOLED display device has the advantages of long service life, high display brightness, high contrast, wide color gamut and the like.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims

1. A display substrate, comprising:

a substrate base plate;

2. The display substrate according to claim 1, wherein the arc surface is convex in a direction approaching the second conductive layer.

3. The display substrate according to claim 1, wherein the insulating layer comprises: at least two sub-insulating layers sequentially stacked along a direction far away from the substrate base plate;

4. The display substrate according to claim 3, wherein the insulating layer comprises: the first sub-insulating layer, the second sub-insulating layer and the third sub-insulating layer are sequentially stacked along the direction far away from the substrate base plate;

5. The display substrate according to claim 4, wherein the aperture of the first sub-via, the aperture of the second sub-via, and the aperture of the third sub-via are sequentially increased.

6. The display substrate of claim 4, wherein the sidewall of at least one of the second sub-via and the third sub-via has a cambered surface.

7. The display substrate of claim 4, wherein any cross section of the first sub-via is rectangular.

8. The display substrate according to claim 4, wherein a first cross section of the first sub-via is rectangular, a second cross section of the first sub-via is polygonal, and the first cross section is perpendicular to the second cross section;

9. The display substrate of claim 8, wherein the length of the orthographic projection of the third edge on the substrate and the length of the orthographic projection of the fourth edge on the substrate are both greater than or equal to 1 micron, and the first direction is parallel to the second cross section;

10. The display substrate of claim 8, wherein the length of the orthographic projection of the third edge on the substrate and the length of the orthographic projection of the fourth edge on the substrate are both greater than or equal to 1.5 microns, and the first direction is parallel to the second cross section;

11. The display substrate of claim 8, wherein the length of the orthographic projection of the third edge on the substrate and the length of the orthographic projection of the fourth edge on the substrate are both less than or equal to 2 microns, and the first direction is parallel to the second cross section;

12. The display substrate according to any one of claims 1 to 11, wherein the display substrate further comprises: and the third conducting layer is positioned on one side of the first conducting layer, which is far away from the substrate base plate, and covers part or all of the side wall of the through hole.

13. The display substrate according to claim 12, wherein the sidewall of the via hole comprises a first portion and a second portion oppositely arranged in a first direction, and a third portion and a fourth portion oppositely arranged in a second direction, the first direction being perpendicular to the second direction;

14. The display substrate of claim 13, wherein the third conductive layer further covers third and fourth portions of the sidewalls of the via.

15. The display substrate of claim 13, wherein the third conductive layer covers a sidewall of the second sub-via and a portion of a sidewall of the third sub-via included in the via.

16. The display substrate according to claim 12, wherein the third conductive layer further covers the first conductive layer.

17. The display substrate according to claim 12, wherein the insulating layer comprises: the first sub-insulating layer, the second sub-insulating layer and the third sub-insulating layer are sequentially stacked along the direction far away from the substrate base plate;

18. The display substrate according to claim 17, wherein the third sub insulating layer covers the second sub insulating layer.

19. The display substrate according to any one of claims 13 to 18, wherein the sidewall of the third conductive layer further has at least one groove, and a recessed direction of the groove is parallel to the substrate.

20. The display substrate according to claim 19, wherein the sidewall of the third conductive layer has four grooves.

21. The display substrate according to claim 20, wherein the sidewalls of the third conductive layer comprise a first portion and a second portion which are oppositely arranged in the first direction, wherein the first portion has two grooves, wherein the second portion has two grooves, and wherein the two grooves of the first portion are opposite to the two grooves of the second portion in a two-by-two manner.

22. The display substrate according to claim 19, wherein in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.1 and less than 0.2, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.3;

23. The display substrate according to claim 19, wherein in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.05 and less than 0.15, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.25;

24. The display substrate according to claim 19, wherein in the first direction, a ratio of a length of the groove to a maximum aperture of the first sub-via penetrating through the first sub-insulating layer is greater than 0.05 and less than 0.1, and a ratio of the length of the groove to a length of the second conductive pattern of the third conductive layer not covered by the third sub-insulating layer is less than 0.2;

25. The display substrate according to any one of claims 1 to 11, wherein the display substrate further comprises: a plurality of pixel circuits and a plurality of light emitting elements on the substrate; the pixel circuit includes: a switching circuit, a driving circuit and a storage circuit;

26. The display substrate of claim 25, wherein the switching circuit comprises: a switching transistor; the drive circuit includes: a drive transistor; the memory circuit includes: a storage capacitor;

27. The display substrate according to claim 25, wherein the first conductive layer comprises the pull-down power supply line, and wherein the second conductive layer comprises a second electrode of the light emitting element.

28. The display substrate according to claim 27, wherein the first conductive layer is located on a same layer as the driving power supply line and a source drain of the driving transistor.

29. The display substrate according to claim 27, wherein the first conductive layer comprises: the first conductive block and the second conductive block are sequentially stacked along the direction far away from the substrate base plate;

30. The display substrate of claim 29, further comprising: a third conductive block located between the first conductive block and the second conductive block;

31. The display substrate of claim 29, further comprising: a light shielding layer located at the same layer as the first conductive block;

32. The display substrate according to claim 31, wherein an orthographic projection of the light-shielding layer on the base substrate further overlaps with an orthographic projection of the first electrode of the light-emitting element on the base substrate.

33. The display substrate of claim 31, wherein the light shielding layer is integrated with the first conductive bump.

34. The display substrate according to claim 31, wherein the light-shielding layer comprises the data line.

35. The display substrate of claim 29, further comprising: the light reflecting layer is positioned on the same layer as the second conductive block;

36. The display substrate of claim 35, wherein the light reflecting layer is integrated with the second electrode of the driving transistor.

37. The display substrate according to any one of claims 29 to 36, wherein the display substrate further comprises: and the interlayer insulating layer is positioned between every two adjacent metal layers.

38. The display substrate according to any one of claims 26 to 36, wherein the switching transistor and the driving transistor are both top-gate transistors.

39. The display substrate according to any one of claims 26 to 36, wherein the switching transistor and the driving transistor are bottom-gate transistors.

40. The display substrate according to any one of claims 1 to 11, wherein the material of the first conductive layer comprises low carbon alloy steel, and the thickness of the first conductive layer is 500 angstroms;

41. The display substrate according to any one of claims 1 to 11, wherein the material of the second conductive layer comprises silver or silicon oxide or indium tin oxide, and the thickness of the second conductive layer is 500 angstroms.

42. The display substrate according to any one of claims 4 to 11, wherein the material of the first sub insulating layer comprises silicon oxide or silicon nitride, and the thickness of the first sub insulating layer is 4000 angstroms.

43. The display substrate according to any one of claims 4 to 11, wherein the material of the second sub insulating layer comprises polyimide, acrylic plastic or resin, and the thickness of the second sub insulating layer is 21000 angstroms.

44. The display substrate according to any one of claims 4 to 11, wherein the material of the third sub insulating layer comprises polyimide, acrylic plastic or resin, and the thickness of the third sub insulating layer is 7000 angstroms.

45. A display device, characterized in that the display device comprises: a power supply assembly, and a display substrate according to any one of claims 1 to 44;

46. The display device of claim 45, wherein the display device is an active matrix light emitting diode AMOLED display device.