CN113257773A - 半导体设备封装和其制造方法 - Google Patents

半导体设备封装和其制造方法 Download PDF

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CN113257773A
CN113257773A CN202011037599.8A CN202011037599A CN113257773A CN 113257773 A CN113257773 A CN 113257773A CN 202011037599 A CN202011037599 A CN 202011037599A CN 113257773 A CN113257773 A CN 113257773A
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emitting device
package
carrier
disposed
circuit layer
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谢孟伟
康国章
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本公开关于一种半导体设备封装及其制造方法。所述半导体设备封装包含第一电路层、第一发射设备和第二发射设备。所述第一电路层具有第一表面和与所述第一表面相对的第二表面。所述第一发射设备安置在所述第一电路层的所述第二表面上。所述第一发射设备具有面向所述第一电路层的第一表面和与所述第一表面相对的第二表面。所述第一发射设备具有安置在所述第一发射设备的所述第一表面上的第一导电图案。所述第二发射设备安置在所述第一发射设备的所述第二表面上。所述第二发射设备具有面向所述第一发射设备的所述第二表面的第一表面和与所述第一表面相对的第二表面。所述第二发射设备具有安置在所述发射设备的所述第二表面上的第二导电图案。所述第一发射设备的热膨胀系数CTE大于所述第二发射设备的CTE。

Description

半导体设备封装和其制造方法
技术领域
本公开涉及一种半导体设备封装和其制造方法,并且更具体地涉及一种包含天线的半导体设备封装和其制造方法。
背景技术
如蜂窝电话等无线通信设备通常包含用于发射和接收射频(RF)信号的天线。可比较地,无线通信设备包含天线和通信模块,所述天线和所述通信模块各自安置在电路板的不同部分上。在可比较的方法下,天线和通信模块单独制造并且在置于电路板上之后电连接在一起。因此,两个组件都可能引起单独的制造成本。此外,可能难以减小无线通信设备的大小以获得适当紧凑的产品设计。为了降低成本并减小封装大小,提供了封装内天线(Antenna-in-Package,AiP)方法。通常,在AiP系统中普遍使用有机衬底。然而,由于有机衬底的工艺限制,难以实现细间距(小于15/15μm),并且有机衬底相对较厚,这将阻碍AiP系统的小型化。
发明内容
根据本公开的一些实施例,一种半导体设备封装包含第一电路层、第一发射设备和第二发射设备。所述第一电路层具有第一表面和与所述第一表面相对的第二表面。所述第一发射设备安置在所述第一电路层的所述第二表面上。所述第一发射设备具有面向所述第一电路层的第一表面和与所述第一表面相对的第二表面。所述第一发射设备具有安置在所述第一发射设备的所述第一表面上的第一导电图案。所述第二发射设备安置在所述第一发射设备的所述第二表面上。所述第二发射设备具有面向所述第一发射设备的所述第二表面的第一表面和与所述第一表面相对的第二表面。所述第二发射设备具有安置在所述发射设备的所述第二表面上的第二导电图案。所述第一发射设备的热膨胀系数(CTE)大于所述第二发射设备的CTE。在一些实施例中,所述CTE可以是等效CTE。
根据本公开的一些实施例,一种半导体设备封装包含堆积电路、第一发射设备和第二发射设备。所述堆积电路具有第一表面和与所述第一表面相对的第二表面。所述第一发射设备安置在所述堆积电路的所述第二表面上。所述第一发射设备具有面向所述堆积电路的第一表面和与所述第一表面相对的第二表面。所述第一发射设备具有安置在所述第一发射设备的所述第一表面上的第一导电图案。所述第二发射设备安置在所述第一发射设备的所述第二表面上。所述第二发射设备具有面向所述第一发射设备的所述第二表面的第一表面和与所述第一表面相对的第二表面。所述第二发射设备具有安置在所述发射设备的所述第二表面上的第二导电图案。所述第二发射设备的厚度大于所述第一发射设备的厚度。
根据本公开的一些实施例,一种制造光学模块的方法包含:(a)提供具有第一导电图案的第一发射设备;(b)提供多个第二发射设备,每个第二发射设备具有第二导电图案;以及(c)将所述第二发射设备附接在所述第一发射设备上。
附图说明
图1A展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图1B展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图2A展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图2B展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图3展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图4展示了根据本公开的一些实施例的半导体设备封装的横截面视图。
图5A、图5B、图5C、图5D和图5E展示了根据本公开的一些实施例的半导体制造方法。
贯穿附图和详细描述,使用共同的附图标记来指示相同或类似的组件。根据以下结合附图进行的详细描述将容易理解本公开。
具体实施方式
图1A展示了根据本公开的一些实施例的半导体设备封装1A的横截面视图。半导体设备封装1A包含载体10a、10b,电路层11、13、14,互连结构12a、12b,电子组件15,电触点16,以及封装体17、18和19。
在一些实施例中,载体10a可以是或包含玻璃衬底。在一些实施例中,载体10a可以是或包含具有安置在其上的一或多个发射组件(例如,天线、发光设备、传感器等)的发射设备。载体10a可以包含一或多个导电衬垫、一或多条迹线以及一或多个互连(例如,一或多个通孔)。在一些实施例中,载体10a可以包含透明材料。在一些实施例中,载体10a可以包含不透明材料。载体10a包含介电常数(Dk)小于大约5的材料。载体10a包含Dk小于大约3的材料。载体10a包含损耗角正切或耗散因子(Df)小于大约0.005的材料。载体10a包含损耗角正切或Df小于大约0.003的材料。
载体10a具有表面101a、与表面101a相对的表面102a以及在表面101a与表面102a之间延伸的侧面103a。与有机衬底相比,玻璃载体的厚度较容易控制,这可以促进半导体设备封装1A的小型化。在一些实施例中,载体10a的厚度等于或小于约400μm。例如,载体10a的厚度处于约50μm到约400μm的范围内。例如,载体10a的厚度处于约100μm到约300μm的范围内。在一些实施例中,载体10a的热膨胀系数(CTE)处于约0.5到约13的范围内。在一些实施例中,载体10a的CTE处于约3.6到约8.5的范围内。
导电层10p安置在载体10a的表面102a上。在一些实施例中,导电层10p限定图案化天线,如定向天线、全向天线、天线阵列。例如,导电层10p限定贴片天线。导电层10p是或包含如金属或金属合金等导电材料。导电材料的实例包含金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、一或多种其它金属或一或多种合金或其中两种或两种以上的组合。在一些实施例中,导电层10p可以由一或多个发光设备或传感器代替。
载体10b安置在载体10a的表面101a上。载体10b具有背离载体10a的表面101b、与表面101b相对的表面102b以及在表面101b与表面102b之间延伸的侧面103b。载体10b的表面102b通过粘性层10h(例如,胶带、胶水或管芯附接膜(DAF))连接到载体10a的表面101a。载体10b与载体10a间隔开。例如,在载体10a的表面101a与载体10b的表面102b之间存在距离(例如,粘性层10a的厚度)。在一些实施例中,载体10a的侧面103a和载体10b的侧面103b是非共面的或不连续的。例如,载体10a的侧面103a从载体10b的侧面103b凹入。例如,载体10a的宽度小于载体10b的宽度。在一些实施例中,载体10a的侧面103a的粗糙度小于载体10b的侧面103b的粗糙度。在一些实施例中,载体10b和电路层11的一部分(例如,电路层的邻近载体10b的导电层)也可以被称为第一发射设备。
在一些实施例中,载体10b和载体10a的厚度可以相同。可替代地,载体10b和载体10a的厚度可以不同。例如,载体10a的厚度可以等于、大于或小于载体10b的厚度。在一些实施例中,载体10a的厚度和载体10b的厚度的总和可以等于或小于约400μm。例如,载体10a的厚度可以为约350μm并且载体10b的厚度可以为约50μm。例如,载体10a的厚度可以为约300μm并且载体10b的厚度可以为约100μm。例如,载体10a的厚度可以为约250μm并且载体10b的厚度可以为约150μm。
在一些实施例中,载体10b和载体10a可以包含同一种材料。可替代地,载体10b和载体10a可以包含不同的材料。在一些实施例中,载体10b的CTE高于载体10a的CTE。在一些实施例中,载体10b的硬度高于载体10a的硬度。通过将CTE和硬度相对较高的载体10b安置在载体10a与电路层11之间,可以减轻由于载体10b与封装体17(或封装体18)之间的CTE不匹配引起的翘曲问题。在一些实施例中,载体10a的Dk低于载体10b的Dk。通过选择Dk相对较低的载体10a,可以提高天线方向图(例如,导电层10p)的电性能。这将增加设计半导体设备封装1A的灵活性。
封装体17安置在载体10b的表面102b上。封装体17覆盖载体10a和导电层10p。封装体17覆盖载体10a的表面102a和侧面103a以及粘性层10h的侧面。在一些实施例中,封装体17具有与载体10b的侧面103b基本上共面的侧面173。载体10a的侧面103a从封装体17的侧面173凹入。例如,载体10a的侧面103a与封装体17的侧面173之间存在距离。在一些实施例中,封装体17包含环氧树脂,所述环氧树脂包含填料、模制原料(例如,环氧树脂模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料或其组合。
电路层11(或堆积电路)具有背离载体10b的表面111、与表面111相对的表面112和在表面111与表面112之间延伸的侧面113。电路层11安置在载体10b的表面101b上。在一些实施例中,电路层11与载体10b接触。可替代地,电路层11可以通过粘性层(例如,DAF)连接到载体10b。在一些实施例中,电路层11的侧面113与载体10b的侧面103b基本上共面。
电路层11包含一或多个导电层(例如,重新分布层RDL)11c和一或多个介电层11d。导电层11c的一部分被介电层11d覆盖或包封,而导电层11c的另一部分从介电层11d暴露以提供电连接。在一些实施例中,导电层11c的暴露部分具有面向载体10b并且与载体10b的表面101b接触的表面。在一些实施例中,导电层11c可以是或包含一或多个天线方向图、发光设备、传感器等。
在一些实施例中,介电层11d可以包含预浸渍复合纤维(例如,预浸料)、硼磷硅酸盐玻璃(BPSG)、氧化硅、氮化硅、氮氧化硅、未掺杂的硅酸盐玻璃(USG)、其中两种或两种以上的任何组合等。预浸料的实例可以包含但不限于通过堆叠或层压多种预浸渍材料/片材而形成的多层结构。在一些实施例中,根据设计规格,可以存在任何数量的导电层11c和介电层11d。在一些实施例中,导电层11c由Au、Ag、Cu、Pt、Pd或其合金形成或包含Au、Ag、Cu、Pt、Pd或其合金。
一或多个互连结构12a(例如,导电柱或导电元件)安置在电路层11的表面111上。互连结构12a电连接到电路层11(即,电连接到从介电层11d暴露的导电层11c)。在一些实施例中,互连结构12a限定天线结构。互连结构12a是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd或其合金。
封装体18安置在电路层11的表面111上。封装体18覆盖互连结构12a。在一些实施例中,封装体18具有与电路层11的侧面113基本上共面的侧面183。在一些实施例中,封装体18包含环氧树脂,所述环氧树脂包含填料、模制原料(例如,环氧树脂模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料或其组合。
电路层13(或堆积电路)安置在封装体18上。电路层13具有介电层13d和导电层13c。在一些实施例中,介电层13d和介电层11d可以包含同一种材料。可替代地,介电层13d和介电层11d可以包含不同的材料。电路层13电连接到互连结构12a。例如,电路层13的导电层13c与互连结构12a接触。可替代地,在导电层13c与互连结构12a之间安置有晶种层。在一些实施例中,根据设计规格,可以存在任何数量的导电层13c和介电层13d。
一或多个互连结构12b(例如,导电柱或导电元件)安置在电路层13的背离电路层11的表面上。互连结构12b电连接到电路层13。互连结构12b是或包含如金属或金属合金等导电材料。导电材料的实例包含Au、Ag、Cu、Pt、Pd或其合金。
封装体19安置在电路层13的背离电路层11的表面上。封装体19覆盖互连结构12b和电子组件15。在一些实施例中,封装体19具有与电路层13的侧面基本上共面的侧面。在一些实施例中,封装体19包含环氧树脂,所述环氧树脂包含填料、模制原料(例如,环氧树脂模制原料或其它模制原料)、聚酰亚胺、酚类化合物或材料、包含分散在其中的硅树脂的材料或其组合。
电路层14(或堆积电路)安置在封装体19上。电路层14具有介电层14d和导电层14c。在一些实施例中,介电层14d和介电层11d可以包含同一种材料。可替代地,介电层14d和介电层11d可以包含不同的材料。导电层14c电连接到互连结构12b。例如,电路层14的导电层14c与互连结构12b接触。可替代地,在导电层14c与互连结构12b之间安置有晶种层。在一些实施例中,根据设计规格,可以存在任何数量的导电层14c和介电层14d。
电子组件15安置在电路层13的背离电路层11的表面上。电子组件15的主动表面面向电路层13。电子组件15通过电触点(例如,焊球)电连接到电路层13(例如,电连接到导电层13c),并且电连接可以通过例如倒装芯片技术实现。电子组件15可以是如集成电路(IC)芯片或管芯等有源电子组件。
电触点16安置在从介电层14d暴露的导电层14c上。在一些实施例中,电触点16可以包含焊料或一或多种其它适合的材料。
在一些实施例中,载体10a的侧面103a可以与载体10b的侧面103b共面。例如,载体10a的侧面103a从封装体17暴露。此类结构可以通过以下形成:(i)提供玻璃晶片;(ii)在所述玻璃晶片上形成电路层11、13、14,互连结构12a、12b,和封装体17、18、19,以及电子组件15;以及(iii)穿过电路层11、13、14,封装体17、18、19和载体晶片执行单切。为了满足对天线结构的性能的要求,玻璃晶片应当选择Dk相对较低(例如,小于5)的材料。然而,Dk相对较低的玻璃晶片的CTE也将相对较低(例如,小于13)。由于玻璃晶片与封装体17之间存在CTE不匹配(例如,封装体的CTE通常大于20),所以将发生翘曲问题。随着玻璃晶片的大小增加,翘曲问题变得严重,这可能使玻璃晶片破裂或损坏。
根据图1A中所示的实施例,载体10a的侧面103a从载体10b的侧面103b凹入。此类结构可以通过以下形成(稍后将描述详细操作):(i)对玻璃晶片执行单切以将玻璃晶片分成多个玻璃载体(例如,图1A中所示的载体10a);(ii)形成载体10b,电路层11、13、14,互连结构12a、12b,和封装体17、18、19,以及电子组件15;(iii)通过粘性层10h将载体10a附接在载体10b上。因为经过分割的玻璃载体的大小远小于玻璃晶片的大小,所以可以显著减轻翘曲问题。另外,因为不必选择CTE较高的载体10a的材料来接近封装体17的CTE,所以可以将CTE较低(而且Dk较低)的材料选择为载体10a。这将增强半导体设备封装1A的天线结构的性能。此外,也可以减小载体10a的厚度,这将促进半导体设备封装1A的小型化。
图1B展示了根据本公开的一些实施例的半导体设备封装1B的横截面视图。半导体设备封装1B类似于图1A中所示的半导体设备封装1A,并且其之间的差别之一在于,在图1B中,粘性层10h的宽度大于载体10a的宽度。例如,粘性层10h的侧面与载体10b的侧面103b基本上共面。例如,载体10a的侧面103a从粘性层10h的侧面凹入。这将提高在制造工艺期间使载体10a与载体10b对准的准确度。
图2A展示了根据本公开的一些实施例的半导体设备封装2A的横截面视图。半导体设备封装2A类似于图1A中所示的半导体设备封装1A,并且下文描述了其之间的差别。
电子组件15安置在电路层13的背离电路层11的表面上。电子组件15的背面表面通过粘性层15a(例如,DAF)连接到电路层13。电子组件15通过互连结构15c(例如,Cu柱)电连接到电路层14(例如,电连接到导电层14c)。
图2B展示了根据本公开的一些实施例的半导体设备封装2B的横截面视图。半导体设备封装2B类似于图2A中所示的半导体设备封装2A,并且其之间的差别之一在于,在图2B中,粘性层10h的宽度大于载体10a的宽度。例如,粘性层10h的侧面与载体10b的侧面103b基本上共面。例如,载体10a的侧面103a从粘性层10h的侧面凹入。这将提高在制造工艺期间使载体10a与载体10b对准的准确度。
图3展示了根据本公开的一些实施例的半导体设备封装3的横截面视图。半导体设备封装3类似于图1B中所示的半导体设备封装1B,并且下文描述了其之间的差别。
半导体设备封装3可以包含两个部分3A和3B。部分3A包含介电层13d1、封装体19、电子组件15、电路层14、互连结构12b和电触点16。部分3B包含介电层13d2,封装体17、18,电路层11,载体10a和10b。部分3A和部分3B可以单独地制造并且然后通过电触点31s(例如,焊球)彼此连接。这将提高半导体设备封装3的成品率。在一些实施例中,可以在部分3A与部分3B之间安置底部填料31h以覆盖电触点31s。在一些实施例中,部分3A的宽度与部分3B的宽度相同。可替代地,根据设计规格,部分3A的宽度可以大于或小于部分3B的宽度。
图4展示了根据本公开的一些实施例的半导体设备封装4的横截面视图。半导体设备封装4类似于图3中所示的半导体设备封装3,并且下文描述了其之间的差别。
半导体设备封装4可以包含两个部分4A和4B。部分4B类似于图3中的半导体设备封装3的部分3B。部分4A类似于图3中的半导体设备封装3的部分3A,除了在图4中的半导体设备封装4的部分4A中,电子组件15安置在电路层14的面向介电层13d2的表面上之外。电子组件15的背面表面通过粘性层15a连接到电路层14的表面。电子组件15的主动表面通过互连结构15c(例如,Cu柱)电连接到导电层13c。在一些实施例中,部分4A的宽度与部分4B的宽度相同。可替代地,根据设计规格,部分4A的宽度可以大于或小于部分4B的宽度。
图5A、图5B、图5C、图5D和图5E展示了根据本公开的一些实施例的半导体制造方法。在一些实施例中,可以使用图5A、图5B、图5C、图5D和图5E中的方法来制造图1A中的半导体设备封装1A。
参照图5A,提供载体10b。衬底10b可以属于晶片类型、面板类型或条带类型。在载体10b上形成包含一或多个导电层11c和一或多个介电层11d的电路层11。在电路层11上形成互连结构12a以电连接到电路层11(例如,连接到导电层11c的从介电层11d暴露的部分)。介电层11d通过例如但不限于光刻技术形成。在一些实施例中,互连结构12a可以通过例如但不限于电镀技术形成。
然后,在电路层11上形成封装体18以覆盖互连结构12a。在一些实施例中,封装体18可以形成为完全覆盖互连结构12a。在一些实施例中,封装体18通过例如传递模制技术、压缩技术或任何其它适合的技术形成。
参照图5B,通过例如研磨或任何其它适合的工艺去除载体10b的一部分以减小载体10b的厚度。在一些实施例中,从载体10b背离电路层11的表面执行减薄操作。在一些实施例中,在减薄操作之后,载体10b的厚度等于或小于200μm。例如,载体10b的厚度等于或小于100μm。例如,载体10b的厚度等于或小于50μm。
参照图5C,将封装体18安置在载体59上。可以通过粘性层(例如,胶带或胶水)将封装体18附接到载体59。在载体10b上安置其上具有导电层10p的载体10a。在一些实施例中,载体10a通过粘性层10h附接到载体10b。在一些实施例中,载体10a可以通过执行单切以将玻璃晶片分成包含载体10a的多个玻璃载体来形成。在一些实施例中,载体10a的厚度等于或大于200μm。例如,载体10a的厚度等于或大于300μm。例如,载体10a的厚度等于或大于350μm。
然后,在载体10b上形成封装体17以覆盖载体10a和导电层10p。在一些实施例中,封装体17通过例如传递模制技术、压缩技术或任何其它适合的技术形成。因为载体10b相对较薄(与载体10a相比),所以即使载体10b可以属于晶片类型、面板类型或条带类型,也可以减轻由载体10b与封装体17之间的CTE不匹配引起的翘曲问题。另外,因为载体10a在将载体晶片分成包含载体10a的多个载体之后连接到载体10b,所以经过分割的载体的大小远小于载体晶片的大小。因此,可以显著减轻由封装体17与载体10a之间的CTE不匹配引起的翘曲问题。
参照图5D,从封装体18去除载体59。通过例如研磨或任何其它适合的工艺去除封装体18的一部分以暴露互连结构12a。在封装体18上形成包含一或多个导电层13c和一或多个介电层13d的电路层13并且将所述电路层电连接到从封装体18暴露的互连结构12a。然后,在电路层13上安置电子组件15。在一些实施例中,通过例如倒装芯片或任何其它适合的工艺将电子组件15的主动表面连接到电路层13。
参照图5E,在电路层13上形成互连结构12b并且将所述互连结构电连接到电路层13。在一些实施例中,互连结构12b可以通过例如但不限于电镀技术形成。在电路层13上形成封装体19以覆盖互连结构12b和电子组件15。在一些实施例中,封装体19可以形成为完全覆盖互连结构12b,并且然后通过例如研磨或任何其它适合的技术去除封装体19的一部分以暴露互连结构12b的顶部部分以实现电连接。在一些实施例中,封装体19通过例如传递模制技术、压缩技术或任何其它适合的技术形成。
在封装体18上形成包含一或多个导电层14c和一或多个介电层14d的电路层14并且将所述电路层电连接到从封装体18暴露的互连结构12b。介电层14d通过例如但不限于光刻技术形成。然后,在从介电层14d暴露的导电层14c上安置电触点16。
如本文所使用的,术语“基本上”、“基本”、“大约”和“约”用于表示和解释小的变化。例如,当与数值结合使用时,所述术语可以指代小于或等于所述数值的±10%,如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%或小于或等于±0.05%的变化范围。作为另一个实例,膜或层的厚度“基本上一致”可以指代小于或等于膜或层的平均厚度的±10%,如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%或小于或等于±0.05%的标准偏差。术语“基本上共面”可以指两个表面沿同一平面定位的位置差处于数微米内,如沿同一平面定位的位置差处于40μm内、30μm内、20μm内、10μm内或1μm内。如果两个表面或组件之间的角度为例如90°±10°,如±5°、±4°、±3°、±2°、±1°、±0.5°、±0.1°或±0.05°,则可以认为所述两个表面或组件“基本上垂直”。当与事件或情形结合使用时,术语“基本上”、“基本”、“大约”和“约”可以指代事件或情形精确发生的情况以及事件或情形接近发生的情况。
如本文所使用的,除非上下文另有明确指示,否则单数术语“一个/一种(a/an)”和“所述(the)”可以包含复数指代物。在一些实施例的描述中,设置在一个组件“上”或“之上”的另一个组件可以涵盖前一组件直接位于后一组件上(例如,与其物理接触)的情况以及在前一组件与后一组件之间定位有一或多个中间组件的情况。
如本文所使用的,术语“导电的(conductive)”、“导电的(electricallyconductive)”以及“电导率(electrical conductivity)”指代输送电流的能力。导电材料通常表示对电流流动几乎没有或没有阻碍的那些材料。电导率的一种度量是西门子每米(S/m)。通常,导电材料是电导率大于约104S/m,如至少105S/m或至少106S/m的导电材料。材料的电导率有时可能随温度变化。除非另有说明,否则材料的电导率是在室温下测量的。
另外,量、比率和其它数值在本文中有时以范围格式呈现。应当理解的是,此类范围格式是为了方便和简洁而使用的,并且应该灵活地理解为不仅包含明确指定为范围的界限的数值,而且还包含所述范围内涵盖的所有单独数值或子范围,如同每个数值和子范围被明确指定一样。
虽然已经参考本公开的具体实施例描述和展示了本公开,但是这些描绘和图示不限制本公开。本领域技术人员应当理解,在不脱离如由权利要求限定的本公开的精神和范围的情况下,可以作出各种改变并且可以在实施例内取代等效元件。图示可能不一定按比例绘制。由于制造工艺的变量等,本公开中的艺术再现与实际装置之间可能存在区别。可能存在未具体展示的本公开的其它实施例。说明书和附图应被视为是说明性的而非限制性的。可以作出修改以使特定情况、材料、物质构成、方法或工艺适于本公开的目标、精神和范围。所有此类修改均旨在落入所附权利要求的范围内。虽然已经参考以特定顺序执行的特定操作描述了本文所公开的方法,但是可以理解,可以在不脱离本公开的教导的情况下对这些操作进行组合、细分或重新排列以形成等效方法。因此,除非本文明确指出,否则操作的顺序和分组并不是本公开的限制。

Claims (20)

1.一种半导体设备封装,其包括:
第一电路层,所述第一电路层具有第一表面和与所述第一表面相对的第二表面;
第一发射设备,所述第一发射设备安置在所述第一电路层的所述第二表面上,所述第一发射设备具有面向所述第一电路层的第一表面和与所述第一表面相对的第二表面,所述第一发射设备具有安置在所述第一发射设备的所述第一表面上的第一导电图案;以及
第二发射设备,所述第二发射设备安置在所述第一发射设备的所述第二表面上,所述第二发射设备具有面向所述第一发射设备的所述第二表面的第一表面和与所述第一表面相对的第二表面,所述第二发射设备具有安置在所述发射设备的所述第二表面上的第二导电图案,
其中所述第一发射设备的热膨胀系数CTE大于所述第二发射设备的CTE。
2.根据权利要求1所述的半导体设备封装,其中所述第一电路层的侧面与所述第一发射设备的侧面基本上共面。
3.根据权利要求1所述的半导体设备封装,其中所述发射设备的侧面从所述第一发射设备的侧面凹入。
4.根据权利要求1所述的半导体设备封装,其中所述第一发射设备的宽度小于所述第二发射设备的宽度。
5.根据权利要求1所述的半导体设备封装,其中所述第二发射设备的厚度大于所述第一发射设备的厚度。
6.根据权利要求1所述的半导体设备封装,其中所述第二发射设备的侧面的粗糙度小于所述第一发射设备的侧面的粗糙度。
7.根据权利要求1所述的半导体设备封装,其进一步包括粘性层,所述粘性层安置在所述第一发射设备的所述第二表面与所述第二发射设备的所述第一表面之间。
8.根据权利要求7所述的半导体设备封装,其中所述粘性层的侧面与所述第二发射设备的侧面基本上共面。
9.根据权利要求7所述的半导体设备封装,其中所述粘性层的侧面与所述第一发射设备的侧面基本上共面。
10.根据权利要求1所述的半导体设备封装,其中所述第一发射设备包含第一玻璃载体并且所述第二发射设备包含第二玻璃载体。
11.根据权利要求10所述的半导体设备封装,其中所述第一玻璃载体的CTE大于所述第二玻璃载体的CTE。
12.根据权利要求1所述的半导体设备封装,其进一步包括:
第一组导电柱,所述第一组导电柱安置在所述第一电路层的所述第一表面上;以及
第一封装体,所述第一封装体安置在所述第一电路层的所述第一表面上并且覆盖所述第一组导电柱。
13.根据权利要求12所述的半导体设备封装,其进一步包括:
第二电路层,所述第二电路层安置在所述第一封装体上;
第二组导电柱,所述第二组导电柱安置在所述第二电路层上;以及
第二封装体,所述第二封装体安置在所述第二电路层上并且覆盖所述第二组导电柱。
14.根据权利要求13所述的半导体设备封装,其进一步包括电子组件,所述电子组件安置在所述第二电路层上,所述电子组件具有面向所述第二电路层的主动表面并且电连接到所述第二电路层。
15.一种半导体设备封装,其包括:
堆积电路,所述堆积电路具有第一表面和与所述第一表面相对的第二表面;
第一发射设备,所述第一发射设备安置在所述堆积电路的所述第二表面上,所述第一发射设备具有面向所述堆积电路的第一表面和与所述第一表面相对的第二表面,所述第一发射设备具有安置在所述第一发射设备的所述第一表面上的第一导电图案;以及
第二发射设备,所述第二发射设备安置在所述第一发射设备的所述第二表面上,所述第二发射设备具有面向所述第一发射设备的所述第二表面的第一表面和与所述第一表面相对的第二表面,所述第二发射设备具有安置在所述发射设备的所述第二表面上的第二导电图案,
其中所述第二发射设备的厚度大于所述第一发射设备的厚度。
16.根据权利要求15所述的半导体设备封装,其进一步包括包封料,所述包封料包封所述第二发射设备的侧面并且暴露所述第一发射设备的侧面。
17.根据权利要求15所述的半导体设备封装,其进一步包括粘性层,所述粘性层安置在所述第一发射设备的所述第二表面与所述第二发射设备的所述第一表面之间。
18.一种制造光学模块的方法,所述方法包括:
(a)提供具有第一导电图案的第一发射设备;
(b)提供多个第二发射设备,每个第二发射设备具有第二导电图案;以及
(c)将所述第二发射设备附接在所述第一发射设备上。
19.根据权利要求18所述的方法,在操作(c)之前,其进一步包括使所述第一导电图案与所述第二导电图案对准。
20.根据权利要求18所述的方法,其进一步包括形成封装体以覆盖所述第二发射设备的侧面。
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