CN113256612A - Wafer map identification method, device and readable medium - Google Patents

Wafer map identification method, device and readable medium Download PDF

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CN113256612A
CN113256612A CN202110682913.6A CN202110682913A CN113256612A CN 113256612 A CN113256612 A CN 113256612A CN 202110682913 A CN202110682913 A CN 202110682913A CN 113256612 A CN113256612 A CN 113256612A
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identified
wafer
wafer map
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similarity
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陈培培
王政航
马苗苗
吴大海
黄涛
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Yangtze Memory Technologies Co Ltd
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Abstract

The application provides a wafer map identification method, a wafer map identification device and a readable medium. The wafer map comprises a pattern formed by a plurality of defect crystal grains distributed in the wafer, and the wafer map identification method comprises the following steps: forming a set to be identified according to the position number of the defective crystal grain in the wafer; determining a plurality of similarities between a set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect crystal grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by the plurality of defect crystal grains distributed in the reference wafer; and in response to the maximum value of the similarity degrees being larger than a preset similarity threshold, determining the category of the wafer map as the category of the reference wafer map corresponding to the maximum value. The wafer map identification method, the wafer map identification device and the readable medium can improve the wafer map identification efficiency and reduce the input of labor cost. In addition, the method is simple in algorithm and strong in interpretability.

Description

Wafer map identification method, device and readable medium
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a wafer map recognition method, apparatus and readable medium.
Background
Wafer testing (wafer sort) is a very important test in one step after the wafer fabrication is complete. During testing, it is necessary to test the electrical capability and circuit function of each die on the wafer. And matching and identifying a wafer map (wafer map) formed by defect grain distribution in the detected wafer and a reference wafer map (pattern), thereby carrying out different grading on the wafer.
In conventional methods, identifying wafer maps relies mostly on manual inspection. Such an analysis method is cumbersome and time consuming, and the labor cost is high. As production progresses, a large amount of wafer throughput brings a large amount of wafer map data to be analyzed. Therefore, a wafer map recognition method is desired to solve at least some of the above technical problems.
Disclosure of Invention
The application provides a wafer map identification method. The wafer map comprises a pattern formed by a plurality of defect crystal grains distributed in the wafer, and the wafer map identification method comprises the following steps: forming a set to be identified according to the position number of the defective crystal grain in the wafer; determining a plurality of similarities between a set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect crystal grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by the plurality of defect crystal grains distributed in the reference wafer; and in response to the maximum value of the similarity degrees being larger than a preset similarity threshold, determining the category of the wafer map as the category of the reference wafer map corresponding to the maximum value.
In some embodiments, the step of forming the set to be identified according to the position number of the defect die in the wafer may include: forming a subset to be identified according to the position number of the defective crystal grain of each wafer map in the plurality of wafer maps, thereby forming a plurality of subsets to be identified; and calculating a union set of the plurality of subsets to be identified to form a set to be identified.
In some embodiments, the step of determining a plurality of similarities between the set to be identified and the plurality of reference sets may comprise: and determining the similarity between the set to be identified and each reference set in the plurality of reference sets by a Jacard similarity algorithm so as to determine a plurality of similarities.
In some embodiments, determining a similarity between the set to be identified and each of the plurality of reference sets by the jaccard similarity algorithm to determine the plurality of similarities may include: determining a first number of position numbers simultaneously contained in the set to be identified and the reference set; determining a second number of position numbers contained in the set to be identified and not contained in the reference set; determining a third number of position numbers contained in the reference set and not contained in the set to be identified; and calculating the similarity based on the first number, the second number, and the third number.
In some embodiments, the similarity is a ratio of the first number to a fourth number, wherein the fourth number is a sum of the first number, the second number, and the third number.
In some embodiments, after the step of sequentially determining a plurality of similarities between the set to be identified and the plurality of reference sets, the method may further comprise: and outputting a prompt for manually identifying the category of the wafer map in response to the fact that the maximum value of the similarity is smaller than a preset similarity threshold.
The application also provides a wafer map recognition device. The wafer map recognition device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores a program executable by the at least one processor, the program being executable by the at least one processor, the at least one processor being configured to: forming a set to be identified according to the position number of the defective crystal grain in the wafer; determining a plurality of similarities between a set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect crystal grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by the plurality of defect crystal grains distributed in the reference wafer; and determining the category of the wafer map as the category of the reference wafer map corresponding to the maximum value in response to the maximum value in the plurality of similarity being greater than a preset similarity threshold; the wafer map includes a pattern formed by a plurality of defective dies distributed in the wafer.
In some embodiments, the at least one processor may be further configured to: forming a subset to be identified according to the position number of the defective crystal grain of each wafer map in the plurality of wafer maps, thereby forming a plurality of subsets to be identified; and calculating a union set of the plurality of subsets to be identified to form a set to be identified.
In some embodiments, the at least one processor may be further configured to: and determining the similarity between the set to be identified and each reference set in the plurality of reference sets by a Jacard similarity algorithm so as to determine a plurality of similarities.
In some embodiments, the at least one processor may be further configured to: determining a first number of position numbers simultaneously contained in the set to be identified and the reference set; determining a second number of position numbers contained in the set to be identified and not contained in the reference set; determining a third number of position numbers contained in the reference set and not contained in the set to be identified; and calculating the similarity based on the first number, the second number, and the third number.
The present application also provides a non-transitory computer readable medium storing a computer program. The computer program is for causing a computer to execute a wafer map recognition method according to any one of the embodiments.
According to the wafer map identification method, the wafer map identification device and the readable medium, the wafer map to be identified and the reference wafer map are identified and matched through the similarity calculation method, the wafer map identification efficiency can be improved, and the input of labor cost can be reduced. In addition, the algorithm of the method is simple, the interpretability is strong, and the algorithm can be further simplified because the participation data amount is small, and excessive training sets and testing sets are not needed.
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Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a flow chart of a wafer map identification method according to an embodiment of the present application;
fig. 2 is a schematic diagram of a wafer after wafer testing according to an embodiment of the present application.
Fig. 3 is a schematic diagram of a reference wafer map according to an embodiment of the present application;
fig. 4 is a schematic diagram of a wafer map to be identified and a corresponding reference wafer map according to an embodiment of the present application; and
fig. 5 is a schematic structural diagram of a wafer map recognition apparatus suitable for implementing the embodiment of the present application.
Detailed Description
For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.
The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.
This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1 is a flow chart of a wafer map identification method 1000 according to an embodiment of the present application. The wafer map recognition method 1000 includes steps S110 to S130 shown in fig. 1. The steps S110 to S130 of the wafer map recognition method 1000 will be described in detail with reference to the drawings.
And S110, forming a set to be identified according to the position number of the defective crystal grain in the wafer.
In step S110, fig. 2 is a schematic diagram of the wafer 10 after the wafer test according to the embodiment of the present disclosure. As shown in fig. 2, after being subjected to complicated process processes such as a thin film process, a patterning process, and a doping process, the wafer 10 may include a plurality of dies (die)1 to N formed with semiconductor devices, and the plurality of dies 1 to N are arranged in a row on the wafer 10. Illustratively, the wafer 10 may include 1072 dice, however, it should be understood that the number of dice included in the wafer 10 may vary (several hundred to several ten thousand) depending on the difference in the sizes of the dice, and the number of dice in the wafer 10 is not particularly limited by the present application. The wafer 10 may be divided into a plurality of dies 1-N in the wafer 10 in a subsequent dicing and packaging process, and packaged in a protective case to form an independent chip (chip).
After the wafer fabrication is completed and before the dicing process, the electrical capability and circuit capability of each die 1-N in the wafer 10 needs to be tested, and this testing process is called wafer test or in-wafer test (wafer sort). The wafer 10 goes through hundreds of different processes in the production cycle, and has the production characteristic of dozens of reflow, which causes great uncertainty in the yield of the finished product, and meanwhile, various manufacturing processes and environmental changes are easy to cause defects. Thus, during Wafer testing, test results (e.g., defective dies) are characterized at physical locations corresponding to the Wafer 10, and the resulting pattern is a Wafer map (Wafer map). In other words, the wafer map may include a pattern formed by a plurality of defective dies distributed in the wafer 10.
In some implementationsIn this manner, the N dies include a plurality of good dies and a plurality of defective dies arranged in a row on the wafer 10, and the position number of the leftmost die 1 in the first row may be labeled as D1Sequentially numbering the positions of the crystal grains in the wafer until the position number of the crystal grain N on the rightmost side in the last row is marked as DnThe position numbers of the plurality of crystal grains 1 to N in the wafer 10 form an N-dimensional vector. In other words, the n coordinates in the n-dimensional vector may sequentially correspond to the position numbers of the dies in one wafer 10. Further, the coordinate of the n-dimensional vector corresponding to the position number of the defective die in the wafer 10 is marked as 1, the coordinate of the n-dimensional vector corresponding to the position number of the qualified die in the wafer 10 is marked as 0, and the set a to be identified in the form of the n-dimensional vector is formed according to the position number of the defective die in the wafer 10.
As an example, the set to be identified a ═ 0,0,0,1,0,1,0,0 … … 0]Wherein, the position number in the set A to be identified is D1、D2、D3、D5、D7、D8And DnWhen the corresponding crystal grains are qualified crystal grains, the position number is D4And D6The corresponding grains are defective grains.
In some practical embodiments, a group of wafers (lot) are usually superimposed to form a wafer map and a plurality of reference wafer maps are identified and matched. Thus, a plurality of subsets to be identified may be formed according to the method described hereinabove, based on the location number of the defective die in each of the plurality of wafer maps.
In the following description, a wafer map formed by stacking three wafers as a group is taken as an example, where three subsets to be identified a 1-A3 are a1 ═ 0,0,0,1,0, 0,0 … … 0], a2 ═ 0,0,1,0,1,1,0,0, 0 … … 0], A3 ═ 0,0,1,0,1,1,0,0 … … 0, where the three subsets to be identified a 1-A3 are in the form of n-dimensional vectors, and coordinates in the three subsets to be identified a 1-A3 may have the same meaning as set a described above, and this application is not repeated herein.
Further, in the step of calculating the union of the three subsets to be identified a 1-A3 to form the set to be identified a', since the three subsets to be identified a 1-A3 are all in the form of n-dimensional vectors, the union of the three subsets to be identified a 1-A3 should also be in the form of n-dimensional vectors. And in the process of calculating the union of the three subsets to be identified a 1-A3, the corresponding coordinates in the three subsets to be identified a 1-A3 can be added, and it should be noted that when the sum of the added corresponding coordinates is greater than 1, the coordinate is marked as 1. The set to be recognized a' formed by the union of the three subsets to be recognized a1 to A3 is calculated as described above [0,0,0,1,1,1,1,0,0, 0 … … 0 ].
In some embodiments, the method may further include converting the set to be identified or the subset to be identified into a set form that does not include the position number of the qualified die. In other words, the set to be identified or the subset to be identified may be represented by an element that includes only the location number of the defective die. Specifically, the position number of the defective crystal grain corresponding to the coordinate 1 in the to-be-identified set or the to-be-identified subset and the mark (for example, 1) of the defective crystal grain are used as one element of the converted to-be-identified set. For example, in the step of converting the set a 'to be identified into a set form including no position number of qualified die, a' is [0,0,0,1,1,1,1,0,0, 0 … … 0]The position number of the defective crystal grain with the middle coordinate of 1 includes D4、D5、D6And D7Etc., so the set a' to be recognized can also be represented as a ═ D4,1),(D5,1),(D6,1),(D7,1),……]。
And S120, determining a plurality of similarities between the set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defective crystal grains in the corresponding reference wafer map.
In step S120, fig. 3 is a schematic diagram of a reference wafer map according to an embodiment of the present application. Specifically, fig. 3 shows first to ninth reference wafer maps. The reference wafer map can be used for representing the pattern distribution of defective crystal grains generated due to different traceable reasons such as human error, unclean equipment, chemical pollution and the like, the wafer map to be identified and a plurality of different reference wafer maps are identified and judged, the production line can be checked through the reasons corresponding to the reference wafer map, the defects are reduced by solving the related problems, and the method has great practical significance for improving the yield.
In some embodiments, a plurality of similarities between the set to be identified and the plurality of reference sets may be determined sequentially by, for example, a jaccard similarity algorithm. The Jaccard similarity can be expressed by a set operation of two sets X and Y. Specifically, the jaccard similarity J (X, Y) can be expressed as a proportion of the intersection element of the set X and the set Y in the union element of the set X and the set Y, and can be expressed by formula (1).
Figure BDA0003120636250000071
In practical applications, the Jacard similarity can also be represented by the number of sample relationships within set X and set Y. Specifically, J (X, Y) can be represented by formula (2).
Figure BDA0003120636250000072
Where P is the number of samples included in both set X and set Y, Q is the number of samples included in set X and not included in set Y, and M is the number of samples included in set Y and not included in set X. Further, P + Q + M may be understood as the number of union elements of the set X and the set Y, and P may be understood as the number of intersection elements of the set X and the set Y.
In this step, the similarity of the set a to be identified and each reference set can be determined using the jaccard similarity algorithm. Specifically, based on formula (2) of calculation of the vicard similarity, a first number of position numbers included in both the set a to be identified and the reference set R1 is first determined, and the first number may correspond to P in formula (2). In the case where the set a to be identified is in the form of an n-dimensional vector as described above, the reference set R1 may be identical in the number of coordinates of the set a to be identified and the defective crystal grain position numbering manner, and the number of coordinates simultaneously marked as 1 in the corresponding coordinates in the set a to be identified and the reference set R1 may be determined as the first number.
Further, a second number of position numbers contained in the set a to be identified and not contained in the reference set R1 is determined, which may correspond to Q in equation (2). Similarly, in the case where the set a to be identified is in the form of an n-dimensional vector as described above, the coordinates in the set a to be identified may be 1, and the number of the plurality of coordinates in the reference set R1, in which the corresponding coordinates are marked as 0, may be determined as the second number.
Further, a third number of position numbers contained in the reference set R1 and not contained in the set a to be identified is determined, which may correspond to M in equation (2). Similarly, in the case where the set a to be identified is in the form of an n-dimensional vector as described above, the coordinate in the reference set R1 may be 1, and the number of coordinates in the set a to be identified, whose corresponding coordinates are 0, may be determined as the third number.
It should be understood that in the case where the set to be identified is represented by an element including only the location numbers of defective dies, the first number, the second number, and the third number may be determined by determining the number of location numbers included in the set to be identified and the reference set. In other words, in the steps of determining the first number, the second number, and the third number, the position numbers of the qualified dies may not be involved.
Further, the similarity of the corresponding reference set R1 may be calculated based on the first number, the second number, and the third number. Specifically, based on equation (2), the similarity J1 may be a ratio of a first number to a fourth number, where the fourth number is a sum of the first number, the second number, and the third number. It is understood that the similarity between the set a to be identified and the reference sets R1-R9 of the reference wafer map shown in fig. 3 can be calculated in turn by the same method to determine the similarities J1-J9 corresponding to the reference sets R1-R9.
And S130, in response to the fact that the maximum value of the similarity degrees is larger than a preset similarity threshold value, determining the type of the wafer map as the type of the reference wafer map corresponding to the maximum value.
In step S130, the category of the wafer map may be determined as one of the categories of the nine reference wafer maps corresponding to the maximum value Max (R1 to R9) according to the fact that the maximum value Max (R1 to R9) of the similarity J1 to J9 corresponding to the reference sets R1 to R9 determined in step S120 is greater than the preset similarity threshold. Because the maximum value Max (R1-R9) in the similarity J1-J9 of the reference sets R1-R9 is determined according to the reference sets R1-R9 of the nine reference wafer maps, the reference wafer map corresponding to the wafer map can be identified, so that the reference wafer map can be used for judging the production reason of the wafer map to be identified, which is caused by the corresponding reference wafer map, and further related problems are solved to reduce defects and improve the production yield.
In this embodiment, the preset similarity threshold may be 60%. In other words, according to the similarity that the maximum value Max (R1-R9) of the J1-J9 is more than 60%, the type of the wafer map to be identified can be determined as the type of the reference wafer map corresponding to the maximum value Max (R1-R9). It should be understood that, the present application does not specifically limit the specific value of the similarity threshold, and the determination of the category of the reference wafer map corresponding to the category of the wafer map to be identified is performed when the similarity threshold is set to be greater than or equal to 60%, which is helpful for improving the accuracy of determining the category of the wafer map to be identified.
Fig. 4 is a schematic diagram of a wafer map to be identified and a corresponding reference wafer map according to an embodiment of the present application. As shown in fig. 4, in the process of performing the identification operation on the wafer map to be identified by using the method 1000, in the case that the similarity between the wafer map to be identified and the corresponding reference wafer map is 84.35%, 76.17%, 80.32% and 83.41%, respectively, the category of the wafer map to be identified is determined as the category of the corresponding reference wafer map. In addition, in the process of identifying and judging the categories of 38 groups of wafer maps, 33 groups of wafer maps and corresponding reference wafer maps can be successfully identified, and the accuracy of the wafer map identification method provided by the application can reach 86.84%.
In some embodiments, after step S120, the method 1000 may further include outputting a prompt for manual identification of the category of the wafer map in response to a maximum value of the plurality of similarity degrees being less than a preset similarity threshold. In this embodiment, in the process of performing the identification operation on the category of the wafer map to be identified by using the method 1000, for the case that the wafer map is complex, that is, because the maximum value of the multiple similarities between the wafer map to be identified and the multiple reference wafer maps is smaller than the preset similarity threshold, a prompt for manually identifying the category of the wafer map to be identified may be output. In other words, by manually identifying the type of the wafer map to be identified, another executable operation mode can be provided for wafer map identification.
According to the wafer map identification method provided by the application, the wafer map to be identified is identified and matched with the corresponding reference wafer map through the similarity calculation method, the wafer map identification efficiency can be improved, and the input of labor cost is reduced. In addition, the algorithm of the method is simple, the interpretability is strong, and the algorithm can be further simplified because the participation data amount is small, and excessive training sets and testing sets are not needed.
Fig. 5 is a schematic structural diagram of a wafer map recognition apparatus 100 suitable for implementing an embodiment of the present disclosure. It should be understood that the wafer map recognition apparatus shown in fig. 5 is only an example, and should not bring any limitation to the function and the scope of use of the embodiments of the present application.
As shown in fig. 5, the wafer map recognition apparatus 100 includes at least one processor 101 (e.g., CPU) that can perform various appropriate operations and processes according to a program stored in a Read Only Memory (ROM)102 or a program loaded from a storage section 106 into a Random Access Memory (RAM) 103. In the RAM 103, various programs and data necessary for the operation of the wafer map recognition apparatus 100 are also stored. The processor 101, the ROM 102, and the RAM 103 are connected to each other via a bus 104. An input/output (I/O) interface 105 is also connected to bus 104.
The following components are connected to the I/O interface 105: a storage portion 106 including a hard disk and the like; and a communication section 107 including a network interface card such as a LAN card, a modem, or the like. The communication section 107 performs communication processing via a network such as the internet. A driver 108 is also connected to the I/O interface 105 as necessary. A removable medium 109 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 108 as necessary, so that a computer program read out therefrom is mounted into the storage section 106 as necessary.
It will be understood by those skilled in the art that all or part of the steps in the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, where the program may be stored in a computer readable storage medium, and when executed, the program includes the following steps: and S110, forming a set to be identified according to the position number of the defective crystal grain in the wafer. And S120, determining a plurality of similarities between the set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by a plurality of defect grains distributed in the reference wafer. And S130, in response to the fact that the maximum value of the similarity degrees is larger than a preset similarity threshold value, determining the type of the wafer map as the type of the reference wafer map corresponding to the maximum value. The storage medium includes, for example, ROM/RAM, magnetic disks, optical disks, and the like.
The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (11)

1. A method for identifying a wafer map, wherein the wafer map comprises a pattern formed by a plurality of defective dies distributed in a wafer, the method comprising:
forming a set to be identified according to the position number of the defect crystal grain in the wafer;
determining a plurality of similarities between the set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect crystal grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by the plurality of defect crystal grains distributed in a reference wafer; and
and in response to the fact that the maximum value of the similarity degrees is larger than a preset similarity threshold value, determining the class of the wafer map as the class of the reference wafer map corresponding to the maximum value.
2. The identification method according to claim 1, wherein the step of forming the set to be identified according to the position number of the defective die in the wafer comprises:
forming a subset to be identified according to the position number of the defective crystal grain of each wafer map in the plurality of wafer maps, thereby forming a plurality of subsets to be identified; and
and calculating a union set of the plurality of subsets to be identified to form the set to be identified.
3. The identification method according to claim 1 or 2, wherein the step of determining a plurality of similarities between the set to be identified and a plurality of reference sets comprises:
determining a similarity between the set to be identified and each of the plurality of reference sets by a Jacard similarity algorithm to determine the plurality of similarities.
4. The identification method according to claim 3, wherein the step of determining the plurality of similarities by Jacard similarity algorithm determining the similarity between the set to be identified and each of the plurality of reference sets comprises:
determining a first number of position numbers simultaneously contained in the set to be identified and the reference set;
determining a second number of position numbers included in the set to be identified and not included in the reference set;
determining a third number of location numbers that are included in the reference set and not included in the set to be identified; and
calculating the similarity based on the first number, the second number, and the third number.
5. The identification method according to claim 4, wherein the similarity is a ratio of the first number to a fourth number, wherein the fourth number is a sum of the first number, the second number and the third number.
6. The identification method according to claim 1 or 5, characterized in that after the step of determining a plurality of similarities between said set to be identified and a plurality of reference sets, said method further comprises:
and outputting a prompt for manually identifying the category of the wafer map in response to the fact that the maximum value of the similarity degrees is smaller than a preset similarity threshold value.
7. A wafer map recognition apparatus, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,
the memory stores a program executable by the at least one processor, the program being executable by the at least one processor, the at least one processor being configured to:
forming a set to be identified according to the position number of the defective crystal grain in the wafer;
determining a plurality of similarities between the set to be identified and a plurality of reference sets, wherein each reference set comprises position numbers of a plurality of defect crystal grains in a corresponding reference wafer map, and each reference wafer map is a reference pattern formed by the plurality of defect crystal grains distributed in a reference wafer; and
in response to that the maximum value of the similarity degrees is larger than a preset similarity threshold value, determining the class of the wafer map as the class of the reference wafer map corresponding to the maximum value;
wherein the wafer map includes a pattern formed by a plurality of defective dies distributed in the wafer.
8. The wafer map identification device of claim 7, wherein the at least one processor is further configured to:
forming a subset to be identified according to the position number of the defective crystal grain of each wafer map in the plurality of wafer maps, thereby forming a plurality of subsets to be identified; and
and calculating a union set of the plurality of subsets to be identified to form the set to be identified.
9. The wafer map identification device of claim 7 or 8, wherein the at least one processor is further configured to:
determining a similarity between the set to be identified and each of the plurality of reference sets by a Jacard similarity algorithm to determine the plurality of similarities.
10. The wafer map identification device of claim 9, wherein the at least one processor is further configured to:
determining a first number of position numbers simultaneously contained in the set to be identified and the reference set;
determining a second number of position numbers included in the set to be identified and not included in the reference set;
determining a third number of location numbers that are included in the reference set and not included in the set to be identified; and
calculating the similarity based on the first number, the second number, and the third number.
11. A non-transitory computer readable medium storing a computer program, comprising: the computer program is for causing the computer to perform the method of any one of claims 1 to 6.
CN202110682913.6A 2021-06-18 2021-06-18 Wafer map identification method, device and readable medium Pending CN113256612A (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109978839A (en) * 2019-03-08 2019-07-05 浙江大学 The detection method of the low texture defect of wafer
CN110598200A (en) * 2018-06-13 2019-12-20 北京百度网讯科技有限公司 Semantic recognition method and device
CN111239152A (en) * 2020-01-02 2020-06-05 长江存储科技有限责任公司 Wafer detection method, device and equipment
CN111368928A (en) * 2020-03-06 2020-07-03 普迪飞半导体技术(上海)有限公司 Wafer pattern matching method and device, electronic equipment and storage medium
CN112330590A (en) * 2020-09-25 2021-02-05 上海华力微电子有限公司 Wafer defect verification method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110598200A (en) * 2018-06-13 2019-12-20 北京百度网讯科技有限公司 Semantic recognition method and device
CN109978839A (en) * 2019-03-08 2019-07-05 浙江大学 The detection method of the low texture defect of wafer
CN111239152A (en) * 2020-01-02 2020-06-05 长江存储科技有限责任公司 Wafer detection method, device and equipment
CN111368928A (en) * 2020-03-06 2020-07-03 普迪飞半导体技术(上海)有限公司 Wafer pattern matching method and device, electronic equipment and storage medium
CN112330590A (en) * 2020-09-25 2021-02-05 上海华力微电子有限公司 Wafer defect verification method

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