CN113255280A

CN113255280A - System and method for representing a layout of an integrated circuit

Info

Publication number: CN113255280A
Application number: CN202110190503.XA
Authority: CN
Inventors: R·艾弗森
Original assignee: Synopsys Technologies Co Ltd
Current assignee: Synopsys Technologies Co Ltd
Priority date: 2020-02-13
Filing date: 2021-02-18
Publication date: 2021-08-13

Abstract

The present application relates to systems and methods for representing a layout of an integrated circuit. Embodiments provide a method for representing a layout of an integrated circuit. In an example embodiment, a method includes determining a plurality of regions of an integrated circuit IC layout design based on one or more parameters. In an embodiment, at least one of the plurality of zones has a certain characteristic. The example method further includes determining a plurality of regions associated with the plurality of regions. Each region of the plurality of regions has a characteristic of one region of the plurality of regions.

Description

System and method for representing a layout of an integrated circuit

RELATED APPLICATIONS

Priority OF U.S. provisional application No. 62/976,245, entitled "system and method FOR CONTINUOUS GLOBAL REPRESENTATION OF LOCAL DATA USING active areas in an integrated CIRCUIT LAYOUT" (SYSTEMS AND METHODS FOR content GLOBAL reproduction OF LOCAL DATA EFFECTIVE AREAS IN AN INTEGRATED circular search, filed on 13.2.2020, the contents OF which are incorporated herein by reference in their entirety).

Technical Field

The present disclosure relates generally to integrated circuit fabrication and, more particularly, to continuous global representation of local data using active areas in an integrated circuit layout.

Background

In integrated circuit fabrication techniques, some parameters (e.g., the thickness of a planar dielectric) vary significantly across the integrated circuit layout. However, the rules for generating parameter values often depend on parameters that are not explicitly defined throughout the integrated circuit layout. Even where the parameters are well defined, the parameters may not necessarily be continuous across regions of the integrated circuit layout.

Disclosure of Invention

In some embodiments, a method for representing a layout of an integrated circuit is provided. In some embodiments, the method includes determining a plurality of regions of an Integrated Circuit (IC) layout design based on one or more parameters, at least one region having a certain characteristic. In some embodiments, the method further includes determining a plurality of regions, wherein each region of the plurality of regions has a characteristic of one region of the plurality of regions. In some embodiments, the method further includes assigning a first value to a location of the IC layout design outside the plurality of regions, and assigning a second value to a location of the IC layout design within the plurality of regions. In some embodiments, the method further comprises; in response to determining that a location of the IC layout design is located in two or more overlapping regions of the plurality of regions, determining a generated value associated with the location based at least in part on values of the two or more overlapping regions of the plurality of regions. In some embodiments, the method further includes generating, using the processor, an Integrated Circuit (IC) representation of the IC layout design based at least in part on the first value, the second value, and the generated value.

In some embodiments, the generated value determined based at least in part on the values of the two or more overlapping regions of the plurality of regions comprises a weighted average of the values of the two or more overlapping regions of the plurality of regions.

In some embodiments, the plurality of regions comprises one or more of a plurality of points of an Integrated Circuit (IC) representation, a plurality of line segments of an Integrated Circuit (IC) representation, or a plurality of contiguous regions of an Integrated Circuit (IC) representation.

In some embodiments, determining the plurality of regions includes: for each contiguous region as a region, a contiguous region is determined by sweeping the contiguous region in an x-direction and a y-direction, wherein the contiguous region has a first length and a first width. In some embodiments, determining the plurality of regions further comprises: for each line segment as a region, a rectangle is determined by sweeping the line segment in the x-direction and the y-direction, wherein the rectangle has a second length and a second width. In some embodiments, determining the plurality of regions further comprises: determining a line by sweeping a point in one of the x-direction or the y-direction for each point as a zone, wherein the line has a third length.

In some embodiments, one or more of the first length, the second length, or the third length is determined based at least in part on a portion x1 of the length of the corresponding region, wherein x1> 0.

In some embodiments, one or more of the first width or the second width is determined based at least in part on a portion x2 of the width of the corresponding region, wherein x2> 0.

In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a maximum distance, wherein the maximum distance is a constant.

In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x3 of the length of the corresponding region, wherein x3> 0.

In some embodiments, one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x4 of the width of the corresponding region, wherein x4> 0.

Drawings

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of embodiments of the disclosure. The drawings are intended to provide an understanding and appreciation for the embodiments of the disclosure, and are not intended to limit the scope of the disclosure to these specific embodiments. Furthermore, the drawings are not necessarily drawn to scale.

FIG. 1 is a flow diagram illustrating an example for determining a continuous global representation of local data using active areas in an integrated circuit layout, in accordance with some embodiments.

FIG. 2 is a flow diagram illustrating an example for determining a plurality of regions associated with the plurality of zones, according to some embodiments.

Fig. 3A, 3B, and 3C illustrate example integrated circuit layouts according to some embodiments.

Fig. 4A, 4B, and 4C illustrate example subsets of a plurality of regions according to some embodiments.

5A, 5B, 5C, and 5D illustrate example subsets and global representations of multiple regions according to some embodiments.

Fig. 6 depicts a flow diagram of various processes used during the design and manufacture of integrated circuits according to some embodiments of the present disclosure.

FIG. 7 depicts a diagram of an example computer system in which embodiments of the present disclosure may operate.

Detailed Description

Aspects of the present disclosure relate to continuous global representation of local data using active areas in an integrated circuit layout.

Integrated Circuit (IC) layouts involve the representation (e.g., or modeling) of an integrated circuit in terms of the components that make up the IC, and the components depend on the characteristics of the metal, oxide, or semiconductor layers that make up the components. IC layouts place and connect the components that make up an IC so that they meet certain criteria (e.g., performance, size, density, manufacturability, etc.), and the ability of a component to meet certain criteria depends on parameters or local values associated with the component characteristics (e.g., some of which may not be explicitly defined, measured, or understood).

In multi-dimensional (e.g., three-dimensional (3D)) integrated circuit modeling, some global effects may be characterized in terms of local parameters (e.g., local data). Local parameters may be well-defined only at specific points or regions within a given Integrated Circuit (IC) layout, and local parameters may not be well-defined at many locations of the IC layout. In this document, parameters may be considered explicitly defined when they are clear, constant, or known (e.g., also understandable with reference to the figures described herein). For example, the width of a polygon may be defined at a point on its perimeter as the vertical distance from the edge inward until the perimeter is encountered again. In such examples, the width of the polygon may be considered to be well-defined at the point, but may not be considered to be well-defined at other points. Furthermore, the local parameter may be discontinuous in that different values may be associated with adjacent locations where the local parameter value is actually well defined.

As used herein, local parameters refer to parameters of a layout that are only well defined at specific points or regions within the IC layout and are not defined or poorly defined at the remaining locations of the layout. Local data refers to local parameters and functions of local parameters. As used herein, a uniform local area may refer to a point, line segment, or contiguous region of an IC layout having uniform local parameters. In some embodiments, the local parameters may not be uniform, but rather an average of the local parameters may be used.

As used herein, an area of influence refers to an area associated with a homogeneous local area. In tiled global representations according to embodiments herein, a global data value (such as, for example, the thickness of a dielectric layer) may be assigned to any region. The continuous global representation is defined at all locations and is continuous (e.g., smooth). A continuous global representation based on local data should represent the actual manufactured structure.

In multi-dimensional (e.g., 3D) integrated circuit modeling, it may be preferable that global effects (e.g., derived values such as thickness) are well-defined throughout the layout, and that the global effects are smooth or continuous. In an embodiment, a global effect may be considered smooth or continuous when a value associated with a particular defined area transitions gradually (e.g., as compared to a sharp transition) from a first area of the particular defined parameter adjacent to a second area of the particular defined parameter, wherein the particular defined parameter is different from the first area to the second area. In some embodiments, smooth or continuous may refer to a difference in values between two points approaching zero as the distance between the two points approaches zero.

In various examples, the thickness of the dielectric layer associated with a particular IC layout may be described in terms of a function of the width and spacing of the lines in the interconnect layer. In such instances, the dielectric layer requires a thickness as a smooth function of position, however the width and spacing of the interconnect layers may not be well defined throughout the IC layout.

Embodiments herein overcome the aforementioned disadvantages by implementing a method (e.g., sometimes referred to herein as an active area method) by which a continuous global representation of values across an IC layout is generated that depends on local data (e.g., local parameters associated with various locations of the IC layout). In an embodiment, a tiled global representation is generated from active areas associated with each region of a layout having uniform and well-defined parameter values. As mentioned herein, an active area may include multiple locations of an IC layout to which a value (e.g., a predefined value) may be applied (e.g., multiple locations of the IC layout may be considered to be within a defined active area). That is, the active area may include multiple locations of the IC layout to which a particular local set of parameters may be assigned (e.g., instead of actual parameters associated with the locations). In this way, the continuous global representation has uniform and defined parameter values.

Embodiments herein use regions of influence to build a global representation of local data. That is, a tiled global representation of the IC layout. An area of influence is generated to represent each uniform region of the tiled global representation. The nominal data value for the particular parameter of interest is assigned to any location that is not in any area of influence. In an embodiment, the nominal value may be a value associated with a location of the IC layout that is not proximate to the area of influence (e.g., a region for which the value associated with the particular parameter of interest is not present or known). The data values for a single region of influence (e.g., for a particular parameter of interest) are assigned to any location in the region of influence.

In various embodiments, a region (e.g., or one or more locations of an integrated circuit layout) common to multiple active regions may be assigned data values determined based on the overlapping active regions. In an embodiment, nominal data values may be assigned to areas not covered by any active area. In various embodiments, a smooth global representation may be created using region-based averaging or other techniques.

FIG. 1 is a flow diagram illustrating an example 100 for determining a continuous global representation of local data using active areas in an integrated circuit layout, in accordance with some embodiments. In some embodiments, the present system may determine, at 101, a plurality (e.g., a plurality) of regions of an IC layout design, at least one of the regions having a certain characteristic, based on one or more parameters. In some embodiments, the one or more parameters include parameters of the integrated circuit layout design that are well-defined and continuous, at least within a certain area on the integrated circuit layout design. In some embodiments, the local data contains parameters and functions of parameters (e.g., thickness, which may be a function of parameter width W and parameter spacing S). In some embodiments, the local function is poorly defined in the event that the local data is poorly defined. In addition, when the local data is discontinuous, the local function is discontinuous.

Fig. 3A-3C are example integrated circuit layouts according to some embodiments. As shown in fig. 3C, the spacing within the interconnects is not well defined. As an example, the width between two adjacent interconnects (e.g., within a space) is not explicitly defined. As another example, where the interconnects are non-uniform along the height of the interconnects, the width of the interconnects are discontinuous. In some embodiments, the local data and parameters are not explicitly defined. In some embodiments, the parameters include parameters of the integrated circuit layout that are explicitly defined only at specific points or regions within the integrated circuit layout. Thus, in some embodiments, the parameters are undefined at the remaining locations of the integrated circuit layout. Alternatively, in some embodiments, the parameters are poorly defined at the remaining locations of the integrated circuit layout. In some embodiments, the parameters include a local width W and a local spacing S of the interconnect layer. In some embodiments, the width and spacing are well defined only at points on the perimeter of the shape, with the vertical direction being well defined. It should be appreciated that the shaded regions in fig. 3A-3C represent regions of the IC layout for which no width and spacing are defined (e.g., no W or S is present and no active area is applied to those regions).

As shown in fig. 3B, segments of the perimeter (e.g., edges of the interconnects) are uniform, wherein the segments of the perimeter have a uniform width and spacing. In some embodiments, one segment (in the y-direction) of the outline of the polygon has a uniform value of width and spacing. In some embodiments, each segment comprises an edge of the polygon, or a portion of the polygon that is an edge of the polygon that has the same width and spacing along the entire length of the polygon. In some embodiments, different portions of the perimeter of the polygon may have different width and spacing values. In some embodiments, a zone is defined as a point having a uniform parameter. Alternatively, in some embodiments, a zone is defined as a line segment having a uniform parameter. In some embodiments, a zone is defined as a contiguous region having uniform parameters.

Returning to FIG. 1, in some embodiments, at 102, the current system determines a plurality of regions (e.g., impact regions as discussed above) associated with corresponding regions of the plurality of regions. 4A-4C illustrate example multiple regions according to some embodiments. Multiple regions may be associated with a zone. As a non-limiting example, for a point, the plurality of regions are regions that contain the point. As another non-limiting example, for a line segment having a uniform parameter, the plurality of regions are regions that include the line segment. As yet another non-limiting example, for a contiguous region having a uniform parameter, the plurality of regions includes the contiguous region. The plurality of regions associated with a zone have the same parameter values as the associated zone. The relationship between the zones and the plurality of regions may depend on any of a variety of factors. In some embodiments, the relationship between the zone and the plurality of regions may be based on theoretical considerations including at least one of: a parameter, a function of a parameter, or a function of a location. Fig. 4A shows a plurality of regions of a point based on the density of the point. FIG. 4B shows multiple regions of a segment based on distances, such as-W/2 and + S/2. FIG. 4C illustrates a plurality of regions of a bounding box based region.

Fig. 3A is an example integrated circuit layout, according to some embodiments. In some embodiments, the ratio of W to S (W/S) is used as a parameter. The W/S ratio is based on uniform line segments (e.g., with respect to width and spacing). In some embodiments, the W/S ratio is constructed according to the outline of the polygon. Further, in some embodiments, a particular subset of the plurality of regions is determined. A particular subset of the plurality of regions may include rectangles having widths that match the line segments. It should be understood that the rectangle is merely a non-limiting example used to describe embodiments herein, and that any shape or size of the region is within the scope of the present disclosure. It should also be appreciated that the location of the integrated circuit design may also be referred to herein as (but is not limited to) a point of the design.

In some embodiments, a subset of the plurality of regions is expanded to contain more contours than a single segment. In some embodiments, the subset of the plurality of regions is generated from a uniform region. In some embodiments, a subset of the plurality of regions has a different dimension than a uniform region (e.g., a point, a line segment, a region). A 3D physical representation of an integrated circuit layout requires a smoothing function to achieve an accurate and self-consistent analysis. As a non-limiting example, the thickness of the dielectric layer should be defined at all locations throughout the integrated circuit layout. Further, the thickness should be generally continuous (e.g., smooth) to avoid non-physical conditions. Thus, the function is defined as a continuous global representation.

As shown in fig. 3A, the thickness of the dielectric (e.g., thk) is a function of W and S. In the case where the thickness thk of the dielectric layer is a function of the width W and spacing S of the interconnect layer (e.g., the shaded region), the thickness thk is poorly defined at any location where W or S is poorly defined. For example, where spacing S is zero (e.g., at one end of an integrated circuit layout), the thickness is undefined.

Returning to fig. 3C, for a uniform line segment of the polygon-based outline, the subset of the plurality of regions may be rectangles defined by sweeping the line segment. In some embodiments, a uniform edge parallel to the x-axis is swept in the y-direction, and a uniform edge parallel to the y-axis is swept in the x-direction. The distance swept in the x and y directions may depend on local factors such as the values of W and S. As an example, for the W/S ratio, distances of-W/2 and + S/2 may be used. The minus sign indicates a direction toward the inside of the polygon. The positive sign indicates the direction away from the polygon. Further, in some embodiments, the maximum distance out may be clipped to a constant or to a value that is a function of W or other parameter to limit a subset of the plurality of regions for edges toward the outside of the integrated circuit layout (e.g., where the spacing is infinite).

FIG. 2 is a flow diagram illustrating an example 200 for determining a plurality of regions associated with the plurality of zones, according to some embodiments. In an embodiment, the present system determines a second adjacency region (e.g., area) by sweeping the first adjacency region in the x-direction and the y-direction at 201. The current system may determine a second contiguous region as one region for each contiguous region. In some embodiments, the second abutting region has a first length and a first width. In an embodiment, the current system determines a rectangle (e.g., an area) by sweeping line segments in the x-direction and the y-direction at 202. The current system may determine the rectangle for each line segment as a region. In some embodiments, the rectangle has a first length and a first width. In an embodiment, the current system determines a line (e.g., area) by sweeping a point in one of the x-direction or the y-direction at 203. In some embodiments, the wire has a third length. The current system may determine the line as one region for each point. In some embodiments, one or more of the first length, the second length, and the third length are determined based at least in part on a portion x1 of the length of the corresponding region, wherein x1> 0. In some embodiments, one or more of the first width and the second width are determined based at least in part on a portion x2 of the width of the corresponding region, wherein x2> 0. Alternatively, in some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width are determined based at least in part on a maximum distance, wherein the maximum distance is a constant. In some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width are determined based at least in part on a portion x3 of the length of the corresponding region, wherein x3> 0. In some embodiments, one or more of the first length, the second length, the third length, the first width, and the second width are determined based at least in part on a portion x4 of the width of the corresponding region, wherein x4> 0.

Returning to fig. 1, in an embodiment, the present system assigns nominal data values to each point of the integrated circuit layout in a location outside of the plurality of regions at 103. In an embodiment, the current system assigns data values associated with the plurality of regions to each point of the integrated circuit layout located in the plurality of regions at 104. In an embodiment, the present system, in response to determining that a point of the integrated circuit layout is located in two or more overlapping multiple regions, assigns, at 105, the point a value determined based at least in part on the data value of each of the two or more overlapping multiple regions.

In an embodiment, the global effect is a derived value, such as thickness. The global effect is preferably well-defined everywhere within the integrated circuit layout or design, and should be continuous (e.g., smooth). In an embodiment, in 3D integrated circuit modeling, some global effects are characterized in terms of parameters (e.g., local data). The parameters are only well defined at specific points or regions within the integrated circuit layout. The parameters are not explicitly defined at many locations of the integrated circuit layout. In some embodiments, the parameters may be discontinuous. For example, although a parameter is explicitly defined in a neighboring location, the parameter may have a different value at the neighboring location. For example, the thickness of a dielectric layer may be described as a function of the width and spacing of the lines in the associated interconnect layer. The dielectric layer needs to have a thickness that is a smooth function of position. However, because the width and spacing of the interconnect layers are not well defined everywhere, neither is a function of the width and spacing.

With continued reference to fig. 1, in an embodiment, the present system generates an Integrated Circuit (IC) representation based at least in part on the aforementioned first plurality of values, the second plurality of values, and the generated value at 106. That is, in some instances, a model of the integrated circuit design may be generated using a parameter based on a physical property defined in accordance with the first plurality of values, the second plurality of values, and the generated value. In an embodiment, generating an IC representation of an integrated circuit may include parasitic extraction, general IC layout analysis, physical modeling of an IC layout, capacitive extraction, thermal modeling, lithography effect analysis, generation of a compact device model, design rule generation, metal migration, interface resistance analysis, and the like.

5A-5D illustrate example subsets and global representations of multiple regions according to some embodiments. In some embodiments, the W/S ratio is limited to a Manhattan shape. In the manhattan shape, each edge is parallel to the x or y axis. In some embodiments, other angles may be handled by a stepped approach. For example, the stair-stepping method may include replacing diagonal lines by horizontal and vertical line stairs. Alternatively, in some embodiments, other angles may be processed using a hybrid approach (e.g., a combination of a step and Manhattan approach; e.g., or using non-Manhattan active areas). In some embodiments, the W/S ratio has two categories of regions: one type of multiple regions oriented in the x-direction and one type of multiple regions oriented in the y-direction. FIG. 5A shows clipping to a constant maximum S_MAXBased on, for example, a uniform segment in the y-direction, and by using the values-W/2 (in) and + S/2 (out). FIG. 5B shows multiple regions oriented in the y-direction. In some embodiments where-W/2 and + S/2 are used, the current system generates a tiled description that approximates all of the regions of the polygon. Transverse to the integrated circuit design or layout in the x-direction of any polygon in S_MAXThe zones within are tiled by a union of subsets of the plurality of zones oriented in the x-direction. No area is covered by a plurality of areas oriented in the x-direction. Similar behavior occurs for multiple regions oriented in the y-direction.

In some embodiments, the intersections of the plurality of regions have a plurality of associated values for the parameters and functions of the parameters. Fig. 5C shows one such intersection between multiple regions directed along the x-direction (e.g., a _ L2) and multiple regions directed along the y-direction (e.g., a _ T1). In some embodiments, any suitable method may be used to resolve the deviations created by the intersection points. In some embodiments, a weighted average method is used. In such embodiments, a weight of 1/Δ is used, where Δ is the plurality of regionsThe width of the field from the associated uniform edge (e.g., the value W/2 or S/2 for the uniform edge). For parameter P_{A_L2}And P_{A_T1}The average value may be [ P ]_{A_L2}/Δ_{A_L2}+P_{A_T1}/Δ_{A_T1}]/[1/Δ_{A_L2}+1/Δ_{A_T1}]. In some embodiments, the use has a weight of 1/Δ²Is calculated as the weighted average of (a). Alternatively, in some embodiments, a value with a minimum value Δ is used.

Fig. 5D illustrates an example tiled global representation. In a tiled global representation, all regions are assigned a global data value, such as the thickness of the dielectric layer. In some embodiments, the nominal zone includes all zones not in any subset of the plurality of zones. In such embodiments, a nominal value is assigned to the nominal region. The nominal regions are shown as lightly shaded (e.g., with small dots) in fig. 5D. In some embodiments, the values associated with the local regions are assigned to regions within a single subset of the plurality of regions. In fig. 5D, the uniform edge is shown as a region within a single subset of the plurality of regions. In some embodiments, the regions that are intersections of multiple subsets of the multiple regions are assigned resolution values based on the parameters or a function of those parameters. In some embodiments, the tiled global representation is a discontinuous global function.

The representation of the layout (e.g., a tiled global representation) is a well-defined function everywhere, but may change abruptly across interfaces or intersections between regions. In some embodiments, the continuous global function is derived from the discontinuous global function by looking up a region-based average at any point. In some embodiments, the region-based average at location (x, y) is found by considering each region (e.g., region i) within a square averaging window centered at (x, y). When the nominal value is 0, the area-based average value can be given by the following equation (1):

where Ai is the area of the interaction zone i within the window, Fi is the associated function value (e.g., a value assigned to a given point that may be a function of the parameter), and Awindow is the area of the average window. In some embodiments, for a non-zero nominal value Fnom, the following equation (2) may be used.

Multiple windows having different sizes may be used. In some embodiments, the final result is a weighted average with the same or different weights. For example,

F＝50％*F_window1+30％*F_window2+20％*F_window3 (3)

for example, the selection of the weight associated with the weighted average depends on the associated function. As a non-limiting example, if the thickness depends on the closest edge, averaging the two thickness values may be stronger when the edges are closer. In an embodiment, the averaging function may be defined according to equation (4) below.

In an embodiment, the averaging function may be defined according to equation (5) below.

Where k is a number.

In some embodiments, the mapping is generated by finding values of a continuous global function of points on the grid. To evaluate the global function at points between grid points, interpolation is performed in the x-direction and in the y-direction. In some embodiments, a subset of the plurality of regions is used to build a global representation of the local data. In such embodiments, the tiled global representation is first created. A subset of the plurality of regions is generated to represent each homogeneous region. Assigning nominal data values to any location not in any subset of the plurality of zones and assigning data values of a single subset of the plurality of zones to any location in the subset of the plurality of zones. Similarly, data values are assigned to any position in the plurality of subsets of the plurality of regions based on resolving values of the respective overlapping subsets of the plurality of regions. Finally, a smooth global representation of the local data may be created using any of a variety of region-based averaging techniques. In one embodiment, the local data includes a width and spacing defined on the perimeter of the interconnect layer shape. Each uniform line segment is represented by a rectangle that extends from the inside half of the shape to half towards the nearest outside shape.

FIG. 6 illustrates an example set of processes 700 for transforming and verifying design data and instructions representing an integrated circuit for use during design, verification, and manufacture of an article of manufacture, such as an integrated circuit. Each of these processes may be constructed and implemented as a plurality of modules or operations. The term "EDA" stands for the term "electronic design automation". These processes begin with the creation of a product idea 710 with information supplied by a designer that is transformed to create an article of manufacture using a set of EDA processes 712. When the design is complete, the design is taped out 734, at which point the work (e.g., geometric versions) of the integrated circuit is sent to a manufacturing facility to manufacture a mask set, which is then used to manufacture the integrated circuit. After tape-out, the semiconductor die are fabricated 736 and a packaging and assembly process 738 is performed to produce a finished integrated circuit 740.

The specifications of a circuit or electronic structure may vary from a low-level transistor material layout to a high-level description language. The high-level representation may be used to design circuits and systems using a hardware description language ("HDL") such as VHDL, Verilog, systemveilog, SystemC, MyHDL, or OpenVera. The HDL description may be transformed into a logic level register transfer level ("RTL") description, a gate level description, a layout level description, or a mask level description. Each lower level of representation as a more detailed description adds more useful details to the design description, such as more details of the modules comprising the description. The lower level representation, which is described in more detail, may be computer generated, derived from a design library, or created by another design automation process. An example of a specification language at a lower level representation language for specifying a more detailed description is SPICE, which is used for a detailed description of a circuit with many analog components. The description at each representation level is enabled for use by a respective tool (e.g., formal verification tool) for that layer. The design process may use the sequence depicted in fig. 6. The described process is enabled by EDA products (or tools).

During system design 714, the functionality of the integrated circuit to be fabricated is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and/or code lines), and cost reduction. The division of the design into different types of modules or components may be done at this stage.

During logic design and functional verification 716, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, components of a circuit may be inspected to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs, such as test bench generators, static HDL checkers, and formal checkers. In some embodiments, special systems called components of "emulators" or "prototype systems" are used to accelerate functional verification.

During synthesis and testing of design 718, the HDL code is transformed into a netlist. In some embodiments, the netlist may be a curved structure, where the edges of the curved structure represent components of the circuit, and where the nodes of the curved structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by EDA products to verify that the integrated circuit, when manufactured, works according to a specified design. The netlist can be optimized for the target semiconductor manufacturing technology. In addition, the finished integrated circuit may be tested to verify that the integrated circuit meets the requirements of the specification.

During netlist verification 720, the netlist is checked for compatibility with timing constraints and for correspondence with the HDL code. During design planning 722, an overall plan view of the integrated circuit is constructed and analyzed for timing and top level layout.

During the layout or physical implementation 724, physical placement (positioning of circuit components such as transistors or capacitors) and routing (circuit components connected by multiple conductors) is performed, and selection of cells from the library to enable particular logic functions may be performed. As used herein, the term "cell" may designate a set of transistors, other components, AND interconnects that provide a boolean logic function (e.g., AND, OR, NOT, XOR) OR a storage function (e.g., flip-flop OR latch). As used herein, a circuit "block" may refer to two or more units. Both the cells and the circuit blocks may be referred to as modules or components and enabled as both physical and analog structures. Parameters such as size are specified (based on "standard cells") for the selected cells and made accessible in the database for use by the EDA product.

During the analysis and extraction 726, circuit functions are verified at the layout level, which permits an improvement in layout design. During physical verification 728, the layout design is checked to ensure that manufacturing constraints, such as DRC constraints, electrical constraints, lithographic constraints, etc., are correct and that the circuitry functionality matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is fabricated.

During tape-out, data is created for use in producing a photolithographic mask (after applying photolithographic enhancements as appropriate). During mask data preparation 732, the "tape-out" data is used to generate photolithographic masks used to produce finished integrated circuits.

The storage subsystem of a computer system (e.g., computer system 900 of FIG. 7) may be used to store programs and data structures used by some or all of the EDA products described herein as well as products used to develop libraries and cells of physical and logical designs using libraries.

Fig. 7 illustrates an example machine of a computer system 900 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions that specify actions to be taken by that machine (sequential or otherwise). Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 900 includes a processing device 902, a main memory 904 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM) such as synchronous DRAM (sdram)), a static memory 906 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage device 918, which communicate with each other via a bus 930.

The processing device 902 represents one or more processors, such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 902 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processing device 902 may be configured to execute the instructions 926 for performing the operations and steps described herein.

Computer system 900 may further include a network interface device 908 to communicate over a network 920. Computer system 900 may also include a video display unit 910 (e.g., a Liquid Crystal Display (LCD) or a Cathode Ray Tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), the graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

The data storage 918 may include a machine-readable storage medium 924 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 926 or software embodying any one or more of the methodologies or functions described herein. The instructions 926 may also reside, completely or at least partially, within the main memory 904 and/or within the processing device 902 during execution thereof by the computer system 900, the main memory 904 and the processing device 902 also constituting machine-readable storage media.

In some embodiments, the instructions 926 include instructions to implement the functionality corresponding to the present disclosure. While the machine-readable storage medium 924 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and processing device 902 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations that produce a desired result. The operations are those requiring physical manipulations of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, specific terms refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular, more than one element may be depicted in the drawings and similar elements are labeled with similar reference numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

1. A method for representing a layout of an integrated circuit, the method comprising:

determining a plurality of regions of an integrated circuit IC layout design based on one or more parameters, at least one of the plurality of regions having a characteristic;

determining a plurality of regions, each region of the plurality of regions having a characteristic of a region of the plurality of regions;

assigning a first plurality of values to locations of the IC layout design outside of the plurality of regions;

assigning a second plurality of values to locations of the IC layout design within the plurality of regions;

in response to determining that a location of the IC layout design is located in two or more overlapping regions of the plurality of regions, determining a value associated with the location based at least in part on values of the two or more overlapping regions of the plurality of regions; and

generating, using a processor, an Integrated Circuit (IC) representation of the IC layout design based at least in part on the first plurality of values, the second plurality of values, and the values.

2. The method of claim 1, wherein the generated value determined based at least in part on values of the two or more of the plurality of regions comprises a weighted average of the values of the two or more of the plurality of regions.

3. The method of claim 1, wherein the plurality of regions comprises one or more of a plurality of points of the Integrated Circuit (IC) representation, a plurality of line segments of the Integrated Circuit (IC) representation, or a plurality of contiguous regions of the Integrated Circuit (IC) representation.

4. The method of claim 1, wherein the determining the plurality of regions comprises:

as one zone for each contiguous area,

determining a border region by sweeping the border region in an x-direction and a y-direction, wherein the border region has a first length and a first width;

as a zone for each line segment,

determining a rectangle by sweeping the line segment in the x-direction and the y-direction, wherein the rectangle has a second length and a second width; and

as one area for each point,

determining a line by sweeping the point in one of the x-direction or the y-direction, wherein the line has a third length.

5. The method of claim 4, wherein one or more of the first length, the second length, or the third length is determined based at least in part on a portion x1 of a length of a corresponding region, wherein x1> 0.

6. The method of claim 4, wherein one or more of the first width or the second width is determined based at least in part on a portion x2 of a width of a corresponding region, wherein x2> 0.

7. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a maximum distance, wherein the maximum distance is a constant.

8. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x3 of a length of a corresponding region, wherein x3> 0.

9. The method of claim 4, wherein one or more of the first length, the second length, the third length, the first width, or the second width is determined based at least in part on a portion x4 of a width of a corresponding region, wherein x4> 0.

10. A system, comprising:

a memory storing instructions; and

a processor coupled with the memory and executing instructions that, when executed, cause the processor to:

generating an Integrated Circuit (IC) representation of the IC layout design based at least in part on the first plurality of values, the second plurality of values, and the values.