KR20220140578A - Skeletal representation of layouts for development of lithographic masks - Google Patents

Abstract

The method includes the following steps: a layout used in the lithographic mask development process is accessed, eg, the layout may be the layout of the mask itself or the layout of the resulting printed pattern on the wafer; The layout includes a number of discrete shapes; skeletal representations for at least some of the discrete shapes in the layout are determined; A skeletal representation of an individual shape has elements of two or more nodes connected by edges; The skeletal representation of the individual shape also includes size parameters for at least some of the elements; Skeletal representations of shapes are used in the mask development process. The system includes a processor for executing the method. The non-transitory computer readable medium includes stored instructions for executing the method.

Description

Skeletal representation of layouts for development of lithographic masks

Related applications

This application claims priority to US Provisional Application No. 62/977,020, entitled "Skeleton Mask Representation," filed on February 14, 2020, which is incorporated by reference in its entirety.

technical field

The present disclosure relates to the development of lithographic masks as used, for example, in the fabrication of integrated circuits.

As designs for integrated circuits become larger, denser, and more complex, the demands on computational lithography solutions for developing masks used in fabrication are increasing. Features on masks are becoming smaller and less linear. For example, advanced mask writing tools can create curved shapes. This makes their simulations more difficult and more computationally intensive. In addition, the number of features on the mask is increasing, thus further increasing computing requirements. The lithography process itself is also becoming more complex. For example, lighting sources are becoming more complex. This, in turn, requires more sophisticated analysis. Accordingly, it is desirable to take steps to reduce processing requirements when processing a mask layout by mask related applications such as optical proximity correction (OPC), inverse lithography technology (ILT), and lithography verification.

In certain embodiments, the method includes the following steps. The layout used in the lithography mask development process is accessed. For example, the layout may be the layout of the mask itself or the layout of the resulting printed pattern on the wafer. The layout includes a number of discrete shapes. Skeletal representations for at least some of the discrete shapes in the layout are determined. A skeletal representation of an individual shape has elements of two or more nodes connected by edges. It also includes size parameters for at least some of the elements. Skeletal representations of shapes are used in the mask development process.

Other aspects include components, devices, systems, improvements, methods, processes, applications, computer-readable media, and other techniques related to any of the above.

BRIEF DESCRIPTION OF THE DRAWINGS The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The drawings are used to provide knowledge and understanding of embodiments of the disclosure, and do not limit the scope of the disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.
1 shows a flow diagram for a mask development process in accordance with some embodiments of the present disclosure.
2A-2C show examples of polygonal representations and corresponding skeletal representations of individual shapes in a layout;
3a and 3b show the conversion of a polygonal representation to a skeletal representation.
3c and 3d show the conversion of a skeleton representation to a polygonal representation.
Figure 4a shows the perturbation of the tip of the shape.
Figure 4b shows another example of a shape disturbance.
5 and 6 show the use of skeletal representations for mask rule checking.
7 shows a flow diagram of various processes used during design and manufacture of an integrated circuit, in accordance with some embodiments of the present disclosure.
8 depicts an abstract diagram of an exemplary computer system in which embodiments of the present disclosure may operate.

Aspects of the present disclosure relate to skeletal representations of layouts for development of lithographic masks. Traditionally, mask layouts are represented by polygons, more specifically, straight polygons. However, as lithography becomes more complex and challenging, mask layouts are also becoming more complex. The use of sub-resolution assist features and non-rectangular and even curved shapes makes the traditional representation based on straight polygons less than ideal. Representing a curved shape by straight polygons requires a large number of polygons, and still, expressing a curved edge by step approximation. Even if non-straight polygons were allowed, a curved edge would still require a polygon with multiple sides to approximate the curve.

Many processes used in the development of masks, such as optical proximity correction (OPC), inverse lithography technology (ILT), and lithographic verification, require the analysis or manipulation of these representations. For example, such mask development processes may introduce some changes to the layouts to determine whether the changes may be beneficial.

In the approach described below, layouts are represented by skeletal representations rather than polygons. The layouts may be the layout of the mask itself, the layout of the resulting printed pattern on the wafer, a two-dimensional representation of the aerial image created by the mask, or other types of two-dimensional images used for mask development. A layout includes a number of shapes, which can be traditionally represented by straight polygons. Here, at least some of the shapes are represented by skeletal representations instead of or in addition to other types of representations. Skeletal representations of individual shapes include "skeletons" corresponding to the axes or centerlines of the shapes. Elements of the skeleton include two or more nodes connected by edges. The nodes are the "joints" of the skeleton, and the edges are the "bones" of the skeleton. The skeleton representation also includes size parameters for at least some of these elements. These size parameters provide information about the size of the shape at different locations along the skeleton. For example, size parameters for edge elements in a skeletal representation may be based on the widths of the shape along these edges. The size parameters for nodes in the skeleton representation may be based on local radii of shape at these nodes.

A skeleton representation may be a more compact and more computationally efficient representation of a layout for certain mask development processes. For example, if it is desired to move the position of the shape or to change the thickness of the shape, this may involve modifying the corresponding elements (nodes and edges) and/or changing the various size parameters for those elements. It can be achieved simply by As a result, the computational speed is increased, and the required computational resources (memory and processor utilization) are reduced.

1 shows a flow diagram for a mask development process in accordance with some embodiments of the present disclosure. The techniques described in this disclosure may be applied to multiple types of mask development processes 120 . This includes both mask synthesis processes (eg, designing a mask to achieve a desired result) and mask verification processes (eg, verifying whether the mask design produces a desired result). It also includes both forward propagation processes (e.g., predicting an aerial image generated by a mask) and backward propagation (e.g. propagating backward from a desired aerial image to determine which mask to generate that aerial image). do. Examples of mask development processes 120 include optical proximity correction (OPC), inverse lithography technique (ILT), and lithography verification (including mask design rule checks).

The input to the mask development process 120 is a layout 110 of various geometries. For mask development process 120 , layout 110 may be a layout of a mask used to fabricate an integrated circuit, although the skeleton representation is not limited to this example. In many cases, shapes in the layout are represented as polygons, as shown in polygonal representation 115 of FIG. 1 .

The result of the mask development process 120 will generally be referred to as a “solution” 190 . The solution will be determined according to the mask development process 120 . Table 1 below lists some example applications. The "Layout" column is the input to the mask development process, and the "Solution" column is the output. The column "skeletal representations" indicates which quantities can be represented by skeletal representations.

Table 1 Some Exemplary Mask Development Processes

In one approach, the mask development process 120 is applied to shapes in a layout by using a skeletal representation 125 for at least some of the shapes as shown on the right side of FIG. 1 . Layout 110 includes a number of discrete shapes. A skeletal representation is determined 122 for at least some of the shapes. A skeletal representation of an individual shape includes elements of two or more nodes connected by edges. The skeleton representation also includes size parameters for at least some of the elements. A mask development process is then applied (124) using the skeletal representation of the shapes.

2A-2C show examples of polygonal representations and corresponding skeletal representations of individual shapes in a layout; In each figure, the left side shows a polygonal representation with only the skeleton superimposed with dashed lines, and the right shows the skeleton representation with both the bones and edges defined by the size parameters. Polygonal representation 210 is a piecewise linear approximation of the boundary of a shape. In these examples, the polygonal representation 210 is based on boundary segments of 45 degree angles. The skeleton representation 250 includes a piecewise connected skeleton 252 of nodes and edges. In the figures, the nodes are circles, and the edges are thicker lines connecting the circles. Skeleton 252 is a representation of the two-dimensional mask polygon 210 but in a “lower” dimension. This may be based on morphological erosion of the shape 210 .

The skeletal representation 250 may have additional properties. In FIG. 2A , nodes and edges are associated with size parameters. Nodes N are characterized by a local radius R, and edges E are characterized by a width W. These size parameters express the local radius (R) of the curve defined by the node and the width (W) of the shape defined by the edge. Node N1 is a terminal node (ie connected to only one other node), and thus the shape has a tip with a radius (R = R0). Edges E1, E2, E3 all have a width (W = W0 = R0). Node N4 is also an end node with radius R = R0. Nodes N2 and N3 are internal nodes (connected to two or more other nodes). Their radii (R = R0) define the shape of the local curvilinear shape centered at the nodes. These properties can be used to reconstruct the original shape 210 from the base skeleton 252 via a dilation or sizing procedure. The sizing procedure properly sizes the corresponding segment of the base shape 210 using the size parameters defined at the nodes/edges. Reducing the mask representation to a lower dimension allows simpler algorithms to be implemented for various geometry manipulations, such as auxiliary features with high aspect ratios and well represented by an unbranched skeleton as shown in Figure 2a. There are multiple features on the mask.

The skeleton representation may include additional properties to represent more complex shapes, including those with branching skeletons. In FIG. 2B , the axis of the shape has a number of branches in an “H” shape, so the skeleton 252 is branched. It includes nodes N1 to N6 and edges E1 to E5. In addition, the tips of the shape are rounded corners, not arcs. To capture this, the terminal node N1 is characterized by two size parameters: R and r. R defines the width of the end shape and r defines the local radius of the corners. Thus, r = 0 designates a square tip, and r = R designates a circular tip as shown in Figure 2a. In Figure 2b, 0 < r < R, the tip has rounded corners. In addition, nodes N2 and N5 may have negative values of r to specify the shape of the inner corners along the crossbar of "H". Other parameters may also be used to provide more degrees of freedom. For example, tips and other curves corresponding to nodes may be oval, polygonal, or other shapes. The branches corresponding to the edges may vary in width: increase or decrease linearly, change periodically, or change in some other way. Different parameters may be used to capture these and other variations.

Figure 2c shows another example, where skeleton 252 has six nodes N1 to N6, but nodes N1 to N3 are connected as polygons, and so are nodes N4 to N6. . In some cases, the shapes may have internal holes.

Nodes and edges may also have properties that capture information other than the original shape. One example is the association from a node or edge to a specific polygonal feature. For example, a particular skeletal node (N) or edge (E) may be associated with a particular polygon segment(s). This can be used in OPC solvers, where a node (N) and its parameters such as radius are simulated mask (which is defined by N and other skeletal nodes) on a polygon segment or target at a point on the segment. The image is adjusted until it prints. Other examples include constraints on the displacement of the node/edge, constraints on the size of the node/edge, and other constraints on the segment or shape associated with the node/edge.

Different techniques may be used to create a skeletal representation from a polygon or other representation. An example is shown in FIGS. 3A and 3B . In this example, as shown in FIG. 3A , a polygonal representation 310 of a shape is first transformed into a Voronoi diagram 320 . A Voronoi diagram is the mid-axis of a polygon. 3B , the Voronoi diagram is trimmed to create a skeleton 330 of nodes and edges. Trimming may be based on functions of the distance between points on a polygon boundary defining a particular point on the Voronoi diagram. Alternatively, the trimming may be based on the proximity of the intermediate axis to the boundary. Additional attributes such as widths and radii and which polygon segments correspond to which skeleton elements can then be attached to the skeleton.

Conversely, using different techniques, the skeleton representation can be transformed into an overall shape, such as a polygonal representation. One approach is shown in FIGS. 3C and 3D . 3C shows the skeleton 340 . The nodes and edges of the skeleton extend according to their radii and widths, as indicated by the thin arrows. Alternatively, polygons may be created for nodes and edges, and then merged into the resulting polygon 350 shown in FIG. 3D . In some cases, the skeleton may be simplified prior to creating the polygons.

There are a number of use cases where skeletal representations are more efficient than others. In one class of use cases, it is desirable to shift a shape or part of a shape in a direction perpendicular to the axis of the shape. Skeletal representation naturally allows for this. An example of this use case is the use of perturbation tables for OPC. The perturbation tables allow the tool to quickly compute changes in the solution generated by the lithographic simulation from the mask M when perturbations to the boundary of the mask M are applied (ie when the boundaries of the shapes are moved). do. For example, a perturbation table may tabulate the change in wafer intensity for a given mask perturbation. The use of perturbation tables for skeletons is described below.

A general mask synthesizing problem can be framed as an optimization of a cost function C(L) that takes a lithography signal L (eg, mask layout) as input and returns a cost value C. The slope of C for different perturbations P can be computed. These gradients (dC/dP) may be used to optimize a layout through a gradient-based optimization method.

4A shows the disturbance of the end 490 of the shape. In the skeleton representation 450 , an end is represented by nodes N1 , N2 and an edge E1 . Nodes N1 and N2 have a radius (R = R0) and an edge E1 has a width (W = W0 = R0). When a polygonal representation 410 is used, the tip is represented by seven boundary segments 421 - 427 approximating a rounded tip. This is not a very good approximation. More accurate approximations will use more boundary segments.

Disturbing the tip will require moving all of the affected boundary segments together. As each individual boundary segment is perturbed, the resulting change in the cost function is measured, and the lithography cost slope (dC/dP) can be computed for a given perturbation (P). However, if a skeleton representation for a shape is used, the slope (dC/dP) can be computed for the geometric parameters for the skeleton, which can be simpler and more computationally efficient.

For example, assume that the disturbance of interest is increasing the size of the end 490 . For the skeleton representation, this is equivalent to increasing the size parameter (W = R) with a slight corresponding movement of the position of node N2. The effect of the disturbance is given by the slope (dC/dW). In the polygonal representation, the seven boundary segments 421 - 428 are moved together, and the total slope is the sum of the individual slopes for each boundary segment.

Consider now another example as shown in FIG. 4B . In this example, node N1 is a skeletal element to be optimized. In particular, we consider the optimization of the position of the node N1 along a specific direction v. First, assume v = t(N1), which is a tangent to the skeleton edge E1 connected to node N1. This allows for stretching and contracting the shape along the shape's axis. If a formula is available, the slope (dC/dN _T ) can be calculated and used for optimization.

Alternatively, the slope may be constructed from the collective derivative of the polygonal boundary segments associated with node N. This set is referred to as D = {D _i }. From the construction of the polygons from the skeleton, set D comprises boundary segments 423 - 425 . Each of those segments D _i will have its own magnitude of cost change dC _i , and the normals {n _i }) and lengths ({L _i }) of those segments are given in equation (1) can be used to project the cost change onto t(N).

Here, the summation is for polygonal segments i (segments 423 to 425), and ? is the dot product.

Now consider the change in radius R of node N1. To compute the derivative dC/dR for the change in radius at node N1 , the system may use the sum of dC _i projected onto the outward normal of the corresponding polygon edges 423 - 425 .

Consider now a lateral shift of the shape, which is a movement of the edge E1 in a direction perpendicular to the direction of the edge E1 . To compute the derivative for the lateral shift of shape, the system can find the derivative dC/dE for moving the edge E1 in a direction orthogonal to the edge.

If a polygonal representation is used to compute this, the segments D are projected onto the normal vector n(E1) of the edge E1. This is given by equation (2).

Here, the summation is for the affected polygonal segments i. Note that the boundary segments D associated with E1 in equation (2) are a different set than those associated with node N1 in equation (1). Other variations of combinations of these derivatives may be computed to allow for other skeletal modifications that may be useful depending on application requirements.

Once these gradients have been computed, a gradient-based optimization approach can be used to optimize the mask by moving the skeletal elements or modifying their parameters to achieve an improved cost function (C).

The approach described above for OPC can also be used for ILT and other mask development processes. In ILT, the optimization of skeletal elements uses the ILT cost function and the corresponding gradient field, which is described above except that the derivative values (dC _i ) are computed from the ILT cost function gradient field, which can be sampled at polygon edges. It can be computed as Subsequent movement by tangential node shifting, radius modification, or edge shifting would be similar to that described above. This is because the ILT gradient is computed for a level set function whose outgoing normal has magnitude = 1 at polygon edges.

Similar to the lithography cost based optimization steps, the MRC (Mask Rule Checking) enforcement also computes the appropriate corrections for the mask polygon edges, then applies them in the manner as described above to determine the skeletal element positions and/or By modifying the parameters, this can be done. Thus, standard MRC checks to be used for polygons can be applied, and then the violation information can be used to guide skeletal geometry operations to resolve MRC violations. 5 , boundary segments 512 and 514 of polygonal representation 510 are the two segments closest to each other. They are too close, creating a mask rule violation. A polygon-based MRC check identifies these two boundary segments and rule violations. Segment 512 is associated with node N1 of the upper skeleton, and segment 514 is associated with edge E1 of the lower skeleton. These framework elements 550 can then be modified in a manner that reduces or eliminates MRC violations.

Another way to compute the estimated MRC result is to compute the distances between adjacent skeletons and skeleton elements. 6 shows two separate skeletons 650 and 655 . The skeleton 655 is for a folded shape, such as a U-shape, for example. Note that they are skeletons themselves, not shapes. The boundaries of the shapes are omitted for clarity. Double arrows show the locations of possible MRC violations. Given the distance between two skeletons at these locations and their corresponding magnitude parameters, MRC spacing violations can be evaluated.

Such detection may be accomplished by using edge-to-edge search algorithms. Alternatively, this may be done by creating additional “MRC” skeletons 670 , 675 of the mask skeletons 650 , 655 . In this figure, the MRC skeletons are shown with dashed lines, and these skeletons contain information about which mask skeleton edges are closest to them and how far away they are. This information can be used to compute MRC violation locations. This is a useful technique, since bone generation naturally determines which edges of the skeleton 655 can be compared to each other to determine MRC spacing violations.

7 illustrates an example set 700 of processes used during design, verification, and fabrication of an article of manufacture, such as an integrated circuit, to transform and verify design data and instructions representing the integrated circuit. Each of these processes may be structured and enabled as multiple modules or operations. The term 'EDA' refers to the term 'electronic design automation'. These processes begin with the creation of a product idea 710 with information supplied by a designer, and the information is transformed for the creation of an article of manufacture using a set of EDA processes 712 . When the design is complete, the design is taped out 734 , which is the point at which artwork (eg, geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture a set of masks and the mask. The set is later used to fabricate integrated circuits. After tape out, the semiconductor die is fabricated 736 , and packaging and assembly processes 738 are performed to create the finished integrated circuit 740 .

Specifications for a circuit or electronic structure can range from low level transistor material layouts to high level description languages. A high level of abstraction may be used to design circuits and systems using a hardware description language ('HDL') such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. HDL descriptions can be translated into logic level register transfer level ('RTL') descriptions, gate level descriptions, layout level descriptions, or mask level descriptions. Each lower abstraction level, which is a less abstract description, adds more useful detail to the design description, eg, more details about the modules that contain the description. Lower abstraction levels, less abstract descriptions, may be generated by a computer, derived from a design library, or generated by another design automation process. An example of a specification language in a lower abstraction level language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits having multiple analog components. Descriptions at each level of abstraction are enabled for use by corresponding tools in that layer (eg, a formal verification tool). The design process may use the sequence shown in FIG. 7 . The processes described may be enabled by EDA products (or tools).

During system design 714, the functionality of the integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as reduction in power consumption, performance, area (physical and/or code lines), and costs. Partitioning of the design into different types of modules or components may occur at this stage.

During logical design and functional verification 716, modules or components within a circuit are specified in one or more descriptive languages, and specifications are checked for functional correctness. For example, components of a circuit may be verified to produce outputs that match the requirements of the specification of the circuit or system being designed. Functional verification can use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized systems of components referred to as 'emulators' or 'prototyping systems' are used to speed up functional verification.

During synthesis and design for test 718, the HDL code is converted into a netlist. In some embodiments, the netlist may be a graph structure, wherein the edges of the graph structure represent components of a circuit, and nodes of the graph structure represent how the components are interconnected. Both HDL codes and netlists are hierarchical articles of manufacture that can be used by EDA products to verify that an integrated circuit performs according to a specified design when manufactured. The netlist may be optimized for the target semiconductor manufacturing technology. Additionally, the completed integrated circuit may be tested to verify that the integrated circuit meets the requirements of the specification.

During netlist verification 720 , the netlist is checked for compliance to timing constraints and correspondence to HDL codes. During design planning 722, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

During layout or physical implementation 724, physical placement (locating circuit components such as transistors or capacitors) and routing (connection of circuit components by multiple conductors) occur and enable certain logical functions A selection of cells from the library to allow can be performed. As used herein, the term 'cell' refers to transistors, other components that provide Boolean logic functions (eg, AND, OR, NOT, XOR) or storage functions (eg, flip-flops or latches), and A set of interconnections can be specified. As used herein, a circuit 'block' may refer to two or more cells. Both a cell and a circuit block may be referred to as a module or component, and are enabled with both physical structures and simulations. Parameters such as size are specified for selected cells (based on 'standard cells') and made accessible in a database for use by EDA products.

During analysis and extraction 726, circuit functions are verified at the layout level, which allows refinement of the layout design. During physical verification 728 , the layout design is checked to ensure that manufacturing constraints such as DRC constraints, electrical constraints, and lithography constraints are correct and that the circuitry function matches the HDL design specification. During resolution enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

During tape out, data is generated that will be used (after lithographic enhancements have been applied if appropriate) for the creation of lithographic masks. During mask data preparation 732 , the 'tape out' data is used to create lithographic masks that are used to create the completed integrated circuits.

The storage subsystem of a computer system (eg, computer system 800 of FIG. 8 ) is a library and development of cells for programs and data structures, and libraries used by some or all of the EDA products described herein. can be used to store products used for physical and logical design using

8 illustrates an example machine of computer system 800 , within which a set of instructions may be executed to cause the machine to perform any one or more of the methods discussed herein. In alternative implementations, the machine may be connected (eg, networked) to other machines on a LAN, intranet, extranet, and/or the Internet. A machine may operate in the capacity of a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or in a cloud computing infrastructure or environment. It can act as a client machine.

A machine is a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, web device, server, network router, switch or bridge, or It can be any machine capable of executing (sequentially or otherwise) a set of instructions. Additionally, although a single machine is illustrated, the term “machine” also refers to individually or collectively executing a set (or multiple sets) of instructions to perform any one or more of the methods discussed herein. It will be understood to include any collection of machines.

Exemplary computer system 800 includes processing device 802, main memory 804 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), static memory ( 806 (eg, flash memory, static random access memory (SRAM), etc.), and a data storage device 818 , which communicate with each other via a bus 830 .

Processing device 802 represents one or more processors, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or of instruction sets. It may be processors that implement the combination. The processing device 802 may also be one or more special purpose processing devices, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, and the like. The processing device 802 may be configured to execute instructions 826 for performing the operations and steps described herein.

Computer system 800 may further include a network interface device 808 for communicating via network 820 . The computer system 800 also includes a video display unit 810 (eg, a liquid crystal display (LCD) or cathode ray tube (CRT)), an alphanumeric input device 812 (eg, a keyboard), a cursor control device 814 (eg, , mouse), a graphics processing unit 822 , a signal generating device 816 (eg, a speaker), a graphics processing unit 822 , a video processing unit 828 , and an audio processing unit 832 .

The data storage device 818 may include a machine-readable storage medium 824 (also known as a non-transitory computer-readable medium), on the machine-readable storage medium 824 , the method described herein. One or more sets of software or instructions 826 implementing any one or more of the functions or functions are stored. Instructions 826 may also reside fully or at least partially within processing device 802 and/or main memory 804 during their execution by computer system 800 , main memory 804 and processing Device 802 also constitutes machine-readable storage media.

In some implementations, instructions 826 include instructions for implementing functionality corresponding to the present disclosure. Although machine-readable storage medium 824 is shown as being a single medium in the example implementation, the term "machine-readable storage medium" is a single medium or multiple media (eg, centralized centralized or distributed database and/or associated caches and servers). The term “machine-readable storage medium” may also store or encode a set of instructions for execution by a machine, and cause the machine and processing device 802 to perform any one or more of the methods of the present disclosure. It will be understood to include any medium that makes it happen. Accordingly, the term “machine-readable storage medium” will be understood to include, but is not limited to, solid state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of actions that produces a desired result. Operations are operations that require physical manipulations of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities, and are merely convenient indications applied to these quantities. Unless specifically indicated otherwise, and as apparent from this disclosure, throughout this description, specific terms refer to data expressed as physical (electronic) quantities within registers and memories of a computer system, computer system memories. or to operations and processes of a computer system or similar electronic computing device that manipulate and transform into other data similarly represented as physical quantities in registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. Such an apparatus may be specially constructed for its intended purposes, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium such as floppy disks, optical disks, CD-ROMs and any type of disk including magneto-optical disks, read-only memories (ROMs), random access memory ( RAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each of which is a computer system bus is coupled to

The algorithms and displays provided herein are not inherently related to any particular computer or other device. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

The present disclosure may be provided as software or a computer program product that may include a machine-readable medium having stored thereon instructions that may be used to program a computer system (or other electronic devices) to perform a process in accordance with the present disclosure. have. Machine-readable media includes any mechanism for storing information in a form readable by a machine (eg, a computer). For example, a machine readable (eg, computer readable) medium may be a machine readable (eg, computer readable) medium such as read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, and the like. (eg, computer) readable storage media.

In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of implementations of the present disclosure as set forth in the following claims. When this disclosure refers to some elements in the singular, more than one element may be shown in the figures, and like elements are labeled with like numbers. Accordingly, the present disclosure and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (20)

As a method,
accessing a layout used in a mask development process for a lithographic mask, the layout including a plurality of discrete shapes;
determining, by a processor, skeletal representations for at least some of the discrete shapes in the layout, wherein the skeletal representations of individual shapes are at least some of the elements and elements of two or more nodes connected by edges. including size parameters for −; and
using the skeletal representations in the mask development process;
A method comprising According to claim 1,
The individual shape is a polygon,
Determining the skeletal representation of the individual shape comprises:
determining a Voronoi diagram for the polygon; and
Determining the skeletal representation from the Voronoi diagram
A method comprising According to claim 1,
and the nodes and the edges of the skeletal representation of the individual shape are based on morphological erosion of the individual shape. According to claim 1,
wherein the individual shape is reconfigurable by morphological dilation of the nodes and the edges of the skeletal representation of the individual shape according to the size parameters for the nodes and the edges. According to claim 1,
and the size parameters for the edges of the skeletal representations are based on widths of the individual shapes along those edges. According to claim 1,
and the size parameters for the nodes of the skeletal representations are based on local radii of the respective shapes at those nodes. According to claim 1,
and the edges correspond to the axes of the respective shapes. 8. The method of claim 7,
wherein the axis is branched. According to claim 1,
the mask development process is one of optical proximity correction and inverse lithography;
Using the skeleton representations in the mask development process comprises:
determining an impact on a cost function on the mask development process resulting from changes in positions of the elements of the skeleton representations. According to claim 1,
the mask development process is one of optical proximity correction and inverse lithography;
Using the skeleton representations in the mask development process comprises:
determining an impact on a cost function on the mask development process resulting from changes in the size parameters of the skeleton representations. According to claim 1,
The mask development process is mask rule checking,
Using the skeleton representations in the mask development process comprises:
determining a spacing between the two shapes in the layout based on the spacing between the elements of the skeletal representations for the two shapes and based on the size parameters of the elements. As a system,
a memory storing instructions; and
a processor coupled with the memory and for executing the instructions
including,
The instructions, when executed, cause the processor to:
access a layout used in a mask development process for a lithographic mask, the layout including a plurality of discrete shapes;
determine skeletal representations for at least some of the discrete shapes in the layout, the skeletal representation of an individual shape comprising elements of two or more nodes connected by edges and size parameters for at least some of the elements Ham-,
use the skeleton representations in the mask development process. 13. The method of claim 12,
wherein the layout is a mask layout for a mask being developed by the mask development process. 13. The method of claim 12,
wherein the layout is one of an aerial image created by the lithography mask and a printed pattern created on a wafer by the lithography mask. 13. The method of claim 12,
The individual shape is a polygon,
Determining the skeletal representation of the individual shape comprises:
determining a Voronoi diagram for the polygon; and
Determining the skeletal representation from the Voronoi diagram
comprising, a system. 13. The method of claim 12,
and the nodes and the edges of the skeletal representation of the individual shape are based on morphological erosion of the individual shape. 13. The method of claim 12,
wherein the individual shape is reconfigurable by morphological expansion of the nodes and the edges of the skeletal representation of the individual shape according to the size parameters for the nodes and the edges. A non-transitory computer-readable medium comprising:
stored instructions;
The instructions, when executed by a processor, cause the processor to:
access a layout used in a mask development process for a lithographic mask, the layout including a plurality of discrete shapes;
determine skeletal representations for at least some of the discrete shapes in the layout, the skeletal representation of an individual shape comprising elements of two or more nodes connected by edges and size parameters for at least some of the elements Ham-,
provide the skeleton representations for use in the mask development process. 19. The method of claim 18,
the mask development process is one of optical proximity correction and inverse lithography;
Using the skeleton representations in the mask development process comprises:
and determining an effect on a cost function for the mask development process resulting from changes in the skeleton representations. 19. The method of claim 18,
The mask development process is mask rule checking,
Using the skeleton representations in the mask development process comprises:
and determining, based on the skeleton representations of the two shapes, a spacing between the two shapes in the layout.

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