CN113254871B - 矩阵处理装置 - Google Patents

矩阵处理装置 Download PDF

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Publication number
CN113254871B
CN113254871B CN202110566425.9A CN202110566425A CN113254871B CN 113254871 B CN113254871 B CN 113254871B CN 202110566425 A CN202110566425 A CN 202110566425A CN 113254871 B CN113254871 B CN 113254871B
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sparse
unit
matrix
elements
dense matrix
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CN113254871A (zh
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拉维·纳拉亚纳斯瓦米
拉胡尔·纳加拉扬
禹同爀
克里斯多佛·丹尼尔·利里
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Google LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • G—PHYSICS
    • G16—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS
    • G16Z—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR SPECIFIC APPLICATION FIELDS, NOT OTHERWISE PROVIDED FOR
    • G16Z99/00—Subject matter not provided for in other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3059—Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3059—Digital compression and data reduction techniques where the original information is represented by a subset or similar information, e.g. lossy compression
    • H03M7/3062—Compressive sampling or sensing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Databases & Information Systems (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Human Computer Interaction (AREA)
  • Complex Calculations (AREA)
CN202110566425.9A 2016-02-05 2017-01-13 矩阵处理装置 Active CN113254871B (zh)

Priority Applications (1)

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CN202110566425.9A CN113254871B (zh) 2016-02-05 2017-01-13 矩阵处理装置

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US15/016,486 US9898441B2 (en) 2016-02-05 2016-02-05 Matrix processing apparatus
US15/016,486 2016-02-05
CN202110566425.9A CN113254871B (zh) 2016-02-05 2017-01-13 矩阵处理装置
CN201710025656.2A CN107045492B (zh) 2016-02-05 2017-01-13 矩阵处理装置

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CN113254871A CN113254871A (zh) 2021-08-13
CN113254871B true CN113254871B (zh) 2024-09-03

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EP (1) EP3203381A1 (enExample)
JP (2) JP6626433B2 (enExample)
KR (2) KR101936396B1 (enExample)
CN (2) CN113254871B (enExample)
BR (1) BR102016031034A2 (enExample)
SG (1) SG10201610912UA (enExample)
TW (1) TWI661315B (enExample)

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KR102848548B1 (ko) * 2018-11-06 2025-08-25 한국전자통신연구원 딥러닝 모델 압축 및 압축 해제 방법 그리고 장치
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ES3041900T3 (en) * 2019-03-15 2025-11-17 Intel Corp Architecture for block sparse operations on a systolic array
CN110489428B (zh) * 2019-08-26 2020-05-22 上海燧原智能科技有限公司 多维稀疏矩阵压缩方法、解压缩方法、装置、设备及介质
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
US11663746B2 (en) 2019-11-15 2023-05-30 Intel Corporation Systolic arithmetic on sparse data
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US11971885B2 (en) * 2021-02-10 2024-04-30 Adobe Inc. Retrieval aware embedding
CN112712456A (zh) * 2021-02-23 2021-04-27 中天恒星(上海)科技有限公司 Gpu处理电路结构

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TWI661315B (zh) 2019-06-01
US20170228344A1 (en) 2017-08-10
BR102016031034A2 (pt) 2018-11-21
SG10201610912UA (en) 2017-09-28
TW201734845A (zh) 2017-10-01
KR101936396B1 (ko) 2019-01-08
EP3203381A1 (en) 2017-08-09
JP2017138966A (ja) 2017-08-10
CN107045492B (zh) 2021-06-11
KR102099221B1 (ko) 2020-04-09
CN113254871A (zh) 2021-08-13
JP2020061167A (ja) 2020-04-16
US9898441B2 (en) 2018-02-20
JP6626433B2 (ja) 2019-12-25
CN107045492A (zh) 2017-08-15
JP7023917B2 (ja) 2022-02-22
KR20190003849A (ko) 2019-01-09
US9880976B2 (en) 2018-01-30
US20170228342A1 (en) 2017-08-10
KR20170093697A (ko) 2017-08-16

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