CN113253530B

CN113253530B - Display panel and display device

Info

Publication number: CN113253530B
Application number: CN202110795431.1A
Authority: CN
Inventors: 龙春平
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Technology Development Co Ltd
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2021-09-17
Anticipated expiration: 2041-07-14
Also published as: CN113253530A

Abstract

The disclosure relates to the technical field of display, in particular to a display panel and a display device, which are used for optimizing touch experience. The display panel comprises a display substrate and a touch functional layer. In two adjacent groups of first signal lines on the display substrate, the distance between two first signal lines corresponding to the positions in the second direction is p₁. On the touch control functional layer, the distance between the centers of two adjacent first connecting parts or two adjacent second connecting parts in the second direction is m₁. Wherein p is₁=a₁×p₀₁,m₁=b₁×m₀₁。a₁And b₁Is positively correlated, and a₁＞b₁. The display panel is used for realizing touch control and display functions.

Description

Display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

With the continuous development of electronic products, a display device having a touch function and a display function can realize simple and flexible human-computer interaction, and thus is widely applied.

An AMOLED (Active Matrix Organic Light-Emitting Diode) display device can realize a full-screen, a narrow frame, high resolution, curling wearing, folding, and the like, and becomes an important development direction in the display technology field.

The higher the pixel resolution of the current display devices, the higher the fineness of the displayed pictures. However, the resolution of the touch function (i.e. the touch resolution) is still generally set empirically, which results in that the current touch resolution is not adapted to the display device with high pixel resolution to a high degree, which affects the touch effect of the display device.

Disclosure of Invention

The embodiment of the disclosure provides a display panel and a display device, and aims to enable touch resolution to change along with the change of pixel resolution by enabling the touch resolution and the pixel resolution to correspond to each other, so that touch experience is optimized, and the problem that the adaptation degree of the display device with the current touch resolution and the high pixel resolution is not high is solved.

In order to achieve the purpose, the embodiment of the disclosure adopts the following technical scheme:

in one aspect, there is provided a display panel including: the touch control display device comprises a display substrate and a touch control functional layer, wherein the touch control functional layer is arranged on the display substrate.

The display substrate comprises a plurality of pixel circuits arranged in an array mode and a plurality of first signal lines extending along a first direction. The plurality of first signal lines are arranged in parallel along a second direction; the plurality of first signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of first signal lines; in two adjacent groups of first signal lines, the distance between two first signal lines corresponding to the positions in the second direction is p₁(ii) a The first direction is a row direction in which the plurality of pixel circuits are arranged in an array manner, and the second direction is a column direction in which the plurality of pixel circuits are arranged in an array manner.

The touch control functional layer comprises a plurality of first touch control units extending along a first direction and a plurality of second touch control units extending along a second direction, the plurality of first touch control units are arranged in parallel along the second direction, the plurality of second touch control units are arranged in parallel along the first direction, and the plurality of first touch control units and the plurality of second touch control units are electrically insulated; each first touch unit comprises a plurality of first touch electrodes and a plurality of first connecting parts, and every two adjacent first touch electrodes are electrically connected through the first connecting parts; each second touch unit comprises a plurality of second touch electrodes and a plurality of second connecting parts, and every two adjacent second touch electrodes are electrically connected through the second connecting parts; the distance between the centers of two adjacent first connecting parts in the second direction and the distance between the centers of two adjacent second connecting parts in the second direction are both m₁。

Wherein p is₁=a₁×p₀₁, m₁=b₁×m₀₁；p₀₁A preset reference value for the distance between two first signal lines in the second direction corresponding to the positions of two adjacent first signal lines, a₁M is a scaling factor of the target pixel resolution of the display panel relative to the reference pixel resolution in a second direction₀₁Are two second adjacent in the second directionA predetermined reference value of the distance between the centers of one connecting portion or two adjacent second connecting portions, b₁A scaling factor of the target touch resolution of the display panel relative to the reference touch resolution in a second direction is obtained; a is₁And b₁Is positively correlated, and a₁＞b₁。

In some embodiments, the display substrate further includes a plurality of second signal lines extending in the second direction, the plurality of second signal lines being juxtaposed in the first direction; the plurality of second signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of second signal lines; in two adjacent groups of second signal lines, the distance between two second signal lines corresponding to the positions in the first direction is p₂. The distance between the centers of two adjacent first connecting parts in the first direction and the distance between the centers of two adjacent second connecting parts in the first direction are both m₂。

Wherein p is₂=a₂×p₀₂, m₂=b₂×m₀₂；p₀₂A preset reference value a for the distance between two second signal lines corresponding to the positions of two adjacent second signal lines in the first direction₂M is a scaling factor of a target pixel resolution of the display panel relative to a reference pixel resolution in a first direction₀₂A preset reference value for the distance between the centers of two adjacent first connecting parts or two adjacent second connecting parts in the first direction, b₂A scaling factor of a target touch resolution of the display panel relative to a reference touch resolution in a first direction; a is₂And b₂Is positively correlated, and a₂＞b₂。

In some embodiments, p₁=p₂，m₁=m₂，p₀₁= p₀₂，m₀₁=m₀₂，a₁=a₂，b₁=b₂。

In some embodiments, a-b ≧ 0.1; wherein, a₁=a₂=a，b₁=b₂=b。

In some embodiments, the display panel is substantially rectangular; wherein a-b is more than or equal to 0.20 and less than or equal to 0.25.

In some embodiments, the display panel is substantially rectangular; the length d of the diagonal line of the display panel is less than or equal to 16.51cm, and a-b is more than or equal to 0.12 and less than or equal to 0.19.

In some embodiments, the display panel is substantially rectangular; the length d of the diagonal line of the display panel is larger than 16.51cm, and a-b is larger than or equal to 0.26.

In some embodiments, 30 μm ≦ p₀≤50μm，3500μm≤m₀Less than or equal to 4500 μm; wherein p is₀₁= p₀₂=p₀，m₀₁=m₀₂=m₀。

In some embodiments, p₀=40μm，m₀=4000μm。

In some embodiments, each set of the first signal lines includes an enable signal line, at least one scan signal line, and at least one initialization signal line.

In two adjacent groups of first signal lines, the distance between two enable signal lines in the second direction is p₁(ii) a And/or the distance between two scanning signal lines corresponding to the position in the second direction is p₁(ii) a And/or the distance between the two initialization signal lines corresponding to the positions in the second direction is p₁。

In some embodiments, the display substrate further includes a plurality of second signal lines extending in the second direction, the plurality of second signal lines being juxtaposed in the first direction; the plurality of second signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of second signal lines; each group of second signal lines comprises a data line and a power line; in two adjacent groups of second signal lines, the distance between two data lines in the first direction is p₂(ii) a And/or the distance between the two power lines in the first direction is p₂。

In some embodiments, the first touch unit and/or the second touch unit comprises a metal mesh structure; the display substrate comprises a plurality of sub-pixels, each sub-pixel comprises a light emitting device and a pixel circuit electrically connected with the light emitting device; at least one grid of the metal grid structure corresponds to one or more sub-pixels, and an orthographic projection of the grid on the display substrate at least partially overlaps the corresponding one or more sub-pixels.

In some embodiments, the light emitting layer patterns of the light emitting devices of the one or more sub-pixels are located within an orthographic projection range of the corresponding grid on the display substrate; and/or the boundary of the pixel defining layer opening where the light emitting layer pattern of the light emitting device of the one or more sub-pixels is located is positioned within the orthographic projection range of the corresponding grid on the display substrate; and/or the pixel circuits of the one or more sub-pixels are located within the orthographic projection range of the corresponding grid on the display substrate.

In some embodiments, an orthographic projection of grid lines of the metal grid structure on the display substrate at least partially overlaps with at least one first signal line; and/or the display substrate further comprises a plurality of second signal lines extending along a second direction, and the orthographic projection of the grid lines of the metal grid structure on the display substrate is at least partially overlapped with at least one second signal line; and/or an orthographic projection of grid lines of the metal grid structure on the display substrate at least partially overlaps with at least one transistor of the pixel circuit; and/or an orthographic projection of the grid lines of the metal grid structure on the display substrate at least partially overlaps with an anode of the light-emitting device; and/or the orthographic projection of the grid lines of the metal grid structure on the display substrate is overlapped with at least part of the connecting pattern electrically connected with the light-emitting device and the corresponding pixel circuit.

In some embodiments, the pixel circuit includes at least one oxide thin film transistor including an oxide active layer pattern; the orthographic projection of a gap between the metal grid structures of the adjacent first touch electrode and the second touch electrode on the display substrate is staggered with the oxide active layer pattern.

In some embodiments, the pixel circuit includes at least one low temperature polysilicon thin film transistor including a low temperature polysilicon active layer pattern and at least one oxide thin film transistor including an oxide active layer pattern; the oxide active layer pattern is farther from a substrate of the display substrate relative to the low temperature polysilicon active layer pattern in a thickness direction of the display substrate.

In some embodiments, the touch functional layer further comprises at least one first virtual electrode; the first virtual electrode is arranged in a gap area between the adjacent first touch electrode and the second touch electrode, and is electrically insulated from the first touch electrode and the second touch electrode.

In some embodiments, the first dummy electrode includes a bar-shaped first body portion, and a plurality of first protrusions; the plurality of first protrusions are arranged around the first main body part and connected with the first main body part.

In some embodiments, a ratio of a dimension of the first protrusion in a direction perpendicular to a direction in which a length of the first body portion extends to a length of the first body portion is less than or equal to 0.1.

In some embodiments, the touch functional layer further comprises at least one second virtual electrode; the second virtual electrode is arranged in the touch electrode of one of the first touch unit and the second touch unit with a longer length, and the second virtual electrode is electrically insulated from the touch electrode where the second virtual electrode is located.

In some embodiments, the second dummy electrode includes a polygonal second body portion, and a plurality of second protrusions; the plurality of second protrusions are arranged around the second main body part and connected with the second main body part.

In some embodiments, a ratio of a dimension of the second protrusion in a direction perpendicular to a side of the second body portion to which it is attached to a length of the side of the second body portion to which it is attached is less than or equal to 0.1.

In some embodiments, at least one of the plurality of first touch electrodes and the plurality of second touch electrodes is a first selected touch electrode, at least one side of which is provided with a first virtual electrode, and the inside of which is provided with a second virtual electrode.

In some embodiments, the touch functional layer further includes at least one third connecting portion, the first dummy electrode on one side of the first selected touch electrode and the second dummy electrode inside the first selected touch electrode are electrically connected through the third connecting portion, and the third connecting portion is electrically insulated from the first selected touch electrode.

In some embodiments, the touch functional layer includes a touch electrode layer, an insulating layer, and a bridge layer, which are stacked, where the bridge layer is located on a side of the touch electrode layer close to or far from the display substrate; the first virtual electrode, the second virtual electrode and the first selected touch electrode are positioned on the touch electrode layer, and the third connecting part is positioned on the bridge layer; the third connecting portion is electrically connected with the first virtual electrode and the second virtual electrode through a via hole formed in the insulating layer.

In some embodiments, at least one of the plurality of first touch electrodes and the plurality of second touch electrodes includes a rectangular third main body portion, and at least one finger-shaped auxiliary electrode; the auxiliary electrode is disposed on at least one side of the third main body portion and electrically connected to the third main body portion.

In some embodiments, a distance m between a length of the auxiliary electrode and centers of two first connecting portions adjacent in the second direction₁The ratio of (A) to (B) is 0.2-0.4; and/or; a distance m between a length of the auxiliary electrode and centers of two second connection portions adjacent in the first direction₂The ratio of (A) to (B) is 0.2 to 0.4.

In some embodiments, a distance m between a width of the auxiliary electrode and centers of two first connection portions adjacent in the second direction₁The ratio of (A) to (B) is 0.1-0.3; and/or; a distance m between a width of the auxiliary electrode and centers of two second connection portions adjacent in the first direction₁The ratio of (A) to (B) is 0.1 to 0.3.

In some embodiments, the length extension direction of the auxiliary electrode forms an included angle of 60 ° to 120 ° with the edge of the third main body connected to the auxiliary electrode.

In some embodiments, a plurality of auxiliary electrodes are disposed in a gap region between adjacent first touch electrodes and adjacent second touch electrodes, the plurality of auxiliary electrodes belong to the adjacent first touch electrodes and adjacent second touch electrodes, respectively, and the plurality of auxiliary electrodes are disposed in a staggered manner.

In some embodiments, two opposite auxiliary electrodes are disposed between two adjacent first touch electrodes, and the two opposite auxiliary electrodes belong to the two adjacent first touch electrodes respectively; the two opposite auxiliary electrodes are electrically connected through a first connecting part; and/or; two opposite auxiliary electrodes are arranged between two adjacent second touch control electrodes, and the two opposite auxiliary electrodes respectively belong to the two adjacent second touch control electrodes; the two opposite auxiliary electrodes are electrically connected through the second connecting part.

In some embodiments, the display panel is provided with at least one opening, and the opening at least penetrates through the touch functional layer; the aperture of the open hole is smaller than the distance m between the centers of two adjacent first connecting parts in the second direction₁(ii) a And/or the aperture of the open hole is smaller than the distance m between the centers of two adjacent second connecting parts in the first direction₂。

In some embodiments, the aperture occupies at least a portion of each of the two first touch electrodes and the two second touch electrodes; the two first touch electrodes and the two second touch electrodes occupied by the openings are second selected touch electrodes, and the area occupied by each second selected touch electrode by the opening accounts for less than 0.5 of the area of one complete touch electrode.

In some embodiments, the two first touch electrodes and the two second touch electrodes occupied by the aperture are second selected touch electrodes; the touch control function layer further comprises a first electrode ring arranged along the circumferential direction of the opening, the first electrode ring comprises a plurality of first electrode arcs arranged at intervals, and at least one second selected touch control electrode is electrically connected with one first electrode arc.

In some embodiments, the touch functional layer further includes a second electrode ring disposed along a circumferential direction of the opening, and the second electrode ring is located inside the first electrode ring with a gap therebetween.

In some embodiments, the first electrode ring has a width W₁The width of the second electrode ring is W₂，W₁/W₂The value of (A) is 0.4 to 0.6.

In some embodiments, a ratio of an area of the opening to an area of the second selected touch electrode is R, and a width of the second electrode ring is W₂，W₂=K₁×R+K₂(ii) a Wherein, K₁And K₂Is a preset threshold value, K is more than or equal to 240₁≤280，-80≤K₂≤-40。

In some embodiments, a ratio of an area of the opening to an area of the second selected touch electrode is R, a distance between the first electrode ring and the second electrode ring is D, and D = K₃×R+K₄(ii) a Wherein, K₃And K₄Is a preset threshold value, K is more than or equal to-1500₃≤-100，50≤K₄≤100。

In some embodiments, in the case where the opening occupies two first touch electrodes and two second touch electrodes, for the adjacent first touch electrodes and second touch electrodes, a part of the first electrode arc is located on a side of the first touch electrode close to the center of the opening, and another part of the first electrode arc is located on a side of the second touch electrode close to the center of the opening.

In some embodiments, the first electrode ring comprises four first electrode arcs; the two first touch electrodes and the two second touch electrodes occupied by the openings are electrically connected with the four first electrode arcs in a one-to-one correspondence manner.

In some embodiments, the first electrode ring comprises four first electrode arcs; the two first touch electrodes or the two second touch electrodes occupied by the openings are electrically connected with the two first electrode arcs in a one-to-one correspondence mode, and the other two first electrode arcs float.

In another aspect, a display device is provided, which includes the display panel according to any one of the above embodiments.

The display panel and the display device provided by the embodiment of the disclosure have the following beneficial effects:

the scaling coefficient of the touch functional layer is positively correlated with the scaling coefficient of the display substrate, so that the touch resolution is positively correlated with the pixel resolution, namely, the touch resolution is changed along with the change of the pixel resolution, the adaptation of the touch resolution and the pixel resolution is realized, and the touch precision and the touch effect of the display device are improved.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a top view of a display device provided in accordance with some embodiments;

FIG. 2 is a cross-sectional view taken along section line AA' in FIG. 1;

FIG. 3 is a pixel drive architecture diagram of a display substrate provided in accordance with some embodiments;

FIG. 4 is an equivalent circuit diagram of the pixel circuit of one sub-pixel in FIG. 3;

FIG. 5 is a top view of some of the layers of the pixel circuit corresponding to FIG. 4;

FIG. 6 is a top view of another layer of the pixel circuit corresponding to FIG. 4;

FIG. 7 is a top view of the stacked layers of FIGS. 5 and 6;

FIG. 8 is a top view of still other layers of the pixel circuit corresponding to FIG. 4;

FIG. 9 is a top view of the stacked layers of FIGS. 5, 6 and 8;

FIG. 10 is a top view of still other layers of the pixel circuit corresponding to FIG. 4;

FIG. 11 is a top view of the stacked layers of FIGS. 5, 6, 8 and 10;

FIG. 12 is a top view of still other layers of the pixel circuit corresponding to FIG. 4;

FIG. 13 is a top view of the stacked layers of FIGS. 5, 6, 8, 10 and 12;

FIG. 14 is a top view of still further layers of the pixel circuit corresponding to FIG. 4;

FIG. 15 is a top view of the stacked layers of FIGS. 5, 6, 8, 10, 12 and 14;

FIG. 16 is a top view of FIG. 15 with section lines BB' added;

FIG. 17 is a top view of FIG. 15, with section line CC' added;

FIG. 18 is a top view of FIG. 15, taken along line DD';

FIG. 19 is a top view of FIG. 15, taken along the lines EE';

FIG. 20 is a sectional view taken along section line BB' in FIG. 16;

FIG. 21 is a sectional view taken along section line CC' in FIG. 17;

FIG. 22 is a sectional view taken along section line DD' in FIG. 18;

FIG. 23 is a cross-sectional view taken along section line EE' in FIG. 19;

FIG. 24 is a top view of a touch functional layer provided in accordance with some embodiments;

FIG. 25 is a block diagram of the area indicated by the dashed box G in FIG. 24;

FIG. 26 is a section view along section line GG' of FIG. 25;

FIG. 27 is another block diagram of the area indicated by the dashed box G in FIG. 24;

FIG. 28 is a sectional view taken along section line FF' in FIG. 27;

FIG. 29 is a top view of a plurality of pixel circuits provided in accordance with some embodiments;

FIG. 30 is a block diagram of a touch electrode with a metal mesh structure provided in accordance with some embodiments;

FIG. 31 is a top view of a portion of a display panel provided in accordance with some embodiments;

FIG. 32 is a corresponding top view of a pixel circuit and a metal grid in a display panel provided in accordance with some embodiments;

FIG. 33 is a block diagram of portions of a touch functional layer provided in accordance with some embodiments;

FIG. 34 is a block diagram of a first virtual electrode provided in accordance with some embodiments;

FIG. 35 is another block diagram of portions of a touch functional layer provided in accordance with some embodiments;

FIG. 36 is yet another block diagram of portions of a touch functional layer provided in accordance with some embodiments;

FIG. 37 is a block diagram of a second virtual electrode provided in accordance with some embodiments;

FIG. 38 is another block diagram of a second virtual electrode provided in accordance with some embodiments;

FIG. 39 is yet another block diagram of a portion of a touch functional layer provided in accordance with some embodiments;

FIG. 40 is yet another block diagram of portions of a touch functional layer provided in accordance with some embodiments;

FIG. 41 is yet another block diagram of a portion of a touch functional layer provided in accordance with some embodiments;

FIG. 42 is another top view of a display panel provided in accordance with some embodiments;

FIG. 43 is a structural view of a touch functional layer in the area of the opening in FIG. 41;

FIG. 44 is a further structural view of a touch functional layer in the area of the opening in FIG. 41;

fig. 45 is a structural view of another touch functional layer in the area where the opening is formed in fig. 41.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, expressions of "electrically connected" and "connected" and derivatives thereof may be used. For example, the term "point-of-connection" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, "approximate" or "approximately" includes the stated value as well as the average value within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

In the present disclosure, the "pixel resolution" refers to the number of sub-pixels included in the display panel, and may be represented by m × n, where m represents the number of sub-pixels included in one row, and n represents the number of sub-pixels included in one column. In the case where the screen size (i.e., the length and width of the display substrate) is the same, the larger the number of sub-pixels, the higher the pixel resolution, and the finer the display effect.

Similarly, the "touch resolution" refers to the number of touch electrodes included in the display panel, and can be represented by p × q, where p represents the number of touch electrodes included in a row, and q represents the number of touch electrodes included in a column. In the case of the same screen size (i.e., the length and the width of the display substrate), the larger the number of the touch electrodes is, the higher the touch resolution is, and the more sensitive the touch effect is.

Fig. 1 shows a top view structure of a display device. As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, and the display device 100 may be a television, a mobile phone, a computer, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a car computer, or the like.

The display device 100 includes a display panel 200. The Display panel 200 may be a Liquid Crystal Display (LCD); the display panel 200 may also be an electroluminescent display panel or a photoluminescent display panel. In the case that the display panel 200 is an electroluminescent display panel, the electroluminescent display panel may be an Organic Light-Emitting Diode (OLED) display panel or a Quantum Dot electroluminescent (QLED) display panel. In the case where the display panel 200 is a photoluminescent display panel, the photoluminescent display device may be a quantum dot photoluminescent display panel.

Fig. 2 shows a cross-sectional structure of the display panel 200 in fig. 1 at a section line AA'. As shown in fig. 2, in some embodiments, the display panel 200 is an OLED display panel, and the display panel 200 includes a display substrate 10, an encapsulation layer 20 for encapsulating the display substrate 10, and a touch function layer 30. Here, the sealing layer 20 may be a sealing film or a sealing substrate. The touch function layer 30 may be separately formed on a substrate 40 and then stacked on the encapsulation layer 20. The touch function Layer 30 can also be directly formed On the package Layer 20, which is called as FMLOC (flexible Metal Layer On cell) technology, and a lighter and thinner touch panel can be manufactured by using the FMLOC technology, and the technology can be applied to a folded and curled OLED display device.

As shown in fig. 2 and 3, the display substrate 10 includes a plurality of sub-pixels P (see fig. 3) arranged in an array, and each sub-pixel P includes a light emitting device L and a pixel circuit 11 disposed on a substrate 40. The pixel circuit 11 includes a plurality of thin film transistors TFT, only one of which is exemplarily shown in fig. 2. The light emitting device L includes an anode L1, a light emitting functional layer L2, and a cathode L3. Here, the anode L1 is electrically connected to the Source or Drain of the thin film transistor TFT, and fig. 2 shows a case where the anode L1 is electrically connected to the Drain of the thin film transistor TFT.

The Light Emitting device L may be an Organic Light Emitting Diode (OLED).

In some embodiments, the light emitting function layer L2 includes a light emitting layer pattern. In other embodiments, the light emitting function layer L2 includes one or more of an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), a Hole Transport Layer (HTL), and a Hole Injection Layer (HIL) in addition to the light emitting layer pattern.

When the display apparatus 100 is an electroluminescent display apparatus or a photoluminescent display apparatus, the display apparatus 100 may be a top emission type display apparatus, in which case the anode L1 near the substrate 40 is opaque and the cathode L3 far from the substrate 40 is transparent or translucent; the display device 100 may also be a bottom emission type display device, in which case the anode L1 near the substrate 40 is transparent or translucent and the cathode L3 far from the substrate 40 is opaque; the display device 100 may also be a double-sided light-emitting type display device, in which case the anode L1 near the substrate 40 and the cathode L3 far from the substrate 40 are both transparent or translucent.

Illustratively, as shown in fig. 2, the thin film transistor TFT includes a Gate electrode Gate, a Source electrode Source, a Drain electrode Drain, and an active layer pattern 12.

The control electrode of each TFT used in the pixel circuit 11 is a gate electrode of the TFT, the first electrode is one of a Source electrode Source and a Drain electrode Drain of the TFT, and the second electrode is the other of the Source electrode Source and the Drain electrode Drain of the TFT. Since the Source and Drain of the tft may be symmetrical in structure, the Source and Drain may be indistinguishable in structure, that is, the first and second poles of the tft in the embodiments of the present disclosure may be indistinguishable in structure. Exemplarily, in the case that the thin film transistor is a P-type transistor, a first pole of the transistor is a Source, and a second pole of the transistor is a Drain; illustratively, in the case where the tft is an N-type tft, the first electrode of the tft is a Drain electrode Drain, and the second electrode of the tft is a Source electrode Source.

In some embodiments, the pixel circuits 11 use Low Temperature Polysilicon Oxide (LTPO) technology, that is, one pixel circuit 11 includes both Low Temperature Polysilicon (LTPS) thin film transistors and Oxide (Oxide) thin film transistors. In this case, the pixel circuit 11 has two active layers at the same time, wherein the active layer pattern of the LTPS tft is made of low temperature polysilicon, and the active layer pattern of the oxide tft is made of oxide. Optionally, the LTPS thin film transistor is of a top-gate structure, and the oxide thin film transistor is of a bottom-gate structure. Alternatively, as shown in fig. 20, the LTPS thin film transistor (refer to transistors T3, T4 in fig. 20) is a top gate structure, and the oxide thin film transistor (refer to transistors T1, T2 in fig. 20) is a double gate structure in which two gates of the oxide thin film transistor are located above and below an active layer pattern thereof, respectively.

On the basis of the foregoing, along the thickness direction of the display substrate 10 and the direction (refer to the direction Z in fig. 2) away from the display substrate 10, the film layers for forming the pixel circuit 11 sequentially include the semiconductor layer (i.e., the film layer where the active layer pattern 12 is located), the Gate conductive layer (i.e., the film layer where the Gate electrode is located), and the Source/Drain conductive layer (i.e., the film layer where the Source and Drain electrodes Drain are located).

In addition, as shown in fig. 2, the display substrate 10 further includes a pixel defining layer PDL including a plurality of openings K (shown in fig. 20 to 23), and one light emitting device L is disposed in one opening K.

As shown in fig. 2, the display substrate 10 further includes a planarization layer PLN disposed between the thin film transistor TFT and the anode L1.

In addition, as shown in fig. 2, the display substrate 10 may further include: the Buffer layer Buffer is located between the substrate 40 and the semiconductor layer, the gate insulating layer GI is located between the semiconductor layer and the gate conductive layer, the interlayer dielectric layer ILD is located between the gate conductive layer and the source drain conductive layer, and the passivation layer PVX is located between the source drain conductive layer and the planarization layer PLN.

It should be noted that fig. 2 only illustrates that the display substrate 10 includes a semiconductor layer, a gate conductive layer, and a source/drain conductive layer, in some other embodiments, the display substrate 10 may include multiple semiconductor layers, multiple gate conductive layers, or multiple source/drain conductive layers; for example, as shown in fig. 20, the display substrate 10 includes two semiconductor layers, three gate conductive layers, and two source-drain conductive layers. It is understood that, in the case that the display substrate 10 includes a plurality of semiconductor layers, a plurality of gate conductive layers or a plurality of source/drain conductive layers, the number of gate insulating layers GI, interlayer dielectric layers ILD or planarization layers PLN for isolating two adjacent conductive layers is increased accordingly. The structure of the film shown in fig. 20 will be described in detail later.

The structure of one sub-pixel P in the display substrate 10 is described above, and the pixel driving architecture of the display substrate 10 will be described below.

Fig. 3 shows a pixel driving architecture of the display substrate 10. In some embodiments, as shown in fig. 3, the display substrate 10 includes a plurality of sub-pixels P, and for convenience of description, the sub-pixels P are arranged in a matrix for example.

As shown in fig. 3, the display substrate 10 has a display Area (AA Area for short) and a peripheral Area S.

Wherein, the peripheral area S is located on at least one side of the AA area. For example, the peripheral area S may be located at the AA area by one turn.

The plurality of sub-pixels P of the display substrate 10 are disposed on the substrate 40 (see fig. 2) of the display substrate 10 and located in the AA region. The plurality of sub-pixels P include at least a sub-pixel capable of displaying a first color, a sub-pixel capable of displaying a second color, and a sub-pixel capable of displaying a third color; the first, second and third colors are three primary colors (e.g., red, green and blue).

On this basis, each sub-pixel P includes a pixel circuit 11 (see fig. 2) and a light emitting device L (see fig. 2), the pixel circuit 11 is electrically connected to the corresponding light emitting device L, and the pixel circuit 11 is used for driving the light emitting device L to operate.

As shown in fig. 3, the subpixels P arranged in a row in the first direction X (i.e., the row direction) are referred to as a row of subpixels, and the subpixels P arranged in a row in the second direction Y (i.e., the column direction) are referred to as a column of subpixels.

On this basis, in some embodiments, the display substrate 10 further includes a plurality of gate lines G 'and a plurality of data lines D'. Each gate line G 'is electrically connected to a row of sub-pixels P, and in a case where the display substrate 10 includes n rows of sub-pixels P, the display substrate 10 includes n gate lines G' (1) to G '(n), and the gate lines G' are used to transmit gate signals to the sub-pixels P to control the switching of the sub-pixels P. Each data line D 'is electrically connected to a row of sub-pixels P, and in the case that the display substrate 10 includes m rows and columns of sub-pixels P, the display substrate 10 includes m data lines D' (1) to D '(m), and the data lines D' are used for transmitting data signals to the sub-pixels P to control the gray scale of the sub-pixels P.

The pixel driving architecture of the display substrate 10 is described above, and the circuit configuration and layout configuration of the pixel circuit 11 for driving the sub-pixel P will be described below.

The circuit structure of the pixel circuit 11 can be implemented in various ways, for example, structures such as 7T1C and 3T2C, which are not limited by the embodiments of the present disclosure.

Fig. 4 shows a circuit configuration of the pixel circuit 11. As shown in fig. 4, in some embodiments, the pixel circuit 11 employs LTPO technology and has a structure of 7T1C (i.e., one pixel circuit 11 includes 7 tfts and 1 storage capacitor). The pixel circuit 11 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

The first transistor T1 is a reset transistor for resetting the first node, the second transistor T2 is a diode-connected transistor, the third transistor T3 is a driving transistor, the fourth transistor T4 is a data writing transistor, the fifth transistor T5 and the sixth transistor T6 are emission control transistors, and the seventh transistor T7 is a reset transistor for resetting the light emitting device.

In some embodiments, T3, T4, T5, T6, and T7 are P-type LTPS transistors, making these transistors have higher mobility and more stable source voltage suitable for driving light emitting devices, e.g., OLED devices; the T1 and T2 are N-type Oxide transistors, so that the reset transistor and the diode-connected transistor have lower leakage current, and the voltage of the driving transistor and the storage capacitor can be kept stable better.

In the circuit shown in fig. 4, the nodes N1, N2, N3, and N4 do not represent actual components, but represent junctions of the relevant electrical connections in the circuit diagram, that is, the nodes are equivalent nodes of the junctions of the relevant electrical connections in the circuit diagram.

As shown in fig. 5 to 15, the pixel circuit 11 using the LTPO technique finally forms the respective transistors in the equivalent circuit shown in fig. 4 by superimposing the required pattern film layers by etching.

In an exemplary embodiment, as shown in fig. 5, a P-type LTPS transistor is formed.

Illustratively, a first semiconductor layer LTPS is formed first, and optionally, the first semiconductor layer is a Low Temperature Polysilicon (LTPS) material.

A first Gate conductive layer Gate1 is formed on the first semiconductor layer LTPS, and overlapping portions of the first Gate conductive layer Gate1 and the first semiconductor layer LTPS form a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, which are P-type, respectively. The third transistor T3 is used as a driving transistor, and the active layer pattern has a longer channel and a smaller width-to-length ratio, which is beneficial to reducing current fluctuation and improving the stability of the output current.

Optionally, a first Gate insulating layer GI1 (refer to fig. 20) is disposed between the first semiconductor layer LTPS and the first Gate conductive layer Gate 1.

Optionally, the first Gate conductive layer Gate1 includes an enable signal line EM, a first Scan signal line Scan1, a second Scan line Scan2, and a bottom plate Cst1 of the storage capacitor.

Wherein, the overlapped portion of the enable signal line EM and the first semiconductor layer LTPS forms a fifth transistor T5 and a sixth transistor T6, the overlapped portion of the first Scan signal line Scan1 and the first semiconductor layer LTPS forms a fourth transistor T4, the overlapped portion of the second Scan signal line Scan2 and the first semiconductor layer LTPS forms a seventh transistor T7, and the overlapped portion of the lower plate Cst1 of the storage capacitor and the first semiconductor layer LTPS forms a third transistor T3, i.e., the lower plate Cst1 of the storage capacitor simultaneously serves as the gate of the third transistor T3.

In an exemplary embodiment, as shown in fig. 6, an N-type Oxide transistor is formed.

Exemplarily, as shown in fig. 7, a second Gate conductive layer Gate2 is formed on the first Gate conductive layer Gate 1.

Optionally, an underlying interlayer dielectric layer ILD0 (refer to fig. 20) is disposed between the first Gate conductive layer Gate1 and the second Gate conductive layer Gate 2.

A second semiconductor layer Oxide is formed on the second Gate conductive layer Gate 2. Optionally, the second semiconductor layer is an Oxide (Oxide) material. The overlapping portions of the second Gate conductive layer Gate2 and the second semiconductor layer Oxide form a first transistor T1 and a second transistor T2 of N-type, respectively.

Optionally, a first interlayer dielectric layer ILD1 (see fig. 20) is disposed between the second Gate conductive layer Gate2 and the second semiconductor layer Oxide.

In the case where the first and second transistors T1 and T2 have a double Gate structure, the second Gate conductive layer Gate2 is disposed under the second semiconductor layer Oxide, forming bottom gates of the first and second transistors T1 and T2.

Alternatively, the second Gate conductive layer Gate2 includes the first initialization signal line Vini1, a lower portion Scan3 (a) of the third Scan signal line, a lower portion Scan4 (a) of the fourth Scan signal line, and an upper plate Cst2 of the storage capacitor.

The overlapped portion of the lower portion Scan3 (a) of the third Scan signal line and the second semiconductor layer Oxide forms a first transistor T1, and the overlapped portion of the lower portion Scan4 (a) of the fourth Scan signal line and the second semiconductor layer Oxide forms a second transistor T2.

The first initialization signal line Vini1 is used to transmit the first initialization signal to the first transistor T1, and thus it does not overlap the second semiconductor layer Oxide, avoiding the formation of a transistor.

The upper plate Cst2 of the storage capacitor constitutes the storage capacitor Cst together with the lower plate Cst1 of the storage capacitor in the first Gate conductive layer Gate1, and the upper plate Cst2 of the storage capacitor is provided with a via hole H1 so as to expose the first Gate conductive layer Gate1 corresponding to the third transistor T3.

In an exemplary embodiment, as shown in fig. 8, the top gate of the N-type Oxide transistor is formed so as to constitute a double gate structure.

Exemplarily, as shown in fig. 9, a third Gate conductive layer Gate3 is formed on the second semiconductor layer Oxide, and the third Gate conductive layer Gate3 and the second Gate conductive layer Gate2 are at least partially overlapped, so that the first transistor T1 and the second transistor T2 form a double Gate structure, and further reduce leakage current of both, thereby better keeping the voltage of the driving transistor and the storage capacitor Cst stable.

Optionally, a second Gate insulating layer GI2 is disposed between the second semiconductor layer Oxide and the third Gate conductive layer Gate3 (see fig. 20).

Alternatively, the third Gate conductive layer Gate3 includes an upper layer portion Scan3 (b) of the third Scan signal line and an upper layer portion Scan4 (b) of the fourth Scan signal line.

An overlapping portion of the upper layer portion Scan3 (b) of the third Scan signal line and the second semiconductor layer Oxide forms a top gate of the first transistor T1, and an overlapping portion of the upper layer portion Scan4 (b) of the fourth Scan signal line and the second semiconductor layer Oxide forms a top gate of the second transistor T2. The lower portion Scan3 (a) and the upper portion Scan3 (b) of the third Scan signal line overlap, and the lower portion Scan4 (a) and the upper portion Scan4 (b) of the fourth Scan signal line overlap, so that a transistor of a double gate structure is formed.

The lower portion Scan3 (a) and the upper portion Scan3 (b) of the third Scan signal line are commonly used as the third Scan signal line Scan3, and the lower portion Scan4 (a) and the upper portion Scan4 (b) of the fourth Scan signal line are commonly used as the fourth Scan signal line Scan 4.

In an exemplary embodiment, as shown in fig. 10, a first source drain conductive layer SD1 is formed.

Illustratively, as shown in fig. 11, a second interlayer dielectric ILD2 (refer to fig. 20) is formed on the third Gate conductive layer Gate3, and a first source drain conductive layer SD1 is formed on the second interlayer dielectric ILD 2.

Optionally, the second interlayer dielectric layer ILD2 is at least disposed at a position where the third Gate conductive layer Gate3 and the first source drain conductive layer SD1 overlap, and the second interlayer dielectric layer ILD2 is used for insulating the third Gate conductive layer Gate3 from the first source drain conductive layer SD 1.

Optionally, a plurality of via holes H2 to H12 are disposed on the second interlayer dielectric layer ILD2, and the first source-drain conductive layer SD1 includes a second initialization signal line Vini2 and first connection patterns M1 to sixth connection patterns M6.

Wherein the second initialization signal line Vinit2 is electrically connected with the active layer pattern of the seventh transistor T7 through a via H12.

One end of the first connection pattern M1 is electrically connected to the first pole of the fifth transistor T5 through the via H2, and the other end is electrically connected to the upper plate Cst2 of the storage capacitor Cst through the via H3.

The second connection pattern M2 is electrically connected with the second pole of the sixth transistor T6 through the via H4.

One end of the third connection pattern M3 is electrically connected to the gate electrode of the third transistor T3 (i.e., the lower plate Cst1 of the storage capacitor Cst) through the via H5, and the other end is electrically connected to the second pole of the first transistor T1 and the second pole of the second transistor T2 through the via H6.

One end of the fourth connection pattern M4 is electrically connected to the second pole of the third transistor T3 through the via H7, and the other end is electrically connected to the first pole of the second transistor T2 through the via H8.

The fifth connection pattern M5 is electrically connected to the first pole of the fourth transistor T4 through the via H9.

One end of the sixth connection pattern M6 is electrically connected to the first pole of the first transistor T1 through the via H10, and the other end is electrically connected to the first initialization signal line Vini1 through the via H11.

Alternatively, the second initialization signal line Vini2 is designed in an inverted "shape such that an orthogonal projection of at least a portion thereof (the portion including at least the portion of the second initialization signal line Vini2 that intersects the second semiconductor layer Oxide) on the substrate 40 overlaps an orthogonal projection of the third scanning signal line Scan3 on the substrate 40, that is, at least a portion of the second initialization signal line Vini2 is located above the third scanning signal line Scan 3. Therefore, the third Scan signal line Scan3 can be used to shield the influence of the second initialization signal line Vini2 on the first transistor T1 and the second transistor T2, so that the first transistor T1 and the second transistor T2 have stable high on-state current and low leakage current, and thus the voltages of the driving transistor (i.e., T3) and the storage capacitor Cst are more stable and are not easy to leak, so that the driving current of the driving transistor is more stable, the light emitting efficiency of the light emitting device is more stable, and the display quality is improved.

In an exemplary embodiment, as shown in fig. 12, a second source drain conductive layer SD2 is formed.

Illustratively, as shown in fig. 13, a first planarization layer PLN1 (refer to fig. 20) is formed on the first source-drain conductive layer SD1, and a second source-drain conductive layer SD2 is formed on the first planarization layer PLN 1.

Optionally, vias H13 to H15 are disposed on the first planarizing layer PLN1, and the second source-drain conductive layer SD2 includes a Data line Data, a power line VDD, and a seventh connection pattern M7.

Here, the Data line Data is connected to the fifth connection pattern M5 through the via H13, thereby being finally electrically connected to the first pole of the fourth transistor T4.

The power line VDD is electrically connected to the first connection pattern M1 through the via H14 such that the power line VDD passes through the first connection pattern M1 and is finally electrically connected to the first pole of the fifth transistor T5 and to the upper plate Cst2 of the storage capacitor Cst.

The seventh connection pattern M7 is electrically connected with the second connection pattern M2 through the via H15.

In an exemplary embodiment, as shown in fig. 14, an Anode layer Anode is formed.

Illustratively, as shown in fig. 15, a second planarization layer PLN2 (refer to fig. 20) is formed on the second source-drain conductive layer SD2, and an Anode layer Anode is formed on the second planarization layer PLN 2.

The second planarization layer PLN2 is provided with a via H16, the Anode layer Anode includes a plurality of anodes L1 and Anode extensions M8, each Anode L1 is electrically connected to one Anode extension M8 in the same layer, and the Anode extension M8 is electrically connected to the seventh connection pattern M7 through the via H16, so that the Anode L1 sequentially passes through the Anode extension M8, the seventh connection pattern M7, and the second connection pattern M2, and is finally electrically connected to the second electrode of the sixth transistor T6.

In this way, the electrical connection of the pixel circuit 11 and the anode L1 of the light emitting device L is realized, so that the pixel circuit 11 can be used to transmit a voltage signal to the anode L1 of the light emitting device L to drive the light emitting device L to emit light.

In an alternative embodiment, as shown in fig. 14 and 15, a pixel defining layer PDL is formed on the Anode layer Anode, the pixel defining layer PDL being provided with a plurality of openings K exposing the Anode layer Anode, each opening K to define an effective light emitting region of one light emitting device L.

Based on the above, fig. 20 to 23 show the cross-sectional structures of the display substrate 10 along the section line BB 'in fig. 16, the section line CC' in fig. 17, the section line DD 'in fig. 18, and the section line EE' in fig. 19. Fig. 15 to 19 show the same structure, and in order to clearly show the respective hatching lines, the hatching lines are shown in fig. 16 to 19.

As can be seen from fig. 20, the first transistor T1 is a double-gate type transistor, the first gate of which is electrically connected to the first initialization signal line Vinit1 through the sixth connection pattern M6 in the first source-drain conductive layer SD 1; the second electrode is electrically connected to the first electrode of the storage capacitor Cst (i.e., the lower plate Cst 1) through the third connection pattern M3 in the first source-drain conductive layer SD1 (not shown in fig. 20). The first transistor T1 is configured to initialize the lower plate Cst1 of the storage capacitor Cst and the gate electrode of the third switching transistor T3 with the first initialization signal transmitted by the first initialization signal line Vini1 under the control of the third Scan signal line Scan 3.

The second transistor T2 is a double-gate transistor, and its first electrode is electrically connected to the second electrode of the third transistor T3; the second electrode is electrically connected to the first electrode of the storage capacitor Cst (i.e., the lower plate Cst 1) through the third connection pattern M3 in the first source-drain conductive layer SD1 (not shown in fig. 20). The second transistor T2 is configured to compensate for a threshold voltage of the third transistor T3 under the control of the third Scan signal line Scan 3.

As can be seen from fig. 20 and 21, the gate of the third transistor T3 is a first electrode (i.e., the lower plate Cst 1) of the storage capacitor Cst, and the second electrode (i.e., the upper plate Cst 2) of the storage capacitor Cst together constitute the storage capacitor Cst, and the first electrode of the storage capacitor Cst is further electrically connected to the second semiconductor layer Oxide, that is, the gate of the third transistor T3 is electrically connected to the second electrode of the first transistor T1 and the second electrode of the second transistor T2.

A first electrode of the fourth transistor T4 is electrically connected to the Data line Data through the third connection pattern M3 in the first source-drain conductive layer SD 1; the second pole is directly electrically connected with the first pole of the third transistor T3 (i.e., electrically connected between the active layer patterns of the fourth transistor T4 and the third transistor T3). The fourth transistor T4 is configured to transmit a data signal to the third transistor T3 under the control of the first Scan signal line Scan 1.

As can be seen from fig. 22, the first pole of the fifth transistor T5 is electrically connected to the first connection pattern M1 in the first source-drain conductive layer SD1, and since the first connection pattern M1 is electrically connected to the power supply line VDD, the first pole of the fifth transistor T5 is finally electrically connected to the power supply line VDD. The gate of the fifth transistor T5 is formed by an enable signal line EM, and the fifth transistor T5 is configured to transmit a power supply signal on a power supply line VDD to the third transistor T3 under the control of the enable signal line EM.

As can be seen from fig. 22 and 23, the second pole of the sixth transistor T6 is finally electrically connected to the anode L1 of the light emitting device L through the second connection pattern M2, the seventh connection pattern M7, and the anode extension M8, which are sequentially connected. A first pole of the sixth transistor T6 is directly electrically connected to the second pole of the third transistor T3 (i.e., the sixth transistor T6 is directly electrically connected to the active layer pattern of the third transistor T3).

As can be seen from fig. 23, the upper plate Cst2 of the storage capacitor Cst is provided with a via hole H1, and the upper plate Cst2 is electrically connected to the first connection pattern M1 in the first source-drain conductive layer SD1 to be finally connected to the power supply line VDD.

The above is an introduction to the structure of the display substrate 10 of the display panel 200 provided in the embodiment of the present disclosure. Referring to fig. 2 again, as can be seen from the above description, the display panel 200 further includes an encapsulation layer 20 disposed on the light-emitting side of the display substrate 10, and a touch-control functional layer 30 disposed on a side of the encapsulation layer 20 away from the display substrate 10. The structure of the touch function layer 30 will be described below.

Fig. 24 shows a structure of the touch functional layer 30. As shown in fig. 24, in some embodiments, the touch functional layer 30 includes a plurality of first touch units 31 extending along the first direction X and a plurality of second touch units 32 extending along the second direction Y, the plurality of first touch units 31 are arranged side by side along the second direction Y, the plurality of second touch units 32 are arranged side by side along the first direction X, and the plurality of first touch units 31 are electrically insulated from the plurality of second touch units 32.

Each first touch unit 31 includes a plurality of first touch electrodes Tx and a plurality of first connecting portions Br1, and two adjacent first touch electrodes Tx are electrically connected through a first connecting portion Br 1; each second touch unit 32 includes a plurality of second touch electrodes Rx and a plurality of second connection portions Br2, and two adjacent second touch electrodes Rx are electrically connected through the second connection portions Br 2.

Alternatively, as shown in fig. 24, the first touch electrodes Tx and the second touch electrodes Rx are alternately disposed, adjacent different touch electrodes (i.e., between the first touch electrodes Tx and the second touch electrodes Rx) are insulated and can generate mutual capacitance, and the mutual capacitance values of the touch electrodes change after being touched, so that the touch position can be determined by detecting the mutual capacitance values and determining the change amount of the mutual capacitance values.

In some embodiments, each touch unit (i.e., the first touch unit 31 or the second touch unit 32) is connected to at least one touch line. For example, as shown in fig. 24, two ends of each first touch unit 31 are connected to the touch control lines 33, and two ends of each second touch unit 32 are connected to the touch control lines 33. The Touch lines 33 connected to the first Touch units 31 and the Touch lines 33 connected to the second Touch units 32 are gathered in the binding region V through the peripheral region S, and are finally electrically connected to a Touch processor (Touch IC, not shown in fig. 24).

In an alternative embodiment, the first direction X and the second direction Y are arranged crosswise, for example, the first direction X and the second direction Y may be perpendicular to each other. For example, the first direction X may be a lateral direction of the display device 100, and the second direction Y may be a longitudinal direction of the display device 100; alternatively, the first direction X may be a row direction in which pixels of the display apparatus 100 are arranged, and the second direction Y may be a column direction in which pixels of the display apparatus 100 are arranged.

In the drawings of the present disclosure, only the first direction X is taken as a row direction, and the second direction Y is taken as a column direction for illustration, and in the present disclosure, a technical solution obtained by rotating the drawings by 90 degrees is within the protection scope of the present disclosure.

In an alternative embodiment, the first touch electrode Tx and the second touch electrode Rx are diamond-shaped or substantially diamond-shaped. The term "substantially diamond" refers to that the shape of the touch electrodes (i.e. the first touch electrode Tx and the second touch electrode Rx) is a diamond shape as a whole, but is not limited to a standard diamond shape, for example, the boundaries of the touch electrodes are allowed to be non-linear (e.g. zigzag), and as in the following embodiments, the shape of the touch electrodes as a whole is a diamond shape, but the boundaries are zigzag.

In alternative embodiments, the electrode pattern shapes of the first touch electrode Tx and the second touch electrode Rx in the embodiments of the present disclosure are not limited to a diamond shape or a substantially diamond shape, and may also be a rectangular shape, a long strip shape, and the like.

In an optional embodiment, the first touch unit 31 includes 15 to 20 first touch electrodes Tx, and the second touch unit 32 includes 30 to 40 second touch electrodes Rx.

In an exemplary embodiment, as shown in fig. 25, in the first direction X, every two adjacent first touch electrodes Tx are directly electrically connected, and the first connection portion Br1 is on the same layer as the first touch electrodes Tx. Along the second direction Y, every two adjacent second touch units 32 are bridged by a second connecting portion Br2, and the second connecting portion Br2 and the second touch electrode Rx are respectively located on different film layers. In this case, the first touch electrode Tx, the second touch electrode Rx, and the first connection portion Br1 are in the same layer.

In an alternative embodiment, as shown in fig. 26, the touch function layer 30 includes a touch electrode layer 2A, an insulating layer 2B and a bridge layer 2C stacked on the display substrate 10, the insulating layer 2B is located between the touch electrode layer 2A and the bridge layer 2C, and the bridge layer 2C is located on a side of the touch electrode layer 2A close to or far from the display substrate 10. Fig. 26 shows a cross-sectional structure of the touch function layer 30 along a cross-sectional line GG' in fig. 25, wherein the bridge layer 2C is located on a side of the touch electrode layer 2A away from the display substrate 10. The insulating layer 2B has a plurality of via holes Hx therein, and the second connection portion Br2 electrically connects two adjacent second touch electrodes Rx through the via holes Hx.

In an exemplary embodiment, as shown in fig. 27, in the second direction Y, every two adjacent second touch electrodes Rx are directly electrically connected, and the second connection portion Br2 is on the same layer as the second touch electrodes Rx. Along the first direction X, every two adjacent first touch electrodes 31 are bridged by a first connecting portion Br1, and the first connecting portion Br1 and the first touch electrode Tx are located on different film layers respectively. In this case, the first touch electrode Tx, the second touch electrode Rx, and the second connection portion Br2 are in the same layer.

In an alternative embodiment, as shown in fig. 28, the touch function layer 30 includes a touch electrode layer 2A, an insulating layer 2B and a bridge layer 2C stacked on the display substrate 10, the insulating layer 2B is located between the touch electrode layer 2A and the bridge layer 2C, and the bridge layer 2C is located on a side of the touch electrode layer 2A close to or far from the display substrate 10. Fig. 28 shows a cross-sectional structure of the touch functional layer 30 along a cross-sectional line FF' in fig. 27, wherein the bridging layer 2C is located on the side of the touch electrode layer 2A close to the display substrate 10. The insulating layer 2B has a plurality of via holes Hx therein, and the first connection portion Br1 electrically connects two adjacent first touch electrodes Tx through the via holes Hx.

In an alternative embodiment, the touch electrode layer 2A is made of three layers of materials, i.e., Ti, Al, and Ti, and the thicknesses thereof are 400 μm, 1600 μm, and 400 μm, respectively; the bridging layer 2C is made of three layers of materials, namely Ti, Al and Ti, and the thicknesses of the bridging layer are respectively 400 mu m, 3000 mu m and 400 mu m; the insulating layer 2B is made of SiN material and has a thickness of 1800 μm.

With the rapid development of display technology, the demand for display panels 200 with high pixel resolution and various sizes is rapidly increasing, and therefore, scaling (i.e., reducing or enlarging) the pixel resolution of the display panel 200 is inevitable. For the scaling of the pixel resolution, in the embodiment of the present disclosure, the touch resolution of the touch functional layer 30 is also scaled, so that the touch resolution changes with the change of the pixel resolution, and thus the touch resolution is adapted to the pixel resolution, and the purpose of improving the touch effect can be achieved.

In this regard, the display substrate 10 includes a plurality of first signal lines in addition to a plurality of pixel circuits 11 (i.e., sub-pixels P) arranged in an array. As shown in fig. 29, each set of first signal lines G (see G (c) and G (d) in fig. 29) extends in the first direction X, and a plurality of sets of first signal lines G are juxtaposed in the second direction Y. Each group of first signal lines G includes a plurality of first signal lines, each first signal line G extends in the first direction X, and the plurality of first signal lines are arranged in parallel in the second direction Y.

In some embodiments, a set of first line number lines G is electrically connected to a row of subpixels; in the case where the display substrate 10 is provided with n rows of the subpixels P, the display substrate 10 includes n groups of the first signal lines G. Further, a set of first line number lines G is electrically connected to each of the subpixels P in a row of subpixels; further, each of the first signal lines in the group of first line number lines G is electrically connected to each of the subpixels P in the row of subpixels.

In an alternative embodiment, the set of first signal lines G includes an enable signal line EM, at least one initialization signal line (refer to Vini1 and Vini2 in fig. 29), and at least one Scan signal line (refer to Scan1, Scan3, and Scan4 in fig. 29).

Illustratively, as shown in fig. 29, the group of first line number lines G includes an enable signal line EM, a first initialization signal line Vini1, a second initialization signal line Vini2, a first Scan signal line Scan1, a third Scan signal line Scan3, and a fourth Scan signal line Scan 4.

Note that the second Scan signal line Scan2 electrically connected to the pixel circuits 11 in the current row is actually multiplexed with the first Scan signal line Scan1 electrically connected to the pixel circuits 11 in the previous row, and therefore the second Scan signal line Scan2 electrically connected to the pixel circuits 11 in the current row is not divided into the first signal lines G in the current group. For example, as shown in fig. 29, the second Scan signal line Scan2 (d) electrically connected to the pixel circuits 11 in the lower row multiplexes the Scan1 (c) electrically connected to the pixel circuits 11 in the upper row.

As shown in fig. 29, in some embodiments, in two adjacent groups of the first signal lines G (see G (c) and G (d) in fig. 29), the distance between two first signal lines corresponding to the positions in the second direction Y is p₁. That is, in two adjacent subpixels P of a column of subpixels, the distance between the first signal line connected to one subpixel P and the first signal line connected to the other subpixel P is P₁The two first signal lines are of the same type, and the two first signal lines are located at the same position in the pixel circuit 11 where they are electrically connected, respectively (for example, both located at the upper, middle, or lower portion of the pixel circuit 11).

For example, as shown in fig. 29, in the case that each group of the first signal lines G includes the enable signal line EM, two enable signal lines EM (c) and EM (d) in two adjacent groups of the first signal lines G (c) and G (d) correspond to each other in position, and have a distance p in the second direction Y₁。

For another example, in a case where each group of the first signal lines G includes at least one initialization signal line, in two adjacent groups of the first signal lines G, a distance between two corresponding initialization signal lines in the second direction Y is p₁. As shown in fig. 29, each group of the first signal lines G includes a first initialization signal line Vini1 and a second initialization signal line Vini2, and in two adjacent groups of the first signal lines G (c) and G (d), two first initialization signal lines Vini1 (c) and Vini1 (d) are located at corresponding positions and are spaced apart from each other by a distance p in the second direction Y₁(ii) a And/or the two second initialization signal lines Vini2 (c) and Vini2 (d) correspond in position and have a distance p in the second direction Y₁。

For another example, in the case where each group of the first signal lines G includes at least one scanning signal line, two scanning signal lines corresponding in position in two adjacent groups of the first signal lines G have a distance p in the second direction Y₁. As shown in fig. 29, each group of the first signal lines G includes a first Scan signal line Scan1, a third Scan signal line Scan3 and a fourth Scan signal line Scan4, and two of the adjacent groups of the first signal lines G (c), G (d) correspond to the Scan signal lines Scan1 (c) and Scan signal line 1 (d) at a distance p in the second direction Y₁(ii) a And/or the two third scanning signal lines Scan3 (c) and Scan3 (d) are corresponding in position, and the distance between the two third scanning signal lines Scan3 (c) and Scan3 (d) on the second Y is p₁(ii) a And/or the two fourth scanning signal lines Scan4 (c) and Scan4 (d) correspond in position and have a distance p in the second direction Y₁。

In some embodiments, the display substrate 10 further includes a plurality of sets of second signal lines D (see D (c) and D (D) in fig. 29), each set of second signal lines D extends along the second direction Y, and the plurality of sets of second signal lines D are arranged in parallel along the first direction X. Each group of second signal lines D includes a plurality of second signal lines, each second signal line extends in the second direction Y, and the plurality of second signal lines are arranged in parallel in the first direction X.

In some embodiments, a group of second signal lines D is electrically connected to a column of sub-pixels; in the case where the display substrate 10 is provided with m columns of the subpixels P, the display substrate 10 includes m sets of the second signal lines D. Further, a group of second signal lines D is electrically connected to each of the subpixels P in a column of subpixels; further, each of the second signal lines D in one group is electrically connected to each of the subpixels P in one column of subpixels.

In an alternative embodiment, the set of second signal lines D includes a Data line Data and a power supply line VDD.

As shown in fig. 29, in some embodiments, in two adjacent groups of second signal lines D (see D (c) and D (D) in fig. 29), the distance between two second signal lines corresponding to the positions in the first direction X is p₂. I.e. two adjacent sub-images in a row of sub-pixelsIn the pixel P, a distance between a second signal line connected to one sub-pixel P and a second signal line connected to another sub-pixel P is P₂The two second signal lines are of the same type, and the two second signal lines are located at the same position in the pixel circuit 11 where they are electrically connected respectively (for example, both located at the left, middle, or right side of the pixel circuit 11).

For example, as shown in fig. 29, in the case where each group of the second signal lines D includes Data lines Data, two Data lines Data (c) and Data (D) in two adjacent groups of the second signal lines D (c) and D (D) correspond to each other in position, and the distance between the two Data lines Data (c) and Data (D) in the first direction X is p₂。

For another example, in a case that each group of the second signal lines D includes the power line VDD, two power lines VDD (c) and VDD (D) in two adjacent groups of the second signal lines D (c) and D (D) correspond to each other, and a distance between the two power lines VDD (c) and VDD (D) in the first direction X is p₂。

In some embodiments, as shown in fig. 24, the distance between the corresponding positions of two adjacent first connecting portions Br1 in the second direction Y and the distance between the corresponding positions of two adjacent second connecting portions Br2 in the second direction Y are both m₁。

Illustratively, the distance between the centers of two adjacent first connecting portions Br1 in the second direction Y and the distance between the centers of two adjacent second connecting portions Br2 in the second direction Y are both m₁(ii) a Alternatively, the distance between the right ends of two adjacent first connecting portions Br1 in the second direction Y and the distance between the upper ends of two adjacent second connecting portions Br2 in the second direction Y are both m₁。

In some embodiments, as shown in fig. 24, the distance between the corresponding positions of two first connecting portions Br1 adjacent in the first direction X and the distance between the corresponding positions of two second connecting portions Br2 adjacent in the first direction X are both m₂。

Illustratively, the distance between the centers of two first connecting portions Br1 adjacent in the first direction X and the distance between the centers of two second connecting portions Br2 adjacent in the first direction XAll are m₂(ii) a Alternatively, the distance between the left ends of two adjacent first connecting portions Br1 in the first direction X and the distance between the lower ends of two adjacent second connecting portions Br2 in the first direction X are both m₂。

In the case that the size of the display panel 200 is not changed, the adjustment of the pixel resolution may be implemented by adjusting the pitch between two adjacent sub-pixels P in the first direction X, for example, if the pitch between two adjacent sub-pixels P in the first direction X is reduced, an extra space may be left in the first direction X, so that more sub-pixels P are arranged in the first direction X, and if the number of sub-pixels P arranged in the first direction X is increased, the pixel resolution in the first direction X is increased.

Similarly, under the condition that the size of the display panel 200 is not changed, the adjustment of the touch resolution may be implemented by adjusting the size of the adjacent touch electrodes, for example, if the size of two adjacent first touch electrodes Tx in the first direction X is reduced, an extra space is left in the first direction X, so that more first touch electrodes Tx are arranged in the first direction X, and the touch resolution in the first direction X is increased if the number of first touch electrodes Tx arranged in the first direction X is increased.

In the exemplary embodiment, in the second direction Y, the pixel resolution is scaled (increased or decreased), and then the spacing between two adjacent sub-pixels P is scaled (increased or decreased) by a certain factor, and accordingly, the spacing between two first signal lines in two adjacent groups of first signal lines G corresponding to the positions in the second direction Y is scaled by a certain factor.

Similarly, in the second direction Y, the touch resolution is scaled (increased or decreased), the sizes of two adjacent touch electrodes are scaled by a certain factor, and accordingly, the distance between the centers of two adjacent first connecting portions Br1 in the second direction Y and the distance between the centers of two adjacent second connecting portions Br2 in the second direction Y are scaled by a certain factor.

Wherein, the distance between two first signal lines corresponding to the two adjacent first signal lines G before the pixel resolution scaling in the second direction Y is set as a preset reference value p₀₁Two adjacent groups after pixel resolution scalingThe distance between two first signal lines corresponding to the first signal line G in the second direction Y is p₁The scaling factor of the pixel resolution in the second direction Y is a₁。

Setting the distance between the centers of two adjacent first connecting parts Br1 or two adjacent second connecting parts Br2 in the second direction Y before touch resolution scaling as a preset reference value m₀₁After the touch resolution is scaled, the distance between the centers of two adjacent first connecting portions Br1 or two adjacent second connecting portions Br2 in the second direction Y is m₁The scaling factor of the touch resolution in the second direction Y is b₁。

Wherein p is₁=a₁×p₀₁, m₁=b₁×m₀₁，a₁And b₁Is positively correlated, and a₁＞b₁. Therefore, in the second direction Y, the touch resolution changes with the change of the pixel resolution, that is, the touch resolution increases with the increase of the pixel resolution and decreases with the decrease of the pixel resolution, so as to ensure that the degree of adaptation between the touch function layer 30 and the display substrate 10 is higher before and after the zooming of the display panel 200, thereby improving the touch effect.

And, from a₁＞b₁It can be seen that, in the second direction Y, the scaling degree of the touch resolution is smaller than the scaling degree of the pixel resolution. Because the fineness required by image display is greater than the fineness required by touch point addressing, the pixel resolution is greater than the touch resolution, so that the touch resolution and the pixel resolution do not need to have the same zoom degree, namely, the zoom degree of the touch resolution is smaller than that of the pixel resolution, and the manufacturing difficulty of the touch structure can be reduced.

In the exemplary embodiment, in the first direction X, the pixel resolution is scaled (increased or decreased), and then the spacing between two adjacent sub-pixels P is scaled (increased or decreased) by a certain factor, and accordingly, the spacing between two corresponding second signal lines in two adjacent sets of second signal lines D in the first direction X is scaled by a certain factor.

Similarly, in the first direction X, the touch resolution is scaled (increased or decreased), and the sizes of two adjacent touch electrodes are scaled by a certain factor, and accordingly, the distance between the centers of two adjacent first connecting portions Br1 in the first direction X and the distance between the centers of two adjacent second connecting portions Br2 in the second direction Y are scaled by a certain factor.

Wherein, the distance between two second signal lines corresponding to the two adjacent second signal lines D before the pixel resolution scaling in the first direction X is set as a preset reference value p₀₂After the pixel resolution is scaled, the distance between two second signal lines corresponding to the positions in the two adjacent groups of second signal lines D in the first direction X is p₂The scaling factor of the pixel resolution in the first direction X is a₂(ii) a Setting the distance between the centers of two adjacent first connecting parts Br1 or two adjacent second connecting parts Br2 in the first direction X before touch resolution scaling as a preset reference value m₀₂After the touch resolution is scaled, the distance between the centers of two adjacent first connecting portions Br1 or two adjacent second connecting portions Br2 in the first direction X is m₂The scaling factor of the touch resolution in the first direction X is b₂。

Wherein p is₂=a₂×p₀₂, m₂=b₂×m₀₂，a₂And b₂Is positively correlated, and a₂＞b₂. Therefore, in the first direction X, the touch resolution changes with the change of the pixel resolution, that is, the touch resolution increases with the increase of the pixel resolution and decreases with the decrease of the pixel resolution, so as to ensure that the degree of adaptation between the touch function layer 30 and the display substrate 10 is high before and after the zooming of the display panel 200, thereby improving the touch effect.

And, from a₂＞b₂It can be known that, in the first direction X, the scaling degree of the touch resolution is smaller than the scaling degree of the pixel resolution. Since the image display requires a finer degree than the touch point addressing, the pixel resolution is larger than the touch resolution, so that the touch resolution and the pixel resolution do not have to be scaled to the same degree, i.e., the touch resolution can be scaled downThe zoom-in degree is smaller than the zoom-in degree of the pixel resolution, so that the manufacturing difficulty of the touch structure can be reduced.

In an exemplary embodiment, p₁=p₂，m₁=m₂，p₀₁= p₀₂，m₀₁=m₀₂，a₁=a₂，b₁=b₂. That is, in the first direction X and the second direction Y, the pitches between two adjacent sub-pixels P are equal, in both the first direction X and the second direction Y, the sizes of the touch electrodes are equal, the scaling degrees of the pixel resolutions in both the directions are equal, and the scaling degrees of the touch resolutions are also equal. Therefore, in the two directions of the first direction X and the second direction Y, the touch resolution changes with the change of the pixel resolution, that is, the touch resolution increases with the increase of the pixel resolution and decreases with the decrease of the pixel resolution, so as to ensure that the adaptation degree of the touch function layer 30 and the display substrate 10 is high before and after zooming in the two directions of the display panel 200, thereby improving the touch effect.

Exemplarily, if a₁=a₂=a，b₁=b₂And if b is not less than 0.1, a-b is not less than 0.1.

Optionally, the display panel 200 is substantially rectangular; a-b is more than or equal to 0.20 and less than or equal to 0.25; for example, a-b is 0.20, 0.22, 0.245, or 0.25.

Optionally, the display panel 200 is substantially rectangular; when the length d of the diagonal line of the display panel 200 is less than or equal to 16.51cm, a-b is less than or equal to 0.12 and less than or equal to 0.19. For example, a-b is 0.12, 0.15, 0.16, 0.17, 0.175, or 0.19.

Optionally, the display panel 200 is substantially rectangular; when the length d of the diagonal line of the display panel 200 is larger than 16.51cm, a-b is larger than or equal to 0.26. For example, a-b is 0.26, 0.265, 0.27, 0.285, or 0.29.

And correspondingly designing the corresponding relation between the touch resolution and the pixel resolution scaling coefficient according to the screen size, so that the nominal correlation relation between the touch resolution and the pixel resolution scaling coefficient is suitable for screens with different sizes, and the adaptation degree of the touch resolution and the pixel resolution of the screens with different sizes is ensured.

Is exemplified byIf p is₀₁= p₀₂=p₀，m₀₁=m₀₂=m₀And then p is more than or equal to 30 mu m₀≤50μm，3500μm≤m₀Less than or equal to 4500 μm. For example, p₀Is 30 μm, 35 μm, 40 μm or 50 μm, m₀3500 μm, 3600 μm, 4000 μm or 4500 μm.

Exemplarily, p₀=40μm，m₀=4000μm。

In some embodiments, the length d of the diagonal of the display panel 200 is less than or equal to 16.51cm, 0.12 a-b is less than or equal to 0.19; the length d of the diagonal line of the display panel 200 is larger than 16.51cm, and a-b is larger than or equal to 0.26. In this range, the display panel 200 has an excellent touch effect, and the specific verification process is as follows:

TABLE 1 (experiment one)

TABLE 2 (experiment two)

TABLE 3 (experiment three)

Table 4 (experiment four)

TABLE 5 (experiment five)

Table 6 (experiment six)

In the above experiment, p is₁=p₂=p，m₁=m₂=m，p₀₁= p₀₂= p₀，m₀₁=m₀₂=m₀，a₁=a₂=a，b₁=b₂=b。

The screen size refers to the length of the screen diagonal.

In the above experiment, the reference value corresponding to the sub-pixel is p₀The reference value corresponding to the touch electrode is m₀The final value corresponding to the sub-pixel is p, the final value corresponding to the touch electrode is m, the scaling coefficient corresponding to the sub-pixel is a, the scaling coefficient corresponding to the touch electrode is b, and the difference value between the scaling coefficients is a-b.

Through the analysis of the touch effect of the display panel 200 prepared in the first to sixth experiments, the following conclusion is obtained: in the first experiment, the third experiment, the fourth experiment and the fifth experiment, when the length d of the diagonal line of the screen is less than or equal to 16.51cm and a-b is greater than or equal to 0.12 and less than or equal to 0.19, the touch effect of the display panel 200 is good. In the second experiment and the sixth experiment, when the length d of the diagonal line of the screen is greater than 16.51cm, the touch effect of the display panel 200 is good when a-b is greater than or equal to 0.26. The "analysis of touch effects" may include performing tests of accuracy, finger separation, and response time, respectively.

Where "accuracy" refers to the maximum positioning error over a predefined area of the touch screen, measured in units of the linear distance between the actual finger position and the reported finger position. When the numerical range of a-b is not in the conclusion, the phenomenon that the finger position moves is sometimes displayed, however, the simulated finger actually moves linearly, and the phenomenon does not exist from experiment one to experiment six, so that the accuracy from experiment six to experiment six is better.

"finger separation" refers to the minimum distance between the centers of two fingers that the touchscreen controller can report when placed on the touchscreen. The finger separation measurement method is to place two simulated or mechanical fingers on the panel and move in opposite directions until the system reports that two fingers are one finger. Without good finger separation, a true multi-touch solution cannot be designed. Finger separation is particularly important for virtual keyboards because the separation between two fingers on the screen is typically short in this case. The finger spacing for experiments one to six was less than 10 mm.

"response time" refers to the time between finger contact time on the touch screen and the touch screen controller generating an interrupt signal. Response time measurement methods are to simulate finger motion with an electronic stimulus, or to physically move a simulated finger onto a panel. Response time is very important because it directly affects the speed at which the user moves a finger across the screen, performs "panning" or "flicking" operations, and writes with a finger or pen on the screen; a touchpad with a slow response time may pause briefly and fail to detect movement. The response time of the first experiment to the sixth experiment is relatively fast, and the response is sensitive.

Therefore, when the length of the diagonal line of the display panel 200 is less than or equal to 16.51cm, and the difference of the scaling coefficients is in the range of 0.12-0.19, the touch effect of the display panel 200 is good; when the length of the diagonal line of the display panel 200 is greater than 16.51cm, and the difference of the scaling coefficients is greater than or equal to 0.26, the touch effect of the display panel 200 is good.

In some embodiments, in the touch functional layer 30, the touch electrode adopts a metal mesh structure, and compared with a method of forming a planar electrode as a touch electrode by using ITO (Indium Tin Oxide), the touch electrode of the metal mesh structure has a small resistance and a high sensitivity, which can improve the touch sensitivity of the touch functional layer 30. The touch electrode adopting the metal mesh structure has high mechanical strength, so that the weight of the touch function layer 30 can be reduced, and when the touch function layer 30 is applied to the display device 100, the display device 100 can be thinned.

The touch electrodes of the metal mesh structure include first touch electrodes Tx and second touch electrodes Rx in the touch functional layer 30.

In some embodiments, as shown in fig. 30, the first touch electrode Tx and the second touch electrode Rx adopt a metal mesh structure. The metal grids WD of the first touch electrode Tx and the second touch electrode Rx are disposed in the touch electrode layer, and the metal grids WD of the first touch electrode Tx is disconnected from the metal grids WD of the second touch electrode Rx, so that the first touch electrode Tx and the second touch electrode Rx are insulated from each other.

It should be noted that, in fig. 30, the metal grids WD are filled with different patterns to distinguish different touch electrodes, and the metal grids WD of the first touch electrode Tx and the second touch electrode Rx may be formed by using the same material and the same process.

Illustratively, the wire width of the metal mesh WD is 2.8 μm to 4.2 μm, such as 2.8 μm, 3.0 μm, 3.5 μm, 3.8 μm, 4.0 μm or 4.2 μm.

In some embodiments, at least one metal mesh WD in the metal mesh structure corresponds to one or more sub-pixels P, and an orthographic projection of the metal mesh WD on the display substrate 10 at least partially overlaps the corresponding one or more sub-pixels P.

Optionally, the orthographic projection of one metal mesh WD overlaps one sub-pixel P (as shown in fig. 31). Alternatively, the mesh lines WD' of the metal mesh WD corresponding to the subpixels P displaying red have a length of 35 μm and a width of 31 μm; the length of the grid lines WD' of the metal grid WD corresponding to the sub-pixels P displaying blue color is 40 μm and the width is 35 μm; the grid lines WD' of the metal grid WD corresponding to the first subpixel P displaying green color have a length of 35 μm and a width of 32 μm; the mesh line WD' of the metal mesh WD corresponding to the second subpixel P displaying green color has a length of 31 μm and a width of 29 μm.

Optionally, the orthographic projection of one metal mesh WD overlaps with a plurality of sub-pixels P.

The metal grid of the touch electrode corresponds to at least one sub-pixel P, so that the effective facing area of the touch electrode and the sub-pixel P is maximized, the number of the sub-pixels P corresponding to the effective touch point is maximized in the touch process, the touch response time is shortened, the touch accuracy is increased, and the touch effect is optimized; meanwhile, the shielding of the effective light-emitting area of the sub-pixel P by the grid lines of the metal grid can be reduced, the light-emitting efficiency is improved, and the display effect is optimized.

In an exemplary embodiment, the pixel circuits 11 of one or more sub-pixels P are located within the orthographic projection range of the corresponding metal mesh WD on the display substrate 10. That is, one or more pixel circuits 11 are corresponding to the metal grid WD, so that the thin film transistor of the sub-pixel P is located right below the metal grid WD, the effective facing area of the sub-pixel P actual driving unit and the touch electrode is maximized, and the touch effect is optimized; meanwhile, the shielding of the grid lines WD' on the pixel circuits 11 of the sub-pixels P is reduced, so that the shielding of the effective light-emitting area of the sub-pixels P is reduced, and the light-emitting efficiency is improved.

In an exemplary embodiment, the light emitting layer patterns L2 (refer to fig. 2) of the light emitting devices L of one or more sub-pixels P are located within the orthographic projection range of the corresponding metal mesh WD on the display substrate 10; alternatively, the openings K (refer to fig. 15) of the pixel defining layer PDL in which the light emitting layer pattern L2 of the light emitting device L of one or more sub-pixels P is located are located within the orthogonal projection range of the corresponding metal mesh WD on the display substrate 10. That is, by corresponding one or more light emitting devices L to the metal mesh WD of the touch electrode, the effective facing area of the sub-pixel P actual light emitting unit to the touch electrode is maximized, and the touch effect is optimized; meanwhile, the shielding of the grid lines WD' on the light emitting layer pattern L2 of the light emitting device L of the sub-pixel P is reduced, thereby reducing the shielding of the effective light emitting area of the sub-pixel P and improving the light extraction efficiency.

In an exemplary embodiment, as shown in fig. 32, when the touch function layer 30 is fabricated on the display substrate 10, an orthographic projection of the grid lines WD' of the metal grid structure WD of the touch electrode on the display substrate 10 overlaps with at least one first signal line (e.g., the first initialization signal line Vini1 shown in fig. 32). That is, the sub-pixel P is defined in the metal mesh WD by designing the relative position of the grid line WD 'and the first signal line connected to the sub-pixel P, so that the effective light-emitting area of the sub-pixel P can be prevented from being blocked by the grid line WD'.

In an exemplary embodiment, an orthographic projection of the grid lines WD 'of the metal grid structure on the display substrate 10 at least partially overlaps with the at least one second signal line, so that the effective light-emitting area of the sub-pixel P is prevented from being blocked by the grid lines WD'.

In an exemplary embodiment, an orthographic projection of the mesh lines WD' of the metal mesh structure on the display substrate 10 overlaps at least a portion of at least one thin film transistor TFT of the pixel circuit 11. For example, as shown in fig. 32, the orthographic projection of the grid line WD 'overlaps the sixth transistor T6 and the seventh transistor T7, so that the effective light-emitting area of the sub-pixel P is prevented from being blocked by the grid line WD'.

In an exemplary embodiment, an orthographic projection of the mesh lines WD' of the metal mesh structure on the display substrate 10 at least partially overlaps the anode L1 of the light emitting device L. For example, the orthographic projection of the grid lines WD 'overlaps with the portion of the anode electrode L1 of the light emitting device L outside the opening K of the pixel defining layer PDL, so that the effective light emitting area of the sub-pixel P is prevented from being blocked by the grid lines WD'.

In an exemplary embodiment, an orthogonal projection of the mesh lines WD' of the metal mesh structure on the display substrate 10 overlaps at least portions of the anode extension M8, the seventh connection pattern M7, and the second connection pattern M2 electrically connected to the light emitting device L and the corresponding pixel circuit 11. This can prevent the grid lines WD' from obstructing the effective light-emitting areas of the sub-pixels P.

In an exemplary embodiment, the pixel circuit 11 includes at least one Oxide thin film transistor (e.g., the first transistor T1) including an Oxide active layer pattern (e.g., a pattern of the second semiconductor layer Oxide); the orthographic projection of the gaps Wh (see fig. 30) between the metal mesh structures of the adjacent first touch electrode Tx and second touch electrode Rx on the display substrate 10 is staggered from the oxide active layer pattern. That is, the upper side of the Oxide active layer pattern is always shielded by the metal mesh structure, so that the Oxide active layer pattern is prevented from being influenced by the light transmitted through the gap Wh between the metal mesh structures, and the service life of the second semiconductor layer Oxide is prolonged.

In some embodiments, as shown in fig. 31, the touch electrode adopts a metal mesh structure, and each metal mesh WD in the metal mesh structure corresponds to one sub-pixel P, and an orthogonal projection of the metal mesh WD on the display substrate 10 overlaps the corresponding sub-pixel P. On this basis, when the pixel resolution is changed (increased or decreased), the distance between adjacent sub-pixels P is also changed, and the distance between adjacent signal lines (including adjacent first signal lines and adjacent second signal lines) is also changed, at this time, if the touch resolution is kept unchanged, that is, the size of the touch electrode of the touch functional layer 30 is kept unchanged, that is, the size of the metal mesh WD of the touch electrode is kept unchanged, the sub-pixel P with the changed position cannot be kept corresponding to the metal mesh WD with the unchanged position, the effective facing area of the touch electrode and the sub-pixel P is reduced, the touch effect is poor, and the probability that the grid line WD' shields the effective light emitting area of the sub-pixel P is increased, which affects the display effect.

In order to solve the above problem, in some embodiments, the touch electrode adopts a metal mesh structure, and at least one metal mesh WD in the metal mesh structure corresponds to one or more sub-pixels P, and an orthogonal projection of the metal mesh WD on the display substrate 10 at least partially overlaps the corresponding one or more sub-pixels P. Based on this, p₁=a₁×p₀₁, m₁=b₁×m₀₁；a₁And b₁Is positively correlated, and a₁＞b₁. By positively correlating the scaling coefficients of the pixel resolution and the touch resolution in the second direction Y, the touch resolution in the second direction Y is changed along with the change of the pixel resolution, so that the sub-pixel P in the second direction Y still corresponds to the metal grid of the touch electrode after the pixel resolution is changed, and the touch effect is ensured.

Based on this, a₁-b₁Not less than 0.1. Alternatively, 0.12 ≦ a₁-b₁Not more than 0.19, or, 0.20 not more than a₁-b₁Less than or equal to 0.25, alternatively, a₁-b₁Not less than 0.26; for example, a₁-b₁0.12, 0.135, 0.15, 0.16, 0.17, 0.175, 0.19,0.20, 0.22, 0.245, 0.25 or 0.26.

In some other embodiments, at least one metal mesh WD in the metal mesh structure corresponds to one or more sub-pixels P, and an orthographic projection of the metal mesh WD on the display substrate 10 at least partially overlaps the corresponding one or more sub-pixels P. Based on this, p₂=a₂×p₀₂, m=b₂×m₀₂；a₂And b₂Is positively correlated, and a₂＞b₂. By positively correlating the scaling coefficients of the pixel resolution and the touch resolution in the first direction X, the touch resolution in the first direction X changes along with the change of the pixel resolution, so that after the pixel resolution changes, the sub-pixel P in the first direction X still corresponds to the metal grid WD of the touch electrode, and the touch effect is ensured.

Based on this, a₂-b₂Not less than 0.1. Alternatively, 0.12 ≦ a₂-b₂Not more than 0.19, or, 0.20 not more than a₂-b₂Less than or equal to 0.25, alternatively, a₂-b₂Not less than 0.26; for example, a₂-b₂0.12, 0.135, 0.15, 0.16, 0.17, 0.175, 0.19, 0.20, 0.22, 0.245, 0.25 or 0.26.

In some other embodiments, at least one metal mesh WD in the metal mesh structure corresponds to one or more sub-pixels P, and an orthographic projection of the metal mesh WD on the display substrate 10 at least partially overlaps the corresponding one or more sub-pixels P. Based on this, p = a × p₀, m=b×m₀Wherein p is₁=p₂，m₁=m₂，p₀₁= p₀₂，m₀₁=m₀₂，a₁=a₂，b₁=b₂。

Based on this, if a₁=a₂=a，b₁=b₂And if b is not less than 0.1, a-b is not less than 0.1. Optionally, a-b is more than or equal to 0.12 and less than or equal to 0.19, or a-b is more than or equal to 0.20 and less than or equal to 0.25, or a-b is more than or equal to 0.26; for example, a-b is 0.12, 0.135, 0.15, 0.16, 0.17, 0.175, 0.19, 0.20, 0.22, 0.245, 0.25, or 0.26.

For example, when the pixel resolution is increased to 1.16 times of the initial pixel resolution, the zoom range of the touch resolution is controlled to be between 0.9 and 1.01 times of the initial touch resolution. Within this range, the touch accuracy, the finger distance, and the response time of the display panel 200 are excellent. The difference value of the pixel resolution and the scaling degree of the touch resolution is controlled within a fixed range, so that the sub-pixel P still corresponds to the metal grid WD of the touch electrode after the pixel resolution is changed, and the touch effect is ensured.

In the display panel 200, since the pixel density is high, the area of the touch electrode corresponding to the sub-pixel P position is reduced, and the touch capacitance is increased. This causes a decrease in the capacitance change rate before and after the touch, which causes a decrease in touch sensitivity, when the same capacitance value changes due to the finger touch.

To solve the above problem, some embodiments of the present disclosure provide a touch function layer 30, as shown in fig. 33, a first dummy electrode I is disposed in a gap Wh between adjacent first touch electrodes Tx and second touch electrodes Rx, and the first dummy electrode I is electrically insulated from both the first touch electrodes Tx and the second touch electrodes Rx. Because the first virtual electrode I is in a floating state, the touch capacitance of the touch electrode can be reduced, the change rate of the touch capacitance is improved, and the touch sensitivity is optimized.

In an exemplary embodiment, as shown in fig. 33 and 34, the first dummy electrode I includes a first main body portion I1 having a bar shape, and a plurality of first protrusions I2, the plurality of first protrusions I2 being disposed around the first main body portion I1 and connected to the first main body portion I1.

Illustratively, as shown in fig. 34, the ratio of the dimension of the first protrusion I2 in the direction perpendicular to the direction in which the length of the first main body portion I1 extends, to the length of the first main body portion I1 is less than or equal to 0.1. That is, the ratio of Wd1 to Ld1 is less than or equal to 0.1. Alternatively, the ratio of Wd1 to Ld1 is 0.01, 0.025, 0.05 or 0.1.

In an exemplary embodiment, the edge of the first dummy electrode I has an irregular polygonal line shape.

In an exemplary embodiment, the first dummy electrode I adopts a metal mesh structure.

In some embodiments, in the case that the display panel 200 is rectangular, due to the difference between the lengths of the long side and the short side, the touch electrode area of the touch unit extending along the long side direction is larger than that of the touch unit extending along the short side direction, which affects the mutual capacitance value generated between the touch unit extending along the long side direction and the touch unit extending along the short side direction, and further affects the accuracy of touch position sensing.

In order to solve the above problem, in some embodiments, a second dummy electrode disconnected from the touch electrode is disposed in the touch electrode of the touch unit extending in the long side direction, and the second dummy electrode is not electrically connected to the touch electrode and therefore does not transmit the touch signal, so that the area of the electrode for transmitting the signal in the touch unit extending in the long side direction is reduced, and thus the difference between the area of the electrode for transmitting the signal in the touch unit extending in the long side direction and the area of the electrode for transmitting the signal in the touch unit extending in the short side direction is reduced and may even be equal or approximately equal. Therefore, the problem that mutual capacitance values among different touch units are influenced due to the fact that the areas of electrodes used for transmitting signals in the touch units in different extending directions are different can be solved, and the touch position sensing precision is improved.

In an exemplary embodiment, as shown in fig. 35, in the case where the display panel 200 is rectangular, the first direction X (i.e., a row direction) is a short side direction, and the second direction Y (i.e., a column direction) is a long side direction, the second dummy electrodes J disconnected from the metal mesh WD for transmitting signals are disposed in the second touch electrodes Rx extending in the second direction Y. The second dummy electrode J may also adopt a metal mesh structure, for example, to ensure display uniformity of the display device 100 to which the display panel 200 is applied.

In an exemplary embodiment, as shown in fig. 36, in the case where the display panel is rectangular, the first direction X (i.e., a row direction) is a long side direction, and the second direction Y (i.e., a column direction) is a short side direction, the second dummy electrode J disconnected from the metal mesh WD for transmitting signals is disposed in the first touch electrode Tx extending in the first direction X.

Illustratively, as shown in fig. 37 and 38, the second dummy electrode J includes a polygonal second body portion J1, and a plurality of second protrusions J2, the plurality of second protrusions J2 being disposed around the second body portion J1 and connected to the second body portion J1. Illustratively, the second body portion J1 is rectangular or square.

Alternatively, as shown in fig. 37 and 38, the ratio of the dimension of the second projection J2 in the direction perpendicular to the direction in which the length of the second main body portion J1 extends to the length of the side of the second main body portion J1 connecting the second projection J2 is less than or equal to 0.1. That is, the ratio of Wd2 to Ld2 is less than or equal to 0.1. Alternatively, the ratio of Wd2 to Ld2 is 0.01, 0.025, 0.05 or 0.1.

Illustratively, the edge of the second dummy electrode J has a zigzag shape (as shown in fig. 37). For example, in a zigzag shape (as shown in fig. 38).

In some embodiments, as shown in fig. 39, a second dummy electrode J is disposed in at least one of the adjacent first and second touch electrodes Tx and Rx (i.e., a second dummy electrode J is disposed in the first selected touch electrode), a first dummy electrode I is disposed in a gap Wh between the adjacent first and second touch electrodes Tx and Rx, the first and second dummy electrodes I and J are connected by a third connection portion Br3, and the third connection portion Br3 is electrically insulated from the touch electrodes. In this way, the whole formed by electrically connecting the first dummy electrode I, the second dummy electrode J, and the third connection portion Br3 is in a floating state, thereby further optimizing the touch sensitivity.

In an alternative embodiment, the third connection portion Br3 is integrally formed with the first and second dummy electrodes I and J.

In an alternative embodiment, the first dummy electrode I, the second dummy electrode J and the touch electrode (i.e., TX and RX) are disposed on the same layer, for example, the first dummy electrode I, the second dummy electrode J and the touch electrode are on the touch electrode layer 2A (as shown in fig. 26).

In alternative embodiments, the first and second virtual electrodes I and J are layered with the touch electrodes (i.e., TX and RX), for example, the touch electrodes are on the touch electrode layer 2A (as shown in fig. 26), the first and second virtual electrodes I and J are on the bridge layer 2C (as shown in fig. 26), or one of the first and second virtual electrodes I and J is on the touch electrode layer 2A.

In an optional embodiment, the first dummy electrode I and the second dummy electrode J are connected by a third connecting portion Br3 in a bridging manner, and optionally, the third connecting portion Br3 is located in the touch electrode layer 2A or the bridging layer 2C.

In an alternative embodiment, the third connection portion Br3 may be located on a layer of the touch electrode close to the display substrate 10; or the third connection portion Br3 is located on a layer of the touch electrode away from the display substrate 10.

In some embodiments, as shown in fig. 40 and 41, at least one of the plurality of first touch electrodes Tx and the plurality of second touch electrodes Rx includes a rectangular third main body portion O, and at least one finger-shaped auxiliary electrode O'; the auxiliary electrode O' is disposed on at least one side of the third body portion O and electrically connected to the third body portion O.

In some embodiments, as shown in fig. 40, a plurality of sides of the third body portion O of the touch electrode are provided with the auxiliary electrodes O ', for example, two sides are provided with the auxiliary electrodes O'.

In some embodiments, as shown in fig. 41, two opposite auxiliary electrodes O 'are disposed between two adjacent first touch electrodes Tx, and the two opposite auxiliary electrodes O' respectively belong to the two adjacent first touch electrodes Tx; the two opposite auxiliary electrodes O' are electrically connected to each other by a first connection Br 1.

In an exemplary embodiment, two opposite auxiliary electrodes O 'are disposed between two adjacent second touch electrodes Rx, and the two opposite auxiliary electrodes O' respectively belong to the two adjacent second touch electrodes Rx; the two opposite auxiliary electrodes O' are electrically connected to each other by a second connecting portion Br 2.

In an exemplary embodiment, the auxiliary electrode O' extends toward the gap Wh between two adjacent touch electrodes, thereby increasing the area of the touch electrodes and optimizing the touch effect.

In an exemplary embodiment, the length Lp of the auxiliary electrode O' is equal to the length in the second direction Y (i.e., the column direction)) A distance m between centers of two upper adjacent first connection parts Br1₁The ratio of (A) to (B) is 0.2 to 0.4, for example, 0.2, 0.3, 0.4.

In the exemplary embodiment, the length Lp of the auxiliary electrode O' is the distance m from the center of two second connecting portions Br2 adjacent in the first direction X (i.e., the row direction)₂The ratio of (A) to (B) is 0.2 to 0.4, for example, 0.2, 0.3, 0.4.

In an exemplary embodiment, the width Lq of the auxiliary electrode O' is a distance m from the centers of two adjacent first connection parts Br1 or two adjacent second connection parts Br2 in the second direction Y₁The ratio of (A) to (B) is 0.1 to 0.3, for example, 0.1, 0.2, 0.3.

In an exemplary embodiment, the width Lq of the auxiliary electrode O' is a distance m from the centers of two first connection parts Br1 adjacent in the first direction X or two second connection parts Br2 adjacent in the first direction X₁The ratio of (A) to (B) is 0.1 to 0.3, for example, 0.1, 0.2, 0.3.

In an exemplary embodiment, the angle θ between the length extension direction of the auxiliary electrode O' and the edge of the third body portion O connected thereto is 60 ° -120 °, for example, 60 °, 70 °, 85 °, 90 °, 117 °, or 120 °.

In an alternative embodiment, a plurality of auxiliary electrodes O ' are disposed in a gap Wh between adjacent first touch electrodes Tx and second touch electrodes Rx, the plurality of auxiliary electrodes O ' respectively belong to the adjacent first touch electrodes Tx and second touch electrodes Rx, and the plurality of auxiliary electrodes O ' are disposed in a staggered manner. Therefore, the area of the touch electrode can be further increased, and the touch effect is optimized.

In order to effectively utilize the screen space and increase the screen occupation ratio (i.e., the ratio of the Area of the display Area actually used for displaying an image to the Area of the entire front surface of the display panel 200), a functional device such as a camera is placed in the OLED display panel by a punching technique, which is called an AA Hole (Active Area Hole) technique.

In some embodiments, as shown in fig. 42, an opening hole is provided in the display panel 200, the opening hole corresponding to a mounting hole in the display panel 200 for providing a functional device such as a camera. The open hole penetrates at least the touch functional layer 30, and optionally, also penetrates the array substrate, the light emitting layer pattern L2, the cathode layer L3, and the encapsulation layer 20.

It should be noted that fig. 42 only illustrates that one hole is provided in the display panel 200, however, the number of holes provided in the display panel 200 in the embodiment of the present disclosure may be two, three, or more than three, which may be provided as the case may be.

The position, size and shape of the opening hole shown in fig. 42 are only for illustration, and it should be understood by those skilled in the art that the position, size and shape of the opening hole in the embodiment of the present disclosure are not limited thereto, and may be adjusted accordingly according to the position, size and shape of the functional device such as a camera.

The arrangement of the openings inevitably occupies some area of the touch electrodes.

In an alternative embodiment, the aperture dh of the open hole is smaller than the distance m between the centers of two adjacent first connecting portions Br1 or two adjacent second connecting portions Br2 in the second direction Y₁Therefore, the occupied area of the opening to the touch electrode can be reduced as much as possible.

In an alternative embodiment, the aperture dh of the open hole is smaller than the distance m between the centers of two adjacent first connecting portions Br1 or two adjacent second connecting portions Br2 in the first direction X₂Therefore, the occupied area of the opening to the touch electrode can be reduced as much as possible.

In some embodiments, fig. 43 illustrates a partially enlarged structure of the touch function layer 30 in fig. 42 provided with the open holes, which occupy at least a portion of each of the two first touch electrodes Tx and the two second touch electrodes Rx as illustrated in fig. 43.

In an optional embodiment, the two first touch electrodes Tx and the two second touch electrodes Rx provided with the opening hole are second selected touch electrodes, and the area occupied by the opening hole of each second selected touch electrode is less than 0.5 of the area of a complete touch electrode, so as to reduce the influence of the opening hole on the area of the touch electrodes around the hole as much as possible and ensure the touch effect around the hole.

In some embodiments, as shown in fig. 44, the touch functional layer 30 further includes: and the first electrode ring T is arranged along the circumferential direction of the opening hole, and comprises a plurality of first electrode arcs T 'arranged at intervals, and at least one touch electrode occupied by the opening hole (namely, a second selected touch electrode) is electrically connected with one first electrode arc T'. After at least the first electrode arc T' of the first electrode ring T is electrically connected with the second selected touch electrode, capacitance compensation can be performed on the second selected touch electrode, so that the capacitance difference in the first direction and the second direction is further balanced, and the touch effect is enhanced.

Illustratively, in the case where the opening hole occupies two first touch electrodes Tx and two second touch electrodes Rx, for the adjacent first touch electrodes Tx and second touch electrodes Rx, a portion of the first electrode arc T' is located at a side of the first touch electrode Tx near the center of the opening hole, and another portion is located at a side of the second touch electrode Rx near the center of the opening hole. That is, the off positions of two adjacent first electrode arcs T' are staggered from the gap between the adjacent first touch electrode Tx and the adjacent second touch electrode Rx.

Illustratively, the first electrode ring T includes four first electrode arcs T'. The two first touch electrodes Tx or the two second touch electrodes Rx occupied by the openings hole are electrically connected to the two first electrode arcs T 'in a one-to-one correspondence, and the other two first electrode arcs T' are floating. The touch control effect is enhanced by electrically connecting the first electrode arc T' to the touch control electrode needing enhancing the touch control capacitance to compensate the touch control capacitance, so that the difference value between the touch control capacitance T and the touch control capacitance T of other touch control electrodes is reduced.

For example, the two first touch electrodes Tx occupied by the holes are electrically connected to the two first electrode arcs T' in a one-to-one correspondence. The touch capacitance of the two first touch electrodes Tx is compensated, so that the capacitance difference between the touch capacitance of the two first touch electrodes Tx and the touch capacitance of the second touch electrode Rx is reduced, and the touch effect is enhanced.

For example, as shown in fig. 44, the two second touch electrodes Rx occupied by the openings hole are electrically connected to the two first electrode arcs T' in a one-to-one correspondence manner. The touch capacitance of the two second touch electrodes Rx is compensated, so that the capacitance difference between the touch capacitance of the two second touch electrodes Rx and the touch capacitance of the first touch electrode Tx is reduced, and the touch effect is enhanced.

Illustratively, as shown in fig. 45, the first electrode ring T includes four first electrode arcs T'. The two first touch electrodes Tx and the two second touch electrodes Rx occupied by the opening hole are electrically connected to the four first electrode arcs T' in a one-to-one correspondence. For example, one first electrode arc T' is connected to each of the two first touch electrodes Tx and the two second touch electrodes Rx occupied by the opening hole. The touch capacitance of the two first touch electrodes Tx and the two second touch electrodes Rx is compensated, the overall touch capacitance of the touch electrodes is enhanced, and the touch effect is optimized.

In some embodiments, as shown in fig. 44 or 45, the touch functional layer 30 further includes: and the second electrode ring U is arranged along the circumferential direction of the opening hole. The second electrode ring U is located inside the first electrode ring T with a gap therebetween. The second electrode ring U is arranged along the circumferential direction of the opening hole, so that the hole circumference of the opening hole can be effectively shielded, and the light emitting effect of light rays on the display substrate 10 is reduced.

For example, the second electrode ring U and the first electrode ring T belong to different conductive film layers, for example, the second electrode ring U is located on the bridging layer 2C, and the first electrode ring T is located on the touch electrode layer 2A; or the second electrode ring U is located on the touch electrode layer 2A, and the first electrode ring T is located on the bridge layer 2C.

Illustratively, the second electrode ring U and the first electrode ring T belong to the same conductive film layer, for example, both the second electrode ring U and the first electrode ring T are located at the bridging layer 2C; or, the second electrode ring U and the first electrode ring T are both located on the touch electrode layer 2A.

For example, the second electrode ring U is not connected to other components, for example, the touch electrode or the first electrode ring T.

Illustratively, as shown in fig. 44 or 45, the second electrode ring U includes a plurality of second electrode arcs U ', optionally, two second electrode arcs U', electrically insulated from each other.

In some implementationsIn one example, as shown in FIG. 44 or FIG. 45, the first electrode ring T has a width W₁The width of the second electrode ring U is W₂，W₁/W₂The value of (A) is 0.4 to 0.6. For example, W₁/W₂Is 0.4, 0.45, 0.56, 0.5 or 0.6.

In some embodiments, as shown in fig. 44 or 45, two first touch electrodes Tx and two second touch electrodes Rx occupied by the opening hole are the second selected touch electrodes, the ratio of the area of the opening hole to the area of the second selected touch electrodes is R, and the width of the second electrode loop U is W₂，W₂=K₁×R+K₂(ii) a Wherein, K₁And K₂Is a preset threshold value, K is more than or equal to 240₁≤280，-80≤K₂Less than or equal to-40. Alternatively, K₁Is 240, 250, 256, 270.5, 275 or 280, K₂Is-80, -75, -65.6, -55, -50 or-40. When the touch resolution is scaled (increased or decreased), the size of the touch electrode is scaled accordingly, and the size of the opening hole is not changed, accordingly, the area of the touch electrode occupied by the opening hole is relatively increased or decreased, thereby resulting in the width W of the second electrode ring U₂It is necessary to increase or decrease, and therefore, the ratio of the open hole on the touch electrode to the width W of the second electrode ring U₂The relationship between, i.e. W₂=K₁×R+K₂When the touch resolution ratio is changed, the relative size of the second electrode ring U and the opening hole can be effectively controlled, and the adaptation degree of the second electrode ring U, the opening hole and the touch electrode is guaranteed.

In some embodiments, as shown in fig. 44 or 45, the two first touch electrodes Tx and the two second touch electrodes Rx occupied by the opening hole are the second selected touch electrodes, the ratio of the area of the opening hole to the area of the second selected touch electrodes is R, the distance between the first electrode ring T and the second electrode ring U is D, and D = K₃×R+K₄(ii) a Wherein, K₃And K₄Is a preset threshold value, K is more than or equal to-1500₃≤-100，50≤K₄Is less than or equal to 100. Alternatively, K₃Is-1500, -1400, -1000, -900, -750, -300 or-100, K₄50, 65.6, 70, 80, 95 or 100. When touching the scoreAfter the resolution is scaled (increased or decreased), the size of the touch electrode is scaled accordingly, and the size of the opening hole is not changed, accordingly, the area of the touch electrode occupied by the opening hole is relatively increased or decreased, and the distance D between the first electrode ring T and the second electrode ring U needs to be changed adaptively, so that the ratio of the opening hole on the touch electrode is related to the distance D, i.e. D = K₃×R+K₄When the touch resolution is changed, the relative size of the distance D between the first electrode ring T and the second electrode ring U can be effectively controlled, and the distance D between the first electrode ring T and the second electrode ring U, the first electrode ring T and the second electrode ring U and the adaptability of the touch electrode are ensured.

As shown in fig. 1, an embodiment of the present disclosure provides a display device 100 including the display panel 200.

Among other things, display device 100 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or textual. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of images for a piece of jewelry), and so forth.

The advantages of the display device 100 are the same as those of the display panel 200 in the above embodiments, and are not described herein again.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising:

the display substrate comprises a plurality of pixel circuits arranged in an array manner, and a plurality of first signal lines extending along a first direction, wherein the plurality of first signal lines are arranged in parallel along a second direction; the plurality of first signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of first signal lines; in two adjacent groups of first signal lines, the distance between two first signal lines corresponding to the positions in the second direction is p₁(ii) a The first direction is a row direction in which the plurality of pixel circuits are arranged in an array manner, and the second direction is a column direction in which the plurality of pixel circuits are arranged in an array manner;

the touch control functional layer is arranged on the display substrate and comprises a plurality of first touch control units extending along a first direction and a plurality of second touch control units extending along a second direction, the plurality of first touch control units are arranged in parallel along the second direction, the plurality of second touch control units are arranged in parallel along the first direction, and the plurality of first touch control units and the plurality of second touch control units are electrically insulated; each first touch unit comprises a plurality of first touch electrodes and a plurality of first connecting parts, and every two adjacent first touch electrodes are electrically connected through the first connecting parts; each second touch unit comprises a plurality of second touch electrodes and a plurality of second connecting parts, and every two adjacent second touch electrodes are electrically connected through the second connecting parts; the distance between the centers of two adjacent first connecting parts in the second direction and the distance between the centers of two adjacent second connecting parts in the second direction are both m₁；

Wherein p is₁=a₁×p₀₁, m₁=b₁×m₀₁；p₀₁A preset reference value for the distance between two first signal lines in the second direction corresponding to the positions of two adjacent first signal lines, a₁To showScaling factor, m, of target pixel resolution of the display panel relative to the reference pixel resolution in a second direction₀₁A preset reference value of the distance between the centers of two adjacent first connecting parts or two adjacent second connecting parts in the second direction, b₁A scaling factor of the target touch resolution of the display panel relative to the reference touch resolution in a second direction is obtained; a is₁And b₁Is positively correlated, and a₁＞b₁。

2. The display panel according to claim 1,

the display substrate further comprises a plurality of second signal lines extending along a second direction, and the plurality of second signal lines are arranged in parallel along the first direction; the plurality of second signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of second signal lines; in two adjacent groups of second signal lines, the distance between two second signal lines corresponding to the positions in the first direction is p₂；

The distance between the centers of two adjacent first connecting parts in the first direction and the distance between the centers of two adjacent second connecting parts in the first direction are both m₂；

3. The display panel according to claim 2, wherein p is₁=p₂，m₁=m₂，p₀₁= p₀₂，m₀₁=m₀₂，a₁=a₂，b₁=b₂。

4. The display panel of claim 3, wherein a-b is 0.1; wherein, a₁=a₂=a，b₁=b₂=b。

5. The display panel of claim 4, wherein the display panel is substantially rectangular;

wherein a-b is more than or equal to 0.20 and less than or equal to 0.25.

6. The display panel of claim 4, wherein the display panel is substantially rectangular;

the length d of the diagonal line of the display panel is less than or equal to 16.51cm, and a-b is more than or equal to 0.12 and less than or equal to 0.19.

7. The display panel of claim 4, wherein the display panel is substantially rectangular;

the length d of the diagonal line of the display panel is larger than 16.51cm, and a-b is larger than or equal to 0.26.

8. The display panel of claim 3, wherein 30 μm ≦ p₀≤50μm，3500μm≤m₀Less than or equal to 4500 μm; wherein p is₀₁= p₀₂=p₀，m₀₁=m₀₂=m₀。

9. The display panel according to claim 7, wherein p is₀=40μm，m₀=4000μm。

10. The display panel according to claim 1, wherein each set of the first signal lines includes an enable signal line, at least one scan signal line, and at least one initialization signal line;

in the adjacent two groups of the first signal lines,

the distance between the two enable signal lines in the second direction is p₁(ii) a And/or the presence of a gas in the gas,

the distance between two corresponding scanning signal lines in the second direction is p₁(ii) a And/or the presence of a gas in the gas,

the distance between the two initialization signal lines with corresponding positions in the second direction is p₁。

11. The display panel according to claim 1, wherein the display substrate further comprises a plurality of second signal lines extending in a second direction, the plurality of second signal lines being juxtaposed in the first direction; the plurality of second signal lines are divided into a plurality of groups, and each row of pixel circuits is electrically connected with one group of second signal lines;

each group of second signal lines comprises a data line and a power line;

in the adjacent two groups of the second signal lines,

the distance between the two data lines in the first direction is p₂(ii) a And/or the presence of a gas in the gas,

the distance between the two power lines in the first direction is p₂。

12. The display panel according to claim 1, wherein the first touch unit and/or the second touch unit comprises a metal mesh structure;

the display substrate comprises a plurality of sub-pixels, each sub-pixel comprises a light emitting device and a pixel circuit electrically connected with the light emitting device;

at least one grid of the metal grid structure corresponds to one or more sub-pixels, and an orthographic projection of the grid on the display substrate at least partially overlaps the corresponding one or more sub-pixels.

13. The display panel according to claim 12,

the light emitting layer patterns of the light emitting devices of the one or more sub-pixels are positioned within the orthographic projection range of the corresponding grids on the display substrate; and/or the presence of a gas in the gas,

the boundary of the pixel defining layer opening where the light emitting layer pattern of the light emitting device of the one or more sub-pixels is located is positioned in the orthographic projection range of the corresponding grid on the display substrate; and/or the presence of a gas in the gas,

the pixel circuits of the one or more sub-pixels are located within a forward projection range of the corresponding grid on the display substrate.

14. The display panel of claim 12, wherein an orthographic projection of the grid lines of the metal grid structure on the display substrate at least partially overlaps with at least one first signal line; and/or the presence of a gas in the gas,

the display substrate further comprises a plurality of second signal lines extending along a second direction, and orthographic projections of the grid lines of the metal grid structure on the display substrate are at least partially overlapped with at least one second signal line; and/or the presence of a gas in the gas,

an orthographic projection of grid lines of the metal grid structure on the display substrate at least partially overlaps with at least one transistor of the pixel circuit; and/or the presence of a gas in the gas,

an orthographic projection of grid lines of the metal grid structure on the display substrate at least partially overlaps with an anode of the light-emitting device; and/or the presence of a gas in the gas,

an orthographic projection of the grid lines of the metal grid structure on the display substrate overlaps at least a portion of a connection pattern electrically connecting the light emitting device and the corresponding pixel circuit.

15. The display panel according to claim 12, wherein the pixel circuit includes at least one oxide thin film transistor including an oxide active layer pattern;

the orthographic projection of a gap between the metal grid structures of the adjacent first touch electrode and the second touch electrode on the display substrate is staggered with the oxide active layer pattern.

16. The display panel according to claim 12, wherein the pixel circuit includes at least one low temperature polysilicon thin film transistor and at least one oxide thin film transistor, the low temperature polysilicon thin film transistor includes a low temperature polysilicon active layer pattern, and the oxide thin film transistor includes an oxide active layer pattern;

the oxide active layer pattern is farther from a substrate of the display substrate relative to the low temperature polysilicon active layer pattern in a thickness direction of the display substrate.

17. The display panel according to any one of claims 1 to 16, wherein the touch functional layer further comprises at least one first dummy electrode;

the first virtual electrode is arranged in a gap area between the adjacent first touch electrode and the second touch electrode, and is electrically insulated from the first touch electrode and the second touch electrode.

18. The display panel according to claim 17, wherein the first dummy electrode includes a first main body portion having a bar shape, and a plurality of first protrusions;

the plurality of first protrusions are arranged around the first main body part and connected with the first main body part.

19. The display panel according to claim 18, wherein a ratio of a dimension of the first protrusion in a direction perpendicular to a direction in which a length of the first main body portion extends to the length of the first main body portion is less than or equal to 0.1.

20. The display panel of claim 17, wherein the touch functional layer further comprises at least one second virtual electrode;

the second virtual electrode is arranged in the touch electrode of one of the first touch unit and the second touch unit with a longer length, and the second virtual electrode is electrically insulated from the touch electrode where the second virtual electrode is located.

21. The display panel according to claim 20, wherein the second dummy electrode comprises a polygonal second main body portion and a plurality of second protrusions;

the plurality of second protrusions are arranged around the second main body part and connected with the second main body part.

22. The display panel according to claim 21, wherein a ratio of a dimension of the second projection in a direction perpendicular to a side of the second main body portion to which the second projection is connected to a length of the side of the second main body portion to which the second projection is connected is less than or equal to 0.1.

23. The display panel of claim 20, wherein at least one of the first touch electrodes and the second touch electrodes is a first selected touch electrode, and a first dummy electrode is disposed on at least one side of the first selected touch electrode and a second dummy electrode is disposed inside the first selected touch electrode.

24. The display panel of claim 23, wherein the touch functional layer further comprises at least one third connecting portion, the first dummy electrode on one side of the first selected touch electrode and the second dummy electrode inside the first selected touch electrode are electrically connected to each other through the third connecting portion, and the third connecting portion is electrically insulated from the first selected touch electrode.

25. The display panel according to claim 24, wherein the touch functional layer comprises a touch electrode layer, an insulating layer and a bridge layer, which are stacked, and the bridge layer is located on a side of the touch electrode layer close to or far from the display substrate;

the first virtual electrode, the second virtual electrode and the first selected touch electrode are positioned on the touch electrode layer, and the third connecting part is positioned on the bridge layer; the third connecting portion is electrically connected with the first virtual electrode and the second virtual electrode through a via hole formed in the insulating layer.

26. The display panel according to any one of claims 1 to 16, wherein at least one of the plurality of first touch electrodes and the plurality of second touch electrodes comprises a rectangular third main body portion and at least one finger-shaped auxiliary electrode;

the auxiliary electrode is disposed on at least one side of the third main body portion and electrically connected to the third main body portion.

27. The display panel according to claim 26, wherein a length of the auxiliary electrode is equal to a distance m between centers of two first connecting portions adjacent in the second direction₁The ratio of (A) to (B) is 0.2-0.4; and/or;

a distance m between a length of the auxiliary electrode and centers of two second connection portions adjacent in the first direction₂The ratio of (A) to (B) is 0.2 to 0.4.

28. The display panel according to claim 26, wherein a width of the auxiliary electrode is a distance m from centers of two first connecting portions adjacent in the second direction₁The ratio of (A) to (B) is 0.1-0.3; and/or;

a distance m between a width of the auxiliary electrode and centers of two second connection portions adjacent in the first direction₁The ratio of (A) to (B) is 0.1 to 0.3.

29. The display panel according to claim 26, wherein an angle between a longitudinal extending direction of the auxiliary electrode and a side of the third main body portion connected thereto is 60 ° to 120 °.

30. The display panel according to claim 26, wherein a plurality of auxiliary electrodes are disposed in a gap area between the adjacent first touch electrode and the adjacent second touch electrode, the plurality of auxiliary electrodes belong to the adjacent first touch electrode and the adjacent second touch electrode respectively, and the plurality of auxiliary electrodes are disposed in a staggered manner.

31. The display panel according to claim 26, wherein two opposite auxiliary electrodes are disposed between two adjacent first touch electrodes, and the two opposite auxiliary electrodes respectively belong to the two adjacent first touch electrodes; the two opposite auxiliary electrodes are electrically connected through a first connecting part; and/or;

two opposite auxiliary electrodes are arranged between two adjacent second touch control electrodes, and the two opposite auxiliary electrodes respectively belong to the two adjacent second touch control electrodes; the two opposite auxiliary electrodes are electrically connected through the second connecting part.

32. The display panel according to any one of claims 1 to 16, wherein the display panel is provided with at least one opening, and the opening at least penetrates through the touch functional layer;

the aperture of the open hole is smaller than the distance m between the centers of two adjacent first connecting parts in the second direction₁(ii) a And/or the presence of a gas in the gas,

the aperture of the open hole is smaller than the distance m between the centers of two second connecting parts adjacent to each other in the first direction₂。

33. The display panel of claim 32, wherein the aperture occupies at least a portion of each of the two first touch electrodes and the two second touch electrodes;

the two first touch electrodes and the two second touch electrodes occupied by the openings are second selected touch electrodes, and the area occupied by each second selected touch electrode by the opening accounts for less than 0.5 of the area of one complete touch electrode.

34. The display panel of claim 32, wherein the two first touch electrodes and the two second touch electrodes occupied by the openings are second selected touch electrodes;

the touch control function layer further comprises a first electrode ring arranged along the circumferential direction of the opening, the first electrode ring comprises a plurality of first electrode arcs arranged at intervals, and at least one second selected touch control electrode is electrically connected with one first electrode arc.

35. The display panel of claim 34, wherein the touch functional layer further comprises a second electrode ring disposed along a circumferential direction of the opening, and the second electrode ring is located inside the first electrode ring with a gap from the first electrode ring.

36. The display panel of claim 35, wherein the first electrode ring has a width W₁The width of the second electrode ring is W₂，W₁/W₂The value of (A) is 0.4 to 0.6.

37. The display panel of claim 35, wherein the ratio of the area of the opening to the area of the second selected touch electrode is R, and the width of the second electrode ring is W₂，W₂=K₁×R+K₂；

Wherein, K₁And K₂Is a preset threshold value, K is more than or equal to 240₁≤280，-80≤K₂≤-40。

38. The display panel of claim 35, wherein a ratio of an area of the opening to an area of the second selected touch electrode is R, a distance between the first electrode ring and the second electrode ring is D, and D = K₃×R+K₄；

Wherein, K₃And K₄Is a preset threshold value, K is more than or equal to-1500₃≤-100，50≤K₄≤100。

39. The display panel according to claim 34, wherein the opening occupies two first touch electrodes and two second touch electrodes, and for the adjacent first touch electrode and second touch electrode, a part of the arc of the first electrode is located on a side of the first touch electrode close to a center of the opening, and another part of the arc of the first electrode is located on a side of the second touch electrode close to the center of the opening.

40. The display panel of claim 39, wherein the first electrode ring comprises four first electrode arcs;

the two first touch electrodes and the two second touch electrodes occupied by the openings are electrically connected with the four first electrode arcs in a one-to-one correspondence manner.

41. The display panel of claim 39, wherein the first electrode ring comprises four first electrode arcs;

the two first touch electrodes or the two second touch electrodes occupied by the openings are electrically connected with the two first electrode arcs in a one-to-one correspondence mode, and the other two first electrode arcs float.

42. A display device comprising the display panel according to any one of claims 1 to 41.