CN113725274A - Pixel circuit, display panel and display device - Google Patents

Pixel circuit, display panel and display device Download PDF

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Publication number
CN113725274A
CN113725274A CN202111032795.0A CN202111032795A CN113725274A CN 113725274 A CN113725274 A CN 113725274A CN 202111032795 A CN202111032795 A CN 202111032795A CN 113725274 A CN113725274 A CN 113725274A
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China
Prior art keywords
transistor
pole
pixel circuit
coupled
electrode
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CN202111032795.0A
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Chinese (zh)
Inventor
王灿
张陶然
周炟
王建波
鲁晏廷
吴董杰
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Priority to CN202111032795.0A priority Critical patent/CN113725274A/en
Publication of CN113725274A publication Critical patent/CN113725274A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

The embodiment of the disclosure provides a pixel circuit, a display panel and a display device, relates to the technical field of display, and is used for improving the bright spot problem of a display picture of the display panel on the premise of improving the residual image problem of the display picture of the display panel. The pixel circuit includes a light emitting device, a driving transistor, a first transistor, and a second transistor. The second pole of the driving transistor is coupled with the light emitting device, and the driving transistor is configured to control the magnitude of current flowing through the first pole and the second pole in response to the voltage of the control pole. The first pole of the first transistor is coupled to the control pole of the driving transistor, and the second pole is configured to write the first initialization signal. The first pole of the second transistor is coupled to the light emitting device, and the second pole is configured to write a second initialization signal. The first transistor comprises at least two sub-transistors connected in series, and the width-to-length ratio of a channel of at least one sub-transistor is smaller than that of a channel of the second transistor.

Description

Pixel circuit, display panel and display device
Technical Field
The invention relates to the technical field of display, in particular to a pixel circuit, a display panel and a display device.
Background
At present, Organic Light-Emitting Diode (OLED) Display devices are widely used because of their advantages of self-luminescence, fast response speed, low power consumption, and the like.
In the OLED display device, the OLED may be driven to emit light by a pixel driving circuit. The pixel driving circuit may include a plurality of Thin Film Transistors (TFTs). Due to the property of the thin film transistor, when the thin film transistor is in an off state, a leakage current may exist in the thin film transistor, which may cause a bright spot, an afterimage, etc. on a display screen of the display device, thereby deteriorating the appearance of the display screen.
Disclosure of Invention
Embodiments of the present invention provide a pixel circuit, a display panel and a display device, which are used for improving a bright spot problem of a display image of the display panel on the premise of improving a residual image problem of the display image of the display panel.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in a first aspect, a pixel circuit is provided that includes a light emitting device, a driving transistor, a first transistor, and a second transistor. Wherein the driving transistor includes a first electrode, a second electrode, and a control electrode, the second electrode is coupled to the light emitting device in the driving transistor, and the driving transistor is configured to control a magnitude of a current flowing through the first electrode and the second electrode in response to a voltage of the control electrode. The first transistor includes a first pole, a second pole, and a control pole, in the first transistor, the first pole is coupled to the control pole of the driving transistor, and the second pole is configured to write the first initialization signal. The second transistor includes a first pole, a second pole, and a control pole, in the second transistor, the first pole is coupled to the light emitting device, and the second pole is configured to write a second initialization signal. The first transistor comprises at least two sub-transistors connected in series, control electrodes of at least two golden kickers are mutually coupled to form the control electrode of the first transistor, and the width-to-length ratio of a channel of at least one sub-transistor is smaller than that of a channel of the second transistor.
In some embodiments, the width-to-length ratio of the channel of each of the at least two sub-transistors is the same.
In some embodiments, a width of a channel of each of the sub-transistors is equal to a width of a channel of the second transistor.
In some embodiments, the length of the channel of the at least one sub-transistor is 0.8 to 1.2 μm greater than the length of the channel of the second transistor.
In some embodiments, the channel of at least one of the sub-transistors has a width of 2.0 to 3.0 μm and a length of 2.7 to 4.0 μm.
In some embodiments, the channel of at least one of the sub-transistors has a width of 2.3 ± 0.2 μm and a length of 3.5 ± 0.2 μm.
In some embodiments, the width of the channel of the driving transistor is greater than the width of the channel of the second transistor.
In some embodiments, the width of the channel of the drive transistor is 3.0 ± 0.2 μm.
In some embodiments, the pixel circuit further includes at least one of a capacitor, a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor; wherein the capacitor includes a first plate coupled to the control electrode of the driving transistor and a second plate configured to write the power supply voltage signal; a third transistor including a first pole, a second pole, and a control pole, in the third transistor, the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write the data signal; a fourth transistor including a first electrode, a second electrode, and a control electrode, in which the first electrode is coupled to the second electrode of the driving transistor and the second electrode is coupled to the control electrode of the driving transistor; a fifth transistor including a first pole, a second pole, and a control pole, in the fifth transistor, the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write the power supply voltage signal; the sixth transistor includes a first electrode, a second electrode, and a control electrode, and in the sixth transistor, the first electrode is coupled to the second electrode of the driving transistor, and the second electrode is coupled to the light emitting device.
In a second aspect, a display panel is provided, which includes a plurality of pixel circuits, each of which is the pixel circuit provided in any one of the above embodiments.
In some embodiments, the plurality of pixel circuits includes a first pixel circuit located at the N-1 th row and a second pixel circuit located at the N-th row. The display panel further includes a reset control signal line. The first pixel circuit and the second pixel circuit are provided in any one of the above embodiments. The control electrode of the first transistor in the second pixel circuit and the control electrode of the second transistor in the first pixel circuit are both coupled with a reset control signal line. Wherein N is an integer greater than 1.
In some embodiments, in the first transistor of the second pixel circuit, the control electrodes of the respective sub-transistors are coupled to each other and form a body pattern, and the body pattern is coupled to the reset control signal line. The reset control signal line, the integral pattern, and the control electrode of the second transistor in the first pixel circuit are located in the same pattern layer, and the width of the integral pattern is larger than the width of the control electrode of the second transistor and larger than the width of the reset control signal line.
In some embodiments, the pixel circuit includes a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor. The display panel further includes a first light emission control signal line and a second light emission control signal line, a control electrode of the fifth transistor and a control electrode of the sixth transistor in the first pixel circuit are coupled to the first light emission control signal line, and a control electrode of the fifth transistor and a control electrode of the sixth transistor in the second pixel circuit are coupled to the second light emission control signal line. The display panel further includes a first scan signal line and a second scan signal line, a control electrode of the fourth transistor and a control electrode of the third transistor in the first pixel circuit are coupled to the first scan signal line, and a control electrode of the fourth transistor and a control electrode of the third transistor in the second pixel circuit are coupled to the second scan signal line. The first light-emitting control signal line, the second light-emitting control signal line, the first scanning signal line, the second scanning signal line and the integrated pattern are positioned in the same pattern layer.
In some embodiments, the pixel circuit includes a capacitor, a second plate of the capacitor being configured to write the supply voltage signal. The first plate and the integral pattern are positioned in the same pattern layer.
In a third aspect, a display device is provided, which includes the display panel provided in any of the above embodiments.
In a transistor, the smaller the aspect ratio of a channel, the worse the on performance of the transistor, and the smaller the leakage current of the transistor in an off state can be. In the pixel circuit provided by the embodiment of the disclosure, in the first transistor, the width-to-length ratio of the channel of at least one sub-transistor is smaller than the width-to-length ratio of the channel of the second transistor, so that compared with the second transistor, the on performance of the whole first transistor can be poorer, the leakage current of the first transistor in an off state can be smaller in the process of light emission of the light emitting device, and the problem of bright spots in a display screen can be improved. Further, since the width-to-length ratio of the channel of the at least one sub transistor is smaller than the width-to-length ratio of the channel of the second transistor, the width-to-length ratio of the channel of the second transistor may be larger. Therefore, the on performance of the second transistor can be better, so that the second transistor can initialize the light-emitting device better, and the problem that the display picture of the display panel has afterimage can be improved. That is, the pixel circuit provided by the embodiment of the present disclosure can improve the problem of the bright spot of the display screen of the display panel on the premise of improving the problem of the afterimage of the display screen of the display panel.
It can be understood that the display panel provided by the second aspect and the display device provided by the third aspect include the pixel circuit, and the advantageous effects achieved by the display panel can refer to the advantageous effects of the pixel circuit, which are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a top view of a display panel provided by some embodiments of the present disclosure;
FIG. 2 is a block diagram of a display panel provided in some embodiments of the present disclosure;
fig. 3 is an equivalent circuit diagram of a pixel circuit provided by some embodiments of the present disclosure;
fig. 4 is a block diagram of a light emitting device in a pixel circuit provided by some embodiments of the present disclosure;
fig. 5 is an equivalent circuit diagram of a pixel circuit provided by some embodiments of the present disclosure;
fig. 6 is a top view of a display panel provided by some embodiments of the present disclosure;
FIG. 7 is a top view of a patterned layer in a display panel according to some embodiments of the present disclosure;
FIG. 8 is a top view of a patterned layer in a display panel according to some embodiments of the present disclosure;
fig. 9 is a top view of a plurality of patterned layers in a display panel according to some embodiments of the present disclosure;
FIG. 10 is an enlarged view of a portion of area B of FIG. 9;
FIG. 11 is a block diagram of a display panel provided by some embodiments of the present disclosure;
fig. 12 is a top view of a display panel provided by some embodiments of the present disclosure;
fig. 13 is a top view of a plurality of pattern layers of a display panel according to some embodiments of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention.
Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.
In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.
In describing some embodiments, expressions of "coupled" and "connected," along with their derivatives, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.
"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.
"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.
"plurality" means at least two.
The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.
Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.
As used herein, "about," "approximately," or "approximately" includes the stated values as well as average values that are within an acceptable range of deviation for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system).
Example embodiments are described herein with reference to cross-sectional and/or plan views as idealized example figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.
The transistors herein may be N-type transistors or P-type transistors, and embodiments of the present disclosure are not particularly limited thereto. The transistors will be exemplified as P-type transistors hereinafter. It is understood that the transistor is an N-type transistor, which can also implement the solution of the present disclosure and obtain the corresponding technical effect.
Some embodiments of the present disclosure provide a display device. The display device is a product having an image (including a still image or a moving image, wherein the moving image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information inquiry apparatus (e.g., an inquiry apparatus for business in a department such as e-government, a bank, a hospital, electric power, etc.), a monitor, and the like.
In some embodiments, the display device may include a display panel, and may further include a driving circuit coupled to the display panel. The driving circuit is configured to supply an electric signal to the display panel. Illustratively, the driving circuit may include: a data driving circuit (which may be, for example, a Source Driver IC) configured to provide a data signal (also referred to as a data driving signal) to the display panel; and a scan driving circuit configured to supply a scan signal to the display panel. The driving circuit may further include a timing control circuit (also referred to as a timing controller, or "TimerControl Register", or "TCON" for short), which may be coupled to the data driving circuit and the scan driving circuit, configured to provide control signals to the scan driving circuit and to provide control signals and image data to the data driving circuit. In some possible implementations, the scan driving circuit may be integrated on the display panel. In this case, the display panel may include a scan driving circuit, and the scan driving circuit may be referred to as a Gate Driver on Array (GOA) circuit disposed on the Array substrate.
Some embodiments of the present disclosure also provide a display panel, which may be included in the display device provided in any of the above embodiments. The display panel may be one of an Organic Light Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, and a micro LED (including a miniLED or a micro LED, where the LED is a Light Emitting Diode) display panel.
Fig. 1 illustrates a structure of a display panel provided by some embodiments of the present disclosure. Referring to fig. 1, the display panel 1 may have a display area AA and a peripheral area SA located on at least one side (e.g., one side; e.g., four sides, including upper and lower sides and left and right sides) of the display area AA. The display panel 1 includes a plurality of pixel circuits 10 disposed in the display area AA. The pixel circuit 10 may include a light emitting device 100 and a pixel driving circuit 200 controlling the light emitting device 100 to emit light. Wherein the pixel driving circuit 200 may be configured to drive the light emitting device 100 to emit light in response to the received data signal and the scan signal, and the luminance of light emitted by the light emitting device 100 may be positively correlated with the voltage of the data signal. In the display area AA, the pixel driving circuits 200 may be distributed in an array.
In some embodiments, the display panel 1 may further include various signal lines. Illustratively, various signal lines may be located in the display area and coupled to the pixel circuits in the display area. Specifically, referring to fig. 2, fig. 2 is a partially enlarged view of the display panel in fig. 1. A pixel circuit 10 (e.g., each pixel circuit 10) may be coupled to a variety of signal lines, each of which may be configured to write an electrical signal to the pixel circuit 10.
In some embodiments, the plurality of signal lines may include at least one of a data line D, a first power line EL1, a second power line EL2, a reset control signal line R, a light emission control signal line E, and a scan signal line G. The various signal lines may also include an initialization signal line Vi (not shown in fig. 2). Wherein the data line D may be configured to write the data signal Da to the pixel circuit 10; the first power supply line EL1 may be configured to write the first power supply voltage signal ELVDD to the pixel circuit 10; the second power supply line EL2 may be configured to write the second power supply voltage signal ELVSS to the pixel circuit 10; the reset control signal line R may be configured to write a reset control signal Sc1 to the pixel circuit 10; the light emission control signal line E may be configured to write a light emission control signal Sc2 to the pixel circuit 10; the scanning signal line G may be configured to write a scanning signal Sc3 to the pixel circuit 10; the initialization signal line Vi may be configured to write an initialization signal Vinit (not shown in the figure) to the pixel circuit 10. The data signal Da, the first power voltage signal ELVDD, the second power voltage signal ELVSS, the reset control signal Sc1, the emission control signal Sc2, the scan signal Sc3, and the initialization signal Vinit may be voltage signals, or may be other types of electrical signals, which is not limited in this embodiment of the disclosure. Wherein a voltage of the first power supply voltage signal ELVDD may be greater than a voltage of the second power supply voltage signal ELVSS. In addition, in fig. 2, the subscript marks corresponding to the reference numerals of the signal lines are used to indicate the serial numbers of the signal lines. E.g. DMThe mth data line is shown.
Some embodiments of the present disclosure also provide a pixel circuit, which may be a pixel circuit in the display panel of any of the above embodiments.
Fig. 3 is an equivalent circuit diagram of the pixel circuit. Referring to fig. 3, based on the above description, the pixel circuit 10 may include the light emitting device 100 and a pixel driving circuit coupled to the light emitting device 100. The light emitting device 100 may be, for example, an organic light emitting diode OLED, a quantum dot light emitting diode QLED, or a light emitting diode LED, but is not limited thereto. The embodiment of the present disclosure does not limit the type of the light emitting device 100, that is, the light emitting device 100 may be any other light emitting device (e.g., a light emitting device that emits light by discharge) as long as they can emit light in response to an electrical signal so that the display panel can display a picture. In some embodiments, light emitting device 100 is an OLED.
In some embodiments, referring to fig. 4, the light emitting device 100 may be an OLED, and the light emitting device 100 may include a first electrode 110, a second electrode 130, and a light emitting function layer 120 between the first electrode 110 and the second electrode 130.
Illustratively, the first electrode 110 may be coupled with a pixel driving circuit, which may provide a voltage-variable electrical signal to the first electrode 110; the second electrode 130 may be coupled to a power line, which may supply a fixed voltage to the second electrode 130. Illustratively, the first electrode 110 is an anode and correspondingly, the second electrode 130 is a cathode; the first electrode 110 is configured to be coupled to a first power line (configured to transmit the first power signal ELVDD of fig. 3) through the pixel driving circuit, and the second electrode 130 is coupled to a second power line (configured to transmit the second power signal ELVSS of fig. 3). Also illustratively, the first electrode 110 is a cathode, and correspondingly, the second electrode 130 is an anode; the first electrode 110 is coupled to a second power line through a pixel driving circuit, and the second electrode 130 is coupled to the first power line.
The light emitting function layer 120 may have a single-layer structure or a multi-layer structure. Illustratively, the light emitting function layer 120 may include a light emitting layer, and the light emitting function layer may further include: at least one of a hole injection layer, a hole transport layer, and an electron blocking layer between the anode and the light emitting layer may further include: and at least one of a hole blocking layer, an electron transport layer, and an electron injection layer between the light emitting layer and the cathode. Among them, the light emitting layer in one light emitting device 100 may be a red light emitting layer, a green light emitting layer, a blue light emitting layer, or a white light emitting layer.
It should be noted that, the structure of other types of light emitting devices (e.g., QLED, or LED) may also refer to the structure of the OLED described above, and the detailed description of the structure of other types of light emitting devices is omitted.
With continued reference to fig. 3, the pixel driving circuit may include a plurality of transistors T. Specifically, the pixel driving circuit may include a driving transistor Td, a first transistor T1, and a second transistor T2.
The driving transistor Td includes a first electrode Td1, a second electrode Td2, and a control electrode Td 3. The driving transistor Td is configured to control the magnitude of current flowing through the first and second poles Td1 and Td2 in response to the voltage of the control pole Td 3. For example, in the driving transistor Td, the control electrode Td3 may be configured to write an electric signal, and the driving transistor Td may control the magnitude of the current flowing through the first and second electrodes Td1 and Td2 in response to the voltage of the electric signal, which is different in magnitude, and the magnitude of the current flowing through the first and second electrodes Td1 and Td2 is different. In some possible implementations, the electric signal written into the control electrode Td3 may be the data signal Da or the data association signal Da' (i.e. the electric signal related to the data signal Da), so that the voltage on the control electrode Td3 may be related to the voltage Vdata of the data signal Da written into the pixel driving circuit, for example, the voltage magnitude of the electric signal is positively related to the magnitude of the voltage Vdata of the data signal Da. Based on this, the magnitude of the current flowing through the first and second poles Td1 and Td2 may be controlled by supplying different data signals Da to the pixel driving circuit.
The second diode Td2 is coupled with the light emitting device 100. Illustratively, the second diode Td2 may be coupled with the first electrode of the light emitting device 100 such that the driving transistor Td and the light emitting device 100 are connected in series on a line between the first power line EL1 and the second power line EL 2. Since the driving transistor Td is connected in series with the light emitting device 100, a current flowing through the first and second electrodes Td1 and Td2 may flow into the light emitting device 100, and the light emitting device 100 may be driven to emit light by the current, and in particular, the light emission luminance of the light emitting device 100 may be controlled by the current. That is, in the pixel circuit 10, the magnitudes of the currents flowing through the first and second electrodes Td1 and Td2 of the driving transistor are different, and the light emission luminance of the light emitting device 100 can be varied accordingly.
In some embodiments, the first pole Td1 of the driving transistor may be coupled with the first power line EL1, so that the first pole Td1 of the driving transistor may write the first power voltage signal ELVDD. In some possible implementations, the second pole Td2 of the driving transistor is coupled to the first electrode of the light emitting device 100, and the second electrode of the light emitting device 100 is coupled to the second power line EL2, so that the first pole Td1 of the driving transistor may be coupled to the first power line EL1, and the second pole Td2 of the driving transistor may be coupled to the second power line EL2 through the light emitting device 100. A voltage difference may be provided between the first power voltage signal ELVDD on the first power line EL1 and the second power voltage signal ELVSS on the second power line EL2, so that a current flowing through the first and second poles Td1 and Td2 of the driving transistor and a current flowing through the light emitting device 100 may be generated.
The first transistor T1 includes a first pole T11, a second pole T12, and a control pole T13. In the first transistor T1, the first pole T11 is coupled to the control pole Td3 of the driving transistor, and the second pole T12 is configured to write the first initialization signal Vinit 1. In this way, when the first transistor T1 is in a turned-on state, the first initialization signal Vinit1 may be written to the control electrode Td3 of the driving transistor through the first transistor T1. The driving transistor Td may be initialized by writing the first initialization signal Vinit1 to the control electrode Td3 of the driving transistor, so that the driving transistor Td may be switched from the initialized state to other operating states in subsequent operating stages. For example, in a subsequent operation phase, the voltage of the driving transistor control electrode Td3 can be switched from the voltage corresponding to the initialization signal Vinit1 to other operation voltages. Thus, the afterimage phenomenon of the display panel can be improved, and the display stability can be improved.
In some possible implementations, the initialization signal line includes a first initialization signal line configured to write the first initialization signal Vinit1 to the pixel circuit 10. The second pole T12 of the first transistor may be coupled to the first initialization signal line so that the first initialization signal Vinit output from the first initialization signal line may be written into the second pole T12 of the first transistor.
In some embodiments, the gate T13 of the first transistor may be configured to control the turn-on and turn-off of the first transistor T1, i.e., the first transistor T1 may be turned on and off in response to the voltage of the gate T13. For example, the gate T13 of the first transistor may be coupled to a reset control signal line, and the reset control signal Sc1 output from the reset control signal line may be written into the gate T13. In response to the voltage of the reset control signal Sc1, the first transistor T1 may be turned on and off.
The first transistor T1 includes at least two (e.g., two; e.g., more than three) sub-transistors in series, including a sub-transistor T1a and a sub-transistor T1 b. Similarly, the sub-transistor includes a first pole, a second pole, and a control pole. For example, the sub-transistor T1a includes a first pole T1a1, a second pole T1a2, and a control pole T1a 3; the sub-transistor T1b includes a first pole T1b1, a second pole T1b2, and a control pole T1b 3.
The control electrodes of at least two (e.g., two; e.g., more than three) of the sub-transistors in series are coupled to each other as the control electrode T13 of the first transistor. Illustratively, the first transistor T1 includes two sub-transistors, i.e., a sub-transistor T1a and a sub-transistor T1b, connected in series. The gate T1a3 of the sub-transistor T1a and the gate T1b3 of the sub-transistor T1b are coupled to each other as a gate T13 of the first transistor. In response to the voltage of the gate T13, the sub transistor T1a and the sub transistor T1b may be turned on and off at the same time.
The second transistor T2 may include a first pole T21, a second pole T22, and a control pole T23. In the second transistor T2, the first pole T21 is coupled with the light emitting device 100, and exemplarily, the first pole T21 may be coupled with a first electrode of the light emitting device 100. The second pole T22 is configured to write a second initialization signal Vinit 2. In this way, when the second transistor T2 is in a turned-on state, the second initialization signal Vinit2 may be written to the light emitting device 100 through the second transistor T2. By writing the second initialization signal Vinit2 to the light emitting device 100, the light emitting device 100 may be initialized such that in a subsequent operating phase the light emitting device 100 may be switched from this initialized state to other operating states. For example, in a subsequent operation phase, the voltage on the first electrode of the light emitting device 100 may be switched from the voltage corresponding to the second initialization signal Vinit2 to other operation voltages. In some possible implementations, the second initialization signal Vinit2 may be a low-voltage electrical signal, and when the low-voltage electrical signal is written to the first electrode of the light emitting device 100, the driving current in the light emitting device 100 may be small or no, so that the light emitting device 100 emits light with small or no luminance, i.e., the pixel circuit 10 including the light emitting device 100 may display a black color block. In the subsequent working phase, the pixel circuit 10 is switched from the state of displaying the black color blocks to the state of displaying other color blocks. Therefore, the problem of afterimage of the display picture of the display panel can be improved, and the display stability is improved.
In some possible implementations, the initialization signal line further includes a second initialization signal line configured to write a second initialization signal Vinit2 to the pixel circuit 10. The second pole T22 of the second transistor may be coupled with the second initialization signal line such that the second initialization signal Vinit2 output by the second initialization signal line may be written into the second pole T22 of the second transistor.
In some embodiments, the gate T23 of the second transistor may be configured to control the turn-on and turn-off of the second transistor T2, i.e., the second transistor T2 may be turned on and off in response to the voltage of the gate T23. For example, the gate T23 of the second transistor may be coupled to a reset control signal line, and the reset control signal Sc1 output from the reset control signal line may be written into the gate T23. In response to the voltage of the reset control signal Sc1, the second transistor T2 may be turned on and off.
Based on the above structure of the pixel circuit 10, the work flow of the pixel circuit 10 may exemplarily include: a stage of initializing the driving transistor Td, a stage of initializing the light emitting device 100, a data writing stage, and a light emitting stage.
In the stage of initializing the driving transistor Td, the first transistor T1 is turned on. The first initialization signal Vinit1 may be written to the control electrode Td3 of the driving transistor Td through the first transistor T1, thereby initializing the driving transistor Td.
In a stage of initializing the light emitting device 100, the second transistor T2 is turned on, and the second initialization signal Vinit2 may be written to the light emitting device 100 through the second transistor T2, for example, the second initialization signal Vinit2 may be written to the first electrode of the light emitting device 100, thereby initializing the light emitting device 100.
In the data writing phase, the first transistor T1 is in a turned-off state, and the control electrode Td3 of the driving transistor writes an electrical signal, which may be, for example, a data signal Da or a data associated signal Da'.
In the light emitting stage, the first transistor T1 is in an off state, and the second transistor T2 is in an off state. In the driving transistor Td, the driving transistor Td is turned on in response to the voltage of the control electrode Td3 of the driving transistor, generating a current that drives the light emitting device 100 to emit light, which is output to the light emitting device 100, so that the light emitting device 100 emits light.
As described above, the driving transistor Td can control the magnitude of the current flowing through the first and second electrodes Td1 and Td2 in response to the voltage of the control electrode Td3, thereby controlling the light emission luminance of the light emitting device 100, and the light emission luminance of the light emitting device 100 can vary depending on the voltage of the control electrode Td 3. In some related art, a leakage current of the first transistor in an off state is large, that is, a current flowing between the first pole and the second pole of the first transistor in the off state of the first transistor is large. Also, since the first electrode of the first transistor is coupled to the control electrode Td3 of the driving transistor, during the light emitting period, the voltage on the control electrode Td3 of the driving transistor can be reduced due to the leakage current. Taking the driving transistor Td as a P-type transistor as an example, the voltage of the control electrode Td3 of the driving transistor is reduced, which results in a larger current for driving the light emitting device 100 to emit light in the pixel circuit of the related art, so that the luminance of the light emitting device 100 is too large, and the color block displayed by the pixel circuit is too bright, so that the bright point exists in the display screen of the display panel.
In order to solve the above-described problem, some embodiments of the present disclosure provide a pixel circuit in which, in the first transistor T1, the width-to-length ratio of the channel of at least one sub-transistor is smaller than the width-to-length ratio of the channel of the second transistor T2. For a transistor, the smaller the aspect ratio of the channel, the worse the on-performance of the transistor, e.g., the larger the threshold voltage Vth of the transistor may be. Taking the transistor as a P-type transistor for example, it is necessary to write a lower voltage on its control electrode to turn on the transistor. Further, the smaller the width-to-length ratio of the channel, the smaller the leakage current in the off state of the transistor can be because the on performance of the transistor becomes poor. Therefore, compared with the second transistor, the whole conduction performance of the first transistor can be poorer, the leakage current of the first transistor in an off state can be smaller in the process of light emitting of the light emitting device, and the bright point problem can be improved.
Further, since the width-to-length ratio of the channel of the at least one sub transistor is smaller than the width-to-length ratio of the channel of the second transistor, the width-to-length ratio of the channel of the second transistor may be larger. As described above, the second transistor may be configured to initialize the light emitting device, and the afterimage phenomenon of the display panel may be improved. The width-length ratio of the channel of the second transistor can be larger, so that the on-state performance of the second transistor can be better, and the initialization of the second transistor on the light-emitting device cannot be influenced. That is, the pixel circuit provided by the embodiment of the present disclosure can improve the problem of the bright spot of the display image of the display panel on the premise of improving the problem of the afterimage of the display image of the display panel.
In some embodiments, in at least two sub-transistors of the first transistor T1, the width-to-length ratio of the channel of each sub-transistor is the same. That is, the width-to-length ratios of the channels of the respective sub transistors are the same and are each smaller than the width-to-length ratio of the second transistor T2. In this way, the aspect ratio of the entire channel of the first transistor T1 can be further reduced, and the leakage current of the first transistor T1 in the off state can be further reduced, so that the problem of the bright point can be better improved.
In some embodiments, the pixel circuit may further include at least one of a capacitor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. Exemplarily, fig. 5 is an equivalent circuit diagram of a pixel circuit, showing a connection relationship between the above-described respective elements. The above elements will be described in detail with reference to fig. 5, respectively.
The capacitor C includes a first plate S1 and a second plate S2, the first plate S1 is coupled to the control electrode Td3 of the driving transistor, and the second plate S2 is configured to write the first power voltage signal ELVDD. For example, the second plate S2 may be coupled to the first power line EL1, and the first power voltage signal ELVDD output by the first power line EL1 may be written into the second plate S2 of the capacitor. The capacitor C may be configured to store an electrical signal, which may be written to the control electrode Td3 of the driving transistor during a light emitting period of the light emitting device 100, so that the driving transistor may generate a current for driving the light emitting device 100 to emit light in response to the electrical signal.
The third transistor T3 includes a first pole T31, a second pole T32, and a control pole T33. In the third transistor T3, the second pole T32 is coupled to the first pole Td1 of the driving transistor, and the first pole T31 is configured to write the data signal Da. For example, the first pole T31 may be coupled to a data line D, and a data signal Da output from the data line D may be written into the first pole T31. The gate T33 may be configured to control the turn-on and turn-off of the third transistor T3, i.e., the third transistor T3 may be turned on and off in response to the voltage of the gate T33. Illustratively, the gate electrode T33 of the third transistor may be coupled to a scan signal line, and a scan signal Sc3 output from the scan signal line may be written into the gate electrode T33 of the third transistor, and the third transistor T3 may be turned on and off in response to the scan signal Sc 3.
The fourth transistor T4 includes a first pole T41, a second pole T42, and a control pole T43. In the fourth transistor T4, the first pole T41 is coupled to the second pole Td2 of the driving transistor, and the second pole T42 is coupled to the control pole Td3 of the driving transistor. Due to the above-described structures of the third and fourth transistors T3 and T4, the second pole T32 of the third transistor T3 may be coupled to the control pole Td3 of the driving transistor through the driving transistor Td and the fourth transistor T4. The gate T43 of the fourth transistor may be configured to control the turn-on and turn-off of the fourth transistor T4, i.e., the fourth transistor T4 may be turned on and off in response to the voltage of the gate T43. Illustratively, the gate T43 of the fourth transistor may be coupled to a scan signal line, and a scan signal Sc3 output from the scan signal line may be written into the gate T43 of the fourth transistor, and the fourth transistor may be turned on and off in response to the scan signal Sc 3. In some embodiments, a scan signal line may be coupled to the control electrode T33 of the third transistor and may also be coupled to the control electrode T43 of the fourth transistor, and thus, the third transistor T3 and the fourth transistor T4 may be turned on at the same time or turned off at the same time. In other embodiments, the third transistor T3 may be coupled to one scan signal line, and the fourth transistor T4 may be coupled to another scan signal line, so that the third transistor T3 and the fourth transistor T4 may be controlled by two scan signal lines, respectively.
The fifth transistor T5 includes a first pole T51, a second pole T52, and a control pole T53. In the fifth transistor T5, the second pole T52 is coupled to the first pole Td1 of the driving transistor, and the first pole T51 is configured to write the first power supply voltage signal ELVDD. Illustratively, the first pole T51 may be coupled to the first power line EL1, and the first power signal ELVDD output from the first power line EL1 may be written to the first pole T51 of the fifth transistor. Accordingly, when the fifth transistor T5 is turned on, the first power signal ELVDD may be written to the first pole Td1 of the driving transistor through the fifth transistor T5. The gate T53 of the fifth transistor may be configured to control the turn-on and turn-off of the fifth transistor T5, i.e., the fifth transistor T5 may be turned on and off in response to the voltage of the gate T53. For example, the gate T53 of the fifth transistor may be coupled to a light emission control signal line, and a light emission control signal Sc2 output from the light emission control signal line may be written to the gate T53 of the fifth transistor, and the fifth transistor may be turned on and off in response to the light emission control signal Sc 2.
The sixth transistor T6 includes a first pole T61, a second pole T62, and a control pole T63. In the sixth transistor T6, the first pole T61 is coupled to the second pole Td2 of the driving transistor, and the second pole T62 is coupled to the light emitting device 100, for example, to the first electrode of the light emitting device 100. In this way, when the sixth transistor T6 is turned on, the current output from the driving transistor Td may be input to the light emitting device 100, and the light emitting device 100 is driven to emit light. The gate T63 of the sixth transistor may be configured to control the sixth transistor T6 to be turned on and off, i.e., the sixth transistor T6 may be turned on and off in response to the voltage of the gate T63. For example, the gate T63 of the sixth transistor may be coupled to a light emission control signal line, and the light emission control signal Sc2 output from the light emission control signal line may be written to the gate of the sixth transistor, and the sixth transistor T6 may be turned on and off in response to the light emission control signal Sc 2. In some embodiments, a light emission control signal line may be coupled to the gate T51 of the fifth transistor and may be coupled to the gate T61 of the sixth transistor, and thus, the fifth transistor T5 and the sixth transistor T6 may be turned on at the same time or turned off at the same time. In other embodiments, the gate T53 of the fifth transistor may be coupled to a light emission control signal line, and the gate T63 of the sixth transistor may be coupled to another light emission control signal line, so that the fifth transistor T5 and the sixth transistor T6 may be controlled by two light emission control signal lines, respectively.
Illustratively, based on the above structure of the pixel circuit 10, the work flow of the pixel circuit 10 may include: a stage of initializing the driving transistor Td, a stage of initializing the light emitting device 100, a data writing stage, and a light emitting stage.
Specifically, in the phase of initializing the driving transistor Td, the first transistor T1 may be turned on, and the first initialization signal Vinit1 is written into the control electrode Td3 of the driving transistor through the first transistor T1, thereby initializing the driving transistor Td. For example, in a stage of initializing the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned off.
In the stage of initializing the light emitting device 100, the second transistor T2 may be turned on, and the second initialization signal Vinit2 is written to the light emitting device 100, for example, to the first electrode of the light emitting device 100, through the second transistor T2, thereby initializing the light emitting device 100.
In the data writing phase, the first transistor T1 and the fifth transistor T5 are turned off. The driving transistor Td, the third transistor T3, and the fourth transistor T4 are turned on. The capacitor C may be charged through the third transistor T3, the driving transistor Td, and the fourth transistor T4. Due to the characteristics of the driving transistor Td, when the voltage of the node N1 becomes Vdata + Vth, the driving transistor Td is turned off, the charging process is ended, and the voltage of the electric signal written into the first plate S1 of the capacitor C is Vdata + Vth, where Vdata represents the voltage of the data signal Da and Vth represents the threshold voltage of the driving transistor Td. The second plate S2 of the capacitor C writes the first power supply voltage signal ELVDD due to the coupling with the first power supply line EL 2.
In some possible implementations, the data writing phase and the phase of initializing the light emitting device 100 may be performed simultaneously. That is, the third transistor T3, the fourth transistor T4, the driving transistor Td, and the second transistor T2 may be turned on, the fifth transistor T5, the sixth transistor T6, and the first transistor T1 may be turned off, and the initialization of the light emitting device 100 while charging the capacitor C may be achieved.
In the light emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. The driving transistor Td is turned on in response to a voltage of an electrical signal on the control electrode Td3, which may be an electrical signal written to the first plate S1 of the capacitor C during the data writing phase, so that a current may be generated through the first electrode Td1 and the second electrode Td2 of the driving transistor, which may be output to the light emitting device 100 to drive the light emitting device 100 to emit light.
Fig. 6 is a partially enlarged view of a portion of a display panel including one pixel circuit according to some embodiments of the present disclosure. It should be noted that, for clarity of illustration, fig. 6 does not show the entire structure of the light emitting device 100, and only shows the first electrode of the light emitting device 100 to show the position and connection relationship of the light emitting device 100. Referring to fig. 6, the display panel may have a multi-layer structure. Exemplarily, the display panel may include an active layer 300, a first pattern layer 400, a second pattern layer 500, and a third pattern layer 600 disposed on a substrate S.
Wherein the active layer 300 and the first pattern layer 400 overlap each other, transistors, such as the driving transistor Td, the first transistor T1, and the second transistor T2, and one or more of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, may be formed. A transistor formed by overlapping the active layer 300 and the first pattern layer 400 with each other may be referred to as a thin film transistor.
The material of the active layer 300 is, for example, a semiconductor material. A portion of the pattern of the active layer 300 may be conducted by a doping process, for example, a portion of the source layer 300 that is not directly opposite to the first pattern layer 400 in a direction perpendicular to the substrate S (e.g., a direction parallel to the z-axis) may be conducted. The conductive portions may serve as source and drain regions of the transistor. Wherein the source region may be a first pole of the transistor and the drain region may be a second pole of the transistor; alternatively, the source region may be a second pole of the transistor and the drain region may be a first pole of the transistor. The material of the first pattern layer 400 may be a conductive material, for example, a metal or an alloy.
To explain the active layer and the first pattern layer in more detail, fig. 7 is a top view of the active layer, fig. 8 is a top view of the first pattern layer, and fig. 9 is a top view of the active layer and the first pattern layer which are stacked. Referring to fig. 8 and 9, a portion of the first conductive layer 400 directly opposite the active layer 300 in a direction perpendicular to the substrate S (e.g., a direction parallel to the z-axis) may include a control electrode of one or more transistors. For example, the first conductive layer 400 may include a control electrode T13 of the first transistor (e.g., including a control electrode T1a3 of the sub-transistor T1a and a control electrode T1b3 of the sub-transistor T1 b), a control electrode T23 of the second transistor, and a control electrode Td3 of the driving transistor, and may further include one or more of a control electrode T33 of the third transistor, a control electrode T43 of the fourth transistor, a control electrode T53 of the fifth transistor, and a control electrode T63 of the sixth transistor.
Referring to fig. 7 and 9, a portion of the active layer 300 directly opposite the first conductive layer 400 may include channels of one or more transistors in a direction perpendicular to the substrate S (e.g., a direction parallel to the z-axis). Specifically, in a direction perpendicular to the substrate S (e.g., a direction parallel to the z-axis), a portion of the active layer 300 that is directly opposite to the control electrode of the transistor, that is, a portion of the active layer 300 that is covered by the control electrode of the transistor, may serve as a channel of the transistor. Based on the above, the active layer 300 may include the channel T1 ' of the first transistor (e.g., including the channel T1a ' of the sub transistor T1a and the channel T1b ' of the sub transistor T1 b), the channel T2 ' of the second transistor, and the channel Td ' of the driving transistor, and may further include one or more of the channel T3 ' of the third transistor, the channel T4 ' of the fourth transistor, the channel T5 ' of the fifth transistor, and the channel T6 ' of the sixth transistor.
To more clearly illustrate the structure of the transistor, fig. 10 is a partially enlarged view of a region B in fig. 9, showing the structure of a sub-transistor (e.g., the sub-transistor T1 a). It is understood that the structures of the other transistors may be similar to the structure of the sub-transistor shown in fig. 10, and therefore, the structures of the other transistors are not described in detail herein. Referring to fig. 10, the sub-transistor T1a may include a first pole T1a1 and a second pole T1a2, and a channel T1 a' between the first pole T1a1 and the second pole T1a 2. The length l1 of the channel T1a 'may be the distance between the first pole T1a1 and the second pole T1a2, and the length l1 of the channel T1 a' may also be equal to the width h1 of the gate T1a3 of the transistor located in the first patterned layer 400. The width w1 of the channel may be the width of the portion of the active layer 300 directly opposite the gate T1a 3. The width w1 of the channel may also be equal to the width d1 of the active pattern in the active layer 300.
With continued reference to fig. 9, as described above, in the pixel circuit provided in some embodiments of the present disclosure, in the first transistor T1, the width-to-length ratio of the channel of at least one sub-transistor is smaller than the width-to-length ratio of the channel of the second transistor T2. That is, the width and length of the channel of at least one of the sub-transistors are small, and thus the leakage current of the sub-transistor in the off state can be reduced. In order to reduce the width-to-length ratio of the channel of the sub-transistor, the length l1 of the channel of the sub-transistor may be increased, or the width w1 of the channel of the sub-transistor may be reduced. In some embodiments, the width w1 of the channel of each sub-transistor is equal to the width w2 of the channel of the second transistor T2. That is, by setting the width w1 of the channel of each sub-transistor to be equal to the width w2 of the channel of the second transistor T2 and setting the length l1 of the channel of at least one (e.g., one; as another example, a plurality) of the sub-transistors to be greater than the length l2 of the channel of the second transistor T2, the aspect ratio of the channel of at least one (e.g., one; as another example, each) of the sub-transistors is smaller than the aspect ratio of the channel of the second transistor T2. Due to the smaller size of the transistor, it is easier to increase the length of the channel of the transistor in terms of process than to decrease the width of the channel of the transistor, for example, it is easier to increase the width h1 of the gate of the sub-transistor in terms of process than to decrease the width d1 of the active pattern in the active layer 300, which is beneficial to improving the yield of the product.
In some embodiments, in the first transistor T1, the length l1 of the channel of at least one (e.g., one; as well as each) sub-transistor is 0.8 to 1.2 μm greater than the length l2 of the channel of the second transistor T2, thereby achieving the goal that the width-to-length ratio of the channel of at least one (e.g., one; as well as each) sub-transistor is less than the width-to-length ratio of the channel of the second transistor T2. For example, the length l1 of the channel of at least one (e.g., one; as well as each) sub-transistor is 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1,2 μm larger than the length l2 of the channel of the second transistor T2. In some possible implementations, as described above, the width w1 of the channel of each sub-transistor is equal to the width w2 of the channel of the second transistor, and at this time, the length l1 of the channel of each sub-transistor may be 0.8 to 1.2 μm greater than the length l2 of the second transistor T2.
In some embodiments, considering the ease of the process and the product effect, in the first transistor T1, the width w1 of the channel of at least one (e.g., one; and, for example, each) sub-transistor is 2.0 to 3.0 μm, and the length l1 is 2.7 to 4.0 μm. Illustratively, the width w1 of the channel of at least one (e.g., one; and as another example, each) of the sub-transistors is 2.3 + -0.2 μm and the length l1 is 3.5 + -0.2 μm. For example, the width w1 of the channel of at least one (e.g., one; and as a further example, each) of the sub-transistors is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, or 3.0 μm; the length l1 of the channel of at least one (e.g., one; and as another example, each) of the sub-transistors is 2.7 μm, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, or 4.0 μm.
In some embodiments, the width wd of the channel of the driving transistor Td is greater than the width w2 of the channel of the second transistor T2. Thus, the uniformity of the size of the channel of the driving transistor Td can be improved, and the performance of the driving transistor Td can be improved. Illustratively, the width w2 of the channel of the driving transistor Td is 3.0 ± 0.2 μm, for example, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, or 3.2 μm.
Based on the foregoing, in some embodiments, at least one (e.g., one; and as another example, each) of the sub-transistors in the first transistor has a channel with a width of 2.3 ± 0.2 μm and a length of 3.5 ± 0.2 μm. At least one (e.g., one; and as another example, each) of the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor has a channel with a width of 2.3 ± 0.2 μm and a length of 2.5 ± 0.2 μm. The width of the channel of the driving transistor is 3.0 + -0.2 μm, and the length is 20.7 + -0.2 μm. Therefore, the problem of afterimage and the problem of bright spots of the display screen of the display panel can be well improved.
As described above, the display panel includes a plurality of pixel circuits, and the pixel driving circuits may be distributed in an array in each pixel circuit. The position of the pixel circuit can be represented by the position of the pixel driving circuit, and based on this, the pixel circuit can also be said to be distributed in an array, as shown in fig. 2. Fig. 11 shows the structure of two pixel circuits and signal lines in two rows and one column (e.g., N-1 th row and N-th row, M-th column) in fig. 2. Referring to fig. 11, the display panel may include a first pixel circuit 10a located at an N-1 th (N is an integer greater than 1) row and a second pixel circuit 10b located at an N-th (N is an integer greater than 1) row in some embodiments. Wherein the content of the first and second substances,the first pixel circuit 10a and the second pixel circuit 10b may be the pixel circuits provided in any of the embodiments described above. The display panel may further include a reset control signal line R in the N-1 th row (or the N-1 th row)N-1Reset signal line RN-1The functions and the connection relationship with the pixel circuit can be as described above, and are not described herein again. Reset signal line RN-1May be coupled to the first pixel circuit 10a and may be coupled to the second pixel circuit 10 b. Specifically, referring to fig. 12, the control electrodes T13-10b of the first transistors in the second pixel circuit 10b in the nth row and the control electrodes T23-10a of the second transistors in the first pixel circuit 10a in the nth row are both connected to the reset control signal line R in the nth-1 rowN-1And (4) coupling. Thus, through a reset control signal line RN-1That is, the second transistor in the first pixel circuit 10a and the first transistor in the second pixel circuit 10b can be controlled, so that the structure of the display panel can be made more compact, and the size of the display panel can be reduced.
In some embodiments, in the first transistor of the second pixel circuit 10b, the control electrodes of the respective sub-transistors are coupled to each other and form an integral pattern U. Illustratively, the first transistor includes two sub-transistors coupled to each other, the two sub-transistors respectively include gates T1a3-10b and T1b3-10b, and the gates T1a3-10b and T1b3-10b are coupled to each other and form an integral pattern U. And, the integrated pattern U and the reset control signal line RN-1And (4) coupling.
Further, the reset control signal line RN-1The integral pattern U and the control electrodes T23-10a of the second transistors in the first pixel circuit 10a are located in the same pattern layer, for example, in the first pattern layer 400. And, the width k of the integral pattern U is greater than the width l2 of the control electrode T23-10a of the second transistor and greater than the reset control signal line RN-1Width f of (d). In this way, the length of the channel of at least one (e.g., one; and as another example, each) of the first transistors in the second sub-pixel 10b may be greater than the length of the channel of the second transistor in the first sub-pixel 10 a. Further, it may be implemented in a pixel circuit (e.g., each pixel circuit), the firstThe length of the channel of at least one (e.g., one; as another example) of the sub-transistors in the transistor is greater than the length of the channel of the second transistor, which in turn can achieve the objective that the width-to-length ratio of the channel of at least one (e.g., one; as another example) of the sub-transistors in the first transistor is less than the width-to-length ratio of the channel of the second transistor. In addition, the reset control signal line R is reset when the length of the channel of the sub transistor is larger than that of the channel of the second transistorN-1May also be narrower, which may make the structure of the pixel circuit more compact.
With continued reference to FIG. 11, in some embodiments, the display panel further includes a first light emission control signal line EN-1And a second light emission control signal line EN. First light emission control signal line EN-1Can be positioned at the N-1 th row (i.e. the first light-emitting control signal line E)N-1An N-1 th emission control signal line) and is coupled to the first pixel circuit 10a of the N-1 th row. Second light emission control signal line ENCan be positioned in the Nth row (i.e. the second light-emitting control signal line E)NAn nth light emission control signal line) and is coupled to the second pixel circuit 10 b. The connection relationship between a pixel circuit and the light-emitting control signal line can refer to the above description, and is not described herein again. Based on the connection relationship of one pixel circuit and the light emission control signal line described above, referring to fig. 12, the second light emission control signal line ENMay be coupled to the control electrode of the fifth transistor T5 and the control electrode of the sixth transistor T6 in the second pixel circuit 10 b. Similarly, the first light emission control signal line may be coupled to the control electrode of the fifth transistor and the control electrode of the sixth transistor in the first pixel circuit 10 a.
With continued reference to fig. 11, the display panel may further include a first scanning signal line GN-1And a second scanning signal line GN. First scanning signal line GN-1Can be located at the N-1 th row (i.e., the first scanning signal line G)N-1An N-1 th scanning signal line) and is coupled to the first pixel circuit 10a of the N-1 th row. Second scanning signal line GNCan be located at the Nth row (i.e. the second scanning signal line G)NThe nth scan signal line) and is coupled to the second pixel circuit 10 b. AThe connection relationship between the pixel circuits and the scan signal lines can refer to the above description, and is not repeated herein. Based on the connection relationship of one pixel circuit and the scanning signal line described above, referring to fig. 12, the second scanning signal line GNMay be coupled to the control electrodes of the third and fourth transistors T3 and T4 in the second pixel circuit 10 b. Similarly, the first scan signal line may be coupled to the control electrodes of the third transistor and the fourth transistor in the first pixel circuit 10 a.
In some embodiments, the reset signal line R (e.g., including the reset signal line R)N-1) A scanning signal line G (for example, including a first scanning signal line G)N-1And a second scanning signal line GN) And a light emission control signal line E (e.g., including a first light emission control signal line E)N-1And a second light emission control signal line EN) And the integral pattern U may be located in the same pattern layer, for example, in the first pattern layer 400.
In some embodiments, referring to fig. 8, the first pattern layer 400 may further include a first plate S1 of a capacitor. That is, the first plate S1 may be located in the same pattern layer as the reset signal line R, the scan signal line G, and the light emission control signal line E, and the integral pattern U.
With continued reference to fig. 12, in some embodiments, the second pattern layer 500 may further include an initialization signal line Vi. The function of the initialization signal line Vi and the connection relationship with the pixel circuit can refer to the above description, and are not described herein again. In some possible implementations, the second pole of the second transistor in the first pixel circuit 10a located in the N-1 th row and the second pole of the first transistor in the second pixel circuit 10b located in the nth row may be coupled to the same initialization signal line, as shown in fig. 12. In other possible implementations, referring to fig. 13, in the display panel, the second pole T22-10a of the second transistor in the first pixel circuit 10a located in the N-1 th row may be coupled to one initialization signal line, and the second pole T12-10b of the first transistor in the second pixel circuit 10b located in the N-1 th row may be coupled to another initialization signal line.
With continued reference to fig. 12, in some embodiments, the second patterning layer 500 may also include a second electrode of the capacitor C.
In some embodiments, the third pattern layer 600 may further include a data line D and a first power line EL 1. The functions of the data line D and the first power line EL1 and the connection relationship with the pixel circuit can be referred to the above description, and are not described again. The third pattern layer 600 may further include a first electrode of the light emitting device 100.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (15)

1. A pixel circuit, comprising:
a light emitting device;
a driving transistor including a first electrode, a second electrode, and a control electrode, in the driving transistor, the second electrode is coupled to the light emitting device, the driving transistor is configured to control a magnitude of a current flowing through the first electrode and the second electrode in response to a voltage of the control electrode;
a first transistor including a first pole, a second pole, and a control pole, in the first transistor, the first pole is coupled to the control pole of the driving transistor, and the second pole is configured to write a first initialization signal;
a second transistor including a first pole, a second pole, and a control pole, in which the first pole is coupled to the light emitting device and the second pole is configured to write a second initialization signal;
the first transistor comprises at least two sub-transistors connected in series, control electrodes of the at least two sub-transistors are mutually coupled to form a control electrode of the first transistor, and the width-to-length ratio of a channel of at least one sub-transistor is smaller than that of a channel of the second transistor.
2. The pixel circuit according to claim 1,
in the at least two sub-transistors, the width-to-length ratio of the channel of each sub-transistor is the same.
3. The pixel circuit according to any one of claims 1 to 2,
the width of the channel of each sub-transistor is equal to the width of the channel of the second transistor.
4. The pixel circuit according to claim 3,
the length of the channel of at least one sub-transistor is 0.8 to 1.2 μm greater than the length of the channel of the second transistor.
5. The pixel circuit according to claim 1,
the width of the channel of at least one sub-transistor is 2.0-3.0 μm, and the length is 2.7-4.0 μm.
6. The pixel circuit of claim 5,
the width of the channel of at least one sub-transistor is 2.3 + -0.2 μm and the length is 3.5 + -0.2 μm.
7. The pixel circuit according to claim 1,
the width of the channel of the driving transistor is larger than the width of the channel of the second transistor.
8. The pixel circuit according to claim 7,
the width of the channel of the driving transistor is 3.0 +/-0.2 mu m.
9. The pixel circuit according to claim 1, further comprising:
at least one of a capacitor, a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor;
wherein the capacitor comprises a first plate coupled to the control electrode of the drive transistor and a second plate configured to write a supply voltage signal;
the third transistor includes a first pole, a second pole, and a control pole, in which the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write a data signal;
the fourth transistor includes a first pole, a second pole, and a control pole, and in the fourth transistor, the first pole is coupled to the second pole of the driving transistor, and the second pole is coupled to the control pole of the driving transistor;
the fifth transistor includes a first pole, a second pole, and a control pole, in the fifth transistor, the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write the power supply voltage signal;
the sixth transistor includes a first electrode, a second electrode, and a control electrode, and in the sixth transistor, the first electrode is coupled to the second electrode of the driving transistor, and the second electrode is coupled to the light emitting device.
10. A display panel, comprising: a plurality of pixel circuits, each pixel circuit being a pixel circuit as claimed in any one of claims 1 to 9.
11. The display panel according to claim 10,
the plurality of pixel circuits includes: a first pixel circuit located at the N-1 th row and a second pixel circuit located at the N-th row;
the display panel further includes:
a reset control signal line to which a control electrode of a first transistor in the second pixel circuit and a control electrode of a second transistor in the first pixel circuit are both coupled;
wherein N is an integer greater than 1.
12. The display panel according to claim 11,
in the first transistor of the second pixel circuit, control electrodes of the respective sub-transistors are coupled to each other and form an integral pattern, the integral pattern being coupled to the reset control signal line;
the reset control signal line, the integral pattern, and a control electrode of a second transistor in the first pixel circuit are located in the same pattern layer, and a width of the integral pattern is greater than a width of the control electrode of the second transistor and greater than a width of the reset control signal line.
13. The display panel according to claim 12,
the pixel circuit includes a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor;
the display panel further includes:
a first light emission control signal line and a second light emission control signal line, a control electrode of a fifth transistor and a control electrode of a sixth transistor in the first pixel circuit being coupled to the first light emission control signal line, a control electrode of a fifth transistor and a control electrode of a sixth transistor in the second pixel circuit being coupled to the second light emission control signal line;
a first scanning signal line to which a control electrode of a fourth transistor and a control electrode of a third transistor in the first pixel circuit are coupled, and a second scanning signal line to which a control electrode of a fourth transistor and a control electrode of a third transistor in the second pixel circuit are coupled;
wherein the first light emission control signal line, the second light emission control signal line, the first scanning signal line, the second scanning signal line, and the integrated pattern are located in the same pattern layer.
14. The display panel according to claim 12,
the pixel circuit includes a capacitor;
the first plate of the capacitor is in the same pattern layer as the integral pattern.
15. A display device comprising the display panel according to any one of claims 10 to 14.
CN202111032795.0A 2021-09-03 2021-09-03 Pixel circuit, display panel and display device Pending CN113725274A (en)

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