CN113241387A - Artificial synapse transistor array and regulation and control method and application thereof - Google Patents

Artificial synapse transistor array and regulation and control method and application thereof Download PDF

Info

Publication number
CN113241387A
CN113241387A CN202110461811.1A CN202110461811A CN113241387A CN 113241387 A CN113241387 A CN 113241387A CN 202110461811 A CN202110461811 A CN 202110461811A CN 113241387 A CN113241387 A CN 113241387A
Authority
CN
China
Prior art keywords
artificial synapse
array
transistor array
transistors
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110461811.1A
Other languages
Chinese (zh)
Other versions
CN113241387B (en
Inventor
李彩虹
杜文
巫江
王志明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Original Assignee
University of Electronic Science and Technology of China
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China filed Critical University of Electronic Science and Technology of China
Priority to CN202110461811.1A priority Critical patent/CN113241387B/en
Publication of CN113241387A publication Critical patent/CN113241387A/en
Application granted granted Critical
Publication of CN113241387B publication Critical patent/CN113241387B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
    • H01L31/113—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor
    • H01L31/1136—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor being of the conductor-insulator-semiconductor type, e.g. metal-insulator-semiconductor field-effect transistor the device being a metal-insulator-semiconductor field-effect transistor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1446—Devices controlled by radiation in a repetitive configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Computing Systems (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • Computational Linguistics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Artificial Intelligence (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

The invention discloses an artificial synapse transistor array, which is sequentially provided with a substrate layer, a channel layer and an electrode layer from bottom to top. According to the artificial synapse transistor array, the channel layer and the electrode layer are sequentially arranged on the substrate layer, silicon of the substrate layer is used as a back gate structure, the material of the channel layer is large-area and uniform multilayer molybdenum disulfide, the transistor can be arrayed and can work in visible light and near infrared light wave bands, the molybdenum disulfide is rich in defect states, constraint of current carriers can be enhanced, and strong synapse plasticity, high sensitivity and low power consumption are achieved. Therefore, the artificial synapse transistor integrates the sensing-storage-preprocessing functions, and the simulation of human eye perception and human brain storage can be realized.

Description

Artificial synapse transistor array and regulation and control method and application thereof
Technical Field
The invention relates to the field of bionic synapses, in particular to an artificial synapse transistor array and a regulation and control method and application thereof.
Background
The artificial synapse transistor has wide application in bionic human eye perception and brain storage. Computing and imaging based on artificial synapse transistors often requires large area arrays and low power consumption as well as high sensitivity. In the aspect of bionic human eyes, most systems based on artificial synapse transistors can only sense visible light wave bands, and are not sensitive to ultra-short light stimulation pulses. In the aspect of information storage, the requirements of simulating human brain storage can be met only by strong synaptic plasticity and low power consumption and high contrast of short-term plasticity and long-term plasticity. In terms of information processing, processing efficiency is low and power consumption is high due to the existence of a separation, i.e., a von neumann bottleneck.
In recent years, synaptic transistors, memristors, phase change memories and the like based on two-dimensional materials are largely used for simulating biological nerves. However, such a synapse transistor based on two-dimensional material may need to be assisted by other materials or structures for enhancing carrier confinement, and the power consumption of a single optical pulse event is at least fJ level at present, so that the difficulty of device preparation is increased and the high power consumption is not favorable for subsequent complex applications. Meanwhile, the synaptic transistor also requires a channel material to realize large-area preparation.
Disclosure of Invention
In order to solve the defects in the prior art, the invention provides an artificial synapse transistor array, the channel layer material of the artificial synapse transistor is set to be large-area, uniform, multilayer and defect-state-rich molybdenum disulfide, so that the device can realize response to ultrashort optical pulses and has extremely low power consumption, meanwhile, the substrate silicon is used as a back gate structure, so that a single device is easy to array, the problem of great process difficulty caused by complex structure in the preparation process is solved, and the gate regulation and control can realize enhancement and inhibition of synapse plasticity.
In order to achieve the above purpose, the invention firstly provides the following technical scheme:
an artificial synapse transistor comprises a substrate layer, a channel layer and an electrode layer from bottom to top in sequence, wherein the substrate layer is silicon and silicon dioxide; the channel layer is a large-area uniform molybdenum disulfide film; an electrode layer is disposed on the channel layer.
The invention also provides the following optimization scheme:
preferably, the substrate layer is made of a silicon and silicon dioxide double-layer structure: silicon dioxide was evaporated by magnetron sputtering onto a p-type doped silicon wafer, wherein the silicon dioxide thickness was 285 nm.
The substrate layer is made of silicon and silicon dioxide, wherein the silicon dioxide is used as a gate oxide layer, the silicon is used as a back gate, the preparation method of the silicon dioxide is magnetron sputtering, the thickness is 285nm, the subsequent channel layer growth is easy, the thickness of the gate oxide layer is proper, and the gate oxide layer is not easy to be broken down by gate voltage. And the back gate structure device is simpler to prepare.
Preferably, the material of the channel layer is molybdenum disulfide with a large area and uniformity.
Preferably, the growing method of the channel layer is a chemical vapor deposition method.
Preferably, the chemical vapor deposition method includes:
ultrasonically cleaning the substrate layer in acetone and isopropanol for 5min respectively;
mixing molybdenum oxide and sodium chloride according to the mass ratio of about 6:1 to form a molybdenum source precursor;
taking 255 parts of sulfur powder as a sulfur source precursor according to the mass parts;
then placing the molybdenum source precursor in the center of a single-temperature-zone 1-inch tube furnace, and placing the sulfur source precursor on the upstream of the molybdenum source precursor;
preferably, the distance between the molybdenum source and the sulfur source precursor is about 23 cm;
then placing the substrate layers at the downstream of the molybdenum source precursor in a face-to-face manner, wherein the vertical distance between the substrate layers is about 2 mm;
and exhausting residual gas in the tube furnace by using high-purity argon-hydrogen mixed gas, wherein the exhausting time is about 10 min.
Pumping the vacuum pump for the tube furnace to low pressure, wherein the pressure is about 0.4 Torr;
respectively introducing argon gas at 32-48sccm and hydrogen gas at 4-6sccm into the quartz tube;
then the temperature of the tubular furnace is raised to 180-250 ℃, wherein the temperature raising rate is 50 ℃/min;
when the temperature of the tubular furnace is increased to 670 ℃, the sulfur powder is increased to 180-250 ℃ by a heating belt;
keeping the tubular furnace at the constant temperature of 680-780 ℃ for half an hour to obtain a sample;
finally, the tube furnace is removed, and the sample is naturally cooled to room temperature.
Preferably, the electrode layer is made of titanium and gold, the thickness of the titanium is 10nm, and the thickness of the gold is 100 nm.
Preferably, the electrode layer is arranged on the channel layer in an array.
The invention also discloses a regulation and control method of the artificial synapse transistor array, which comprises the following methods:
(1) laser irradiation is carried out between electrodes of an artificial synapse transistor array, and the laser wavelengths are respectively 405, 520, 635,800 and 850 nm; the artificial synapse transistor array in the state is adopted to simulate the recognition of human eyes to visible light, and the visual boundary of the human eyes is expanded to near infrared light;
(2) gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; simulating the response of biological synapses to ultrashort light pulses by using the artificial synapse transistor array in the state;
(3) gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; adopting the artificial synapse transistor array in the state to simulate the power consumption of biological synapses on the ultra-short light pulse events;
(4) by shining a single light pulse of varying power between the electrodes of the array of artificial synapse transistors, the power is from 27.7mW/cm2Gradually reduced to 1mW/cm2(ii) a Adopting the artificial synapse transistor array in the state to simulate the response of human eyes to different light intensities;
(5) irradiating double light pulses with the same intensity and different intervals and time between the electrodes of the artificial synapse transistor array, wherein the interval is gradually reduced from 16s to 0.3 s; simulating double-pulse facilitation of biological synapses by adopting the artificial synapse transistor array in the state;
(6) gradually increasing the number of pulses from 10 to 100 by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain;
(7) gradually increasing the pulse frequency from 0.2Hz to 5Hz by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain;
(8) inputting optical pulse, electric pulse, input optical electric pulse and input electric pulse only between the electrodes of the artificial synapse transistor array; adopting the artificial synapse transistor array in the state to simulate the associative learning function of the human brain;
(9) applying a voltage from a negative voltage to a positive voltage by applying a voltage to the substrate silicon of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the influence of negative emotion and positive emotion on the human brain memory function;
(10) by performing single and multiple letter identification on the artificial synapse transistor array; simulating neuro-visual imaging using the array of artificial synapse transistors in this state;
(11) sequentially identifying different images by carrying out different image identification on the artificial synapse transistor array; the artificial synapse transistor array in the state is adopted to simulate addition and subtraction calculation of a logic circuit.
The artificial synapse transistor array can be applied to simulating biological synapses related to visual recognition and brain storage.
The invention provides an artificial synapse transistor, which sequentially comprises a substrate layer, a channel layer and an electrode layer from bottom to top, wherein the substrate layer is silicon and silicon dioxide, and the channel layer is large-area uniform molybdenum disulfide; an electrode layer is arranged on the channel layer; therefore, the channel layer and the electrode layer are sequentially arranged on the substrate layer, silicon of the substrate layer is used as a back gate structure, the material of the channel layer is a large-area uniform multilayer molybdenum disulfide, the transistor can realize array and can work in visible light and near infrared light wave bands, the molybdenum disulfide is rich in defect states, the constraint of current carriers can be enhanced, and strong synaptic plasticity, high sensitivity and low power consumption are realized. Thus enabling the artificial synapse transistors to mimic human eye perception and human brain storage.
Drawings
FIG. 1 is a perspective view of an artificial synapse transistor in accordance with a preferred embodiment of the invention;
the specific reference numerals are:
11 a substrate layer; 12 a channel layer; 13 electrode layer.
Detailed Description
In order that those skilled in the art will better understand the technical solutions of the present invention, the present invention will be further described in detail with reference to the following embodiments.
As shown in fig. 1, the artificial synapse transistor of the invention comprises, from bottom to top, a substrate layer 11, a channel layer 12 and an electrode layer 13, wherein the substrate layer 11 is silicon and silicon dioxide; the channel layer 12 is a large-area uniform molybdenum disulfide film; an electrode layer 13 is provided on the channel layer 12.
The artificial synapse transistor comprises a substrate layer 11, a channel layer 12 and an electrode layer 13;
the preparation method of the substrate layer 11 comprises the following steps:
depositing a silicon dioxide layer on a p-type doped silicon wafer by a magnetron sputtering method;
the substrate layer 11 is made of a silicon and silicon dioxide double-layer structure, and the thickness of the silicon dioxide is 285 nm. The material of the channel layer 12 is molybdenum disulfide with a large area and uniformity.
The growth method of the channel layer 12 is a chemical vapor deposition method.
The chemical vapor deposition method includes:
ultrasonic cleaning the substrate layer 11 in acetone and isopropanol for 5min respectively to remove pollutants on the surface of the substrate layer 11;
molybdenum oxide and sodium chloride are mixed according to the mass ratio of about 6:1 to form a molybdenum source precursor, and a chloride molybdenum source which is easier to evaporate can be generated during heating, so that the subsequent sulfuration reaction can be favorably carried out to generate MoS2；
255 parts of sulfur powder is used as a sulfur source precursor according to the mass parts, and a sulfur-rich reaction atmosphere is provided;
then, placing the molybdenum source precursor in the center of a 1-inch tubular furnace with a single temperature zone, placing a sulfur source precursor at the upstream of the molybdenum source precursor, and carrying the molybdenum source vapor to react and deposit at the substrate together by using the sulfur vapor at high temperature as a carrier gas;
preferably, the distance between the molybdenum source and the sulfur source precursor is about 23cm, so that the sulfur source is outside the single-temperature zone, and the temperature can be independently controlled through a heating zone;
then, the substrate layers 11 are placed at the downstream of the molybdenum source precursor in a face-to-face mode, wherein the vertical distance between the substrate layers 11 is about 2mm, and reaction gas is limited in the area, so that more uniform film growth is realized;
and (3) exhausting residual gas in the tube furnace by using high-purity argon-hydrogen mixed gas, wherein the exhaust time is about 10min, and the interference of oxygen on the vulcanization reaction is eliminated.
Pumping the vacuum pump for the tube furnace to low pressure, wherein the pressure is about 0.4Torr, and the low-pressure CVD is favorable for the uniform growth of the film;
introducing argon gas at a flow rate of 32-48sccm and hydrogen gas at a flow rate of 4-6sccm into the quartz tube respectively to serve as carrier gas and provide a reducing atmosphere;
then, the tubular furnace is heated to 680-780 ℃, wherein the heating rate is 50 ℃/min, and the temperature is rapidly raised to the evaporation temperature of the molybdenum source, so that unnecessary nucleation in the reaction process is reduced;
when the temperature of the tubular furnace is increased to 670 ℃, the sulfur powder is increased to 180-250 ℃ by a heating belt, so that the sulfur source and the molybdenum source reach the reaction temperature at the same time, and the non-film growth caused by early participation of the sulfur source is prevented;
keeping the tubular furnace at the constant temperature of 680-780 ℃ for half an hour to obtain a sample, and enabling the sulfur source and the molybdenum source to fully react to realize large-area uniform film growth;
and finally, the tube furnace is moved away, so that the sample is naturally cooled to room temperature, and the quality of the growing film, namely the channel layer 12, is improved.
The preparation method of the electrode layer 13 comprises the following steps:
the electrode layer 13 is patterned by a standard photolithography system. The preparation process of the electrode layer 13 is normal-temperature electron beam evaporation, the material of the electrode layer 13 is titanium and gold, the thickness of the titanium is 10nm, the titanium is used as an adhesion layer and is beneficial to better contact between the gold and the channel layer 12, the thickness of the gold is 100nm, so that a probe is not easy to penetrate through the electrode to damage the channel layer 12 during testing, and then the residual photoresist lift-off is removed in an acetone solution to form an electrode pattern.
The electrode layer 13 is periodically disposed on the channel layer 12, wherein the channel dimension of a single device is 25 μm long by 10 μm wide, and the device-to-device spacing is about 300 μm, including but not limited to this dimension.
The invention also discloses a regulation and control method of the artificial synapse transistor array, which comprises the following methods:
1. laser irradiation is carried out between electrodes of an artificial synapse transistor array, and the laser wavelengths are respectively 405, 520, 635,800 and 850 nm; the artificial synapse transistor array in the state is adopted to simulate the recognition of human eyes to visible light, and the visual boundary of the human eyes is expanded to near infrared light; the single-layer molybdenum disulfide channel layer can only detect visible light, and the detection of visible light and near infrared light can be realized by the thick layer of the single-layer molybdenum disulfide channel layer, so that the visual range of human eyes can be widened by the prepared device.
2. Gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; simulating the response of biological synapses to ultrashort light pulses by using the artificial synapse transistor array in the state; the channel layer is defect-rich and sensitive to light, so that the device is responsive to ultra-short optical pulses.
3. Gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; adopting the artificial synapse transistor array in the state to simulate the power consumption of biological synapses on the ultra-short light pulse events; the device is very sensitive to ultrashort optical pulses, so that ultralow power consumption of the device is possible.
4. By shining a single light pulse of varying power between the electrodes of the array of artificial synapse transistors, the power is from 27.7mW/cm2Gradually reduced to 1mW/cm2(ii) a Adopting the artificial synapse transistor array in the state to simulate the response of human eyes to different light intensities;
5. irradiating double light pulses with the same intensity and different intervals and time between the electrodes of the artificial synapse transistor array, wherein the interval is gradually reduced from 16s to 0.3 s; simulating double-pulse facilitation of biological synapses by adopting the artificial synapse transistor array in the state; the continuous photoconductive effect of the device allows a double pulse facilitation.
6. Gradually increasing the number of pulses from 10 to 100 by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain; the difference of the light response intensity, the holding time and the like of the device under the long-term and short-term signal stimulation is obvious, so that the device can obviously distinguish a continuous event from a transient event, and the function of image preprocessing is realized.
7. Gradually increasing the pulse frequency from 0.2Hz to 5Hz by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain; the optical response difference of the device under high and low frequency input signals is obvious, so that the high-pass filtering function is realized.
8. Inputting optical pulse, electric pulse, input optical electric pulse and input electric pulse only between the electrodes of the artificial synapse transistor array; adopting the artificial synapse transistor array in the state to simulate the associative learning function of the human brain; the channel layer is very sensitive to both optical signals and electrical signals, so that the device can realize optical stimulation and electrical stimulation response.
9. Applying a voltage from a negative voltage to a positive voltage by applying a voltage to the substrate silicon of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the influence of negative emotion and positive emotion on the human brain memory function; and the charge constraint and the de-constraint under the control of the grid voltage enable the photocurrent of the device to be increased or reduced, so that the control of the memory function of the human brain by the emotion is realized.
10. By performing single and multiple letter identification on the artificial synapse transistor array; simulating neuro-visual imaging using the array of artificial synapse transistors in this state; repeated stimulation enables the device to achieve deep learning, thereby improving the letter or image recognition rate.
11. Sequentially identifying different images by carrying out different image identification on the artificial synapse transistor array; the artificial synapse transistor array in the state is adopted to simulate addition and subtraction calculation of a logic circuit.
The artificial synapse transistor array can be applied to simulating biological synapses related to visual recognition and brain storage.
The technical solution of the present invention will be further explained with reference to specific examples.
Example one
The embodiment provides an artificial synapse transistor array based on molybdenum disulfide, as shown in fig. 1, the artificial synapse transistor includes, from bottom to top, a substrate layer 11, a channel layer 12, and an electrode layer 13, where the electrode layer 13 is disposed on the channel layer 12.
Here, the material of the substrate layer 11 is generally silicon and silicon dioxide, and specifically, the thickness of silicon dioxide is 285 nm. Therefore, the silicon dioxide is used as a gate oxide layer, and the silicon is used as a back gate, so that the preparation of the device can be simplified.
The channel layer 12 is grown on the substrate layer 11 by a chemical vapor deposition method, the material of the channel layer 12 is molybdenum disulfide, and specifically, the channel layer 12 is a large-area uniform thin film. In this way, the area of the channel layer 12 is sufficiently large and uniform, and device arraying can be achieved.
The electrode layer 13 is deposited on the channel layer 12 through an electron beam evaporation method, wherein the electrode layer 13 is made of titanium and gold, the thickness of the titanium is 10nm, the titanium is used as an adhesion layer, better contact between the gold and the channel layer 12 is facilitated, and the thickness of the gold is 100nm, so that a probe is not easy to penetrate through the electrode to damage the channel layer 12 during testing.
Further, in the embodiment of the present invention, although the single-layer molybdenum disulfide is a direct band gap, the detection band thereof is mainly in the visible light band, and in order to realize the detection of visible light and near-infrared light, thereby widening the visual range of the human eye-like, therefore, the channel layer 12, which is the prepared multilayer molybdenum disulfide thin film, is capable of detecting the visible light and the near-infrared band by using the low-pressure chemical vapor deposition method, and has the advantages of uniform thickness, high carrier mobility, high charge confinement rate, long confinement charge retention time, and effective enhancement of the synaptic plasticity of the artificial synapse device.
Specifically, the chemical vapor deposition method includes:
ultrasonic cleaning the substrate layer 11 in acetone and isopropanol for 5min respectively;
mixing molybdenum oxide and sodium chloride according to the mass ratio of about 6:1 to form a molybdenum source precursor;
taking 255 parts of sulfur powder as a sulfur source precursor according to the mass parts;
then placing the molybdenum source precursor in the center of a 1-inch tubular furnace with a single temperature zone, and placing a sulfur source precursor at the upstream of the molybdenum source precursor, wherein the distance between the molybdenum source and the sulfur source precursor is about 23 cm;
then, the substrate layers 11 are placed at the downstream of the molybdenum source precursor in a face-to-face mode, wherein the vertical distance between the substrate layers 11 is about 2 mm;
exhausting residual gas in the tube furnace by using high-purity argon-hydrogen mixed gas, wherein the exhausting time is about 10 min;
pumping the vacuum pump for the tube furnace to low pressure, wherein the pressure is about 0.4 Torr;
respectively introducing argon gas at 32-48sccm and hydrogen gas at 4-6sccm into the quartz tube;
then raising the temperature of the tubular furnace to 680-780 ℃, wherein the temperature raising rate is 50 ℃/min;
when the temperature of the tubular furnace is increased to 670 ℃, the sulfur powder is increased to 180-250 ℃ by a heating belt;
keeping the tubular furnace at the constant temperature of 680-780 ℃ for half an hour to obtain a sample;
finally, the tube furnace is removed, and the sample is naturally cooled to room temperature.
Example two
Specifically, the preparation method of the molybdenum disulfide-based artificial synapse transistor unit device comprises the following steps:
step 1: providing the substrate layer 11 made of silicon/silicon dioxide;
step 2: ultrasonically cleaning the substrate layer 11 in acetone and isopropanol for 5min respectively;
and step 3: mixing molybdenum oxide and sodium chloride according to the mass ratio of about 6:1 to form a molybdenum source precursor; taking 255mg of sulfur powder as a sulfur source precursor;
and 4, step 4: placing the molybdenum source precursor in the center of a 1-inch tubular furnace in a single-temperature area, and placing a sulfur source precursor at the upstream of the molybdenum source precursor, wherein the distance between the molybdenum source and the sulfur source precursor is about 23 cm;
and 5: placing the substrate layers 11 face to face at the downstream of the molybdenum source precursor, wherein the vertical distance between the substrate layers 11 is about 2 mm;
step 6: exhausting residual gas in the tube furnace by using high-purity argon-hydrogen mixed gas, wherein the exhausting time is about 10 min;
step 7, pumping the vacuum pump for the tube furnace to low pressure, wherein the pressure is about 0.4 Torr;
and 8: respectively introducing argon gas at 32-48sccm and hydrogen gas at 4-6sccm into the quartz tube;
and step 9: raising the temperature of the tubular furnace to 680-780 ℃, wherein the temperature raising rate is 50 ℃/min; when the temperature of the tubular furnace is increased to 670 ℃, the sulfur powder is increased to 180-250 ℃ by a heating belt;
step 10: keeping the tubular furnace at the constant temperature of 680-780 ℃ for half an hour to obtain a sample;
step 11: the tube furnace is moved away, the sample is naturally cooled to the room temperature, and the channel layer 12 is prepared on the substrate layer 11;
step 12: preparing the electrode layer 13 on the channel layer 12 by electron beam evaporation;
step 13: and obtaining the artificial synapse transistor unit device.
EXAMPLE III
Further, in the second comparative example, the parameter setting in step 12 is modified in the third embodiment, specifically, the array of electrode layers 13 is prepared on the channel layer 12 by using electron beam evaporation.
Example four
Further, in a third comparative example, the parameter settings in step 3 in the fourth example are modified, specifically, molybdenum oxide and sodium chloride are mixed according to a mass ratio of about 6:1, so as to form a molybdenum source precursor; 255mg of selenium powder is used as a sulfur source precursor.
EXAMPLE five
Further, in a third comparative example, in the fifth embodiment, parameter settings are modified in step 11, specifically, the tube furnace is removed, the sample is naturally cooled to room temperature, the channel layer 12 is prepared on the substrate layer 11, and the channel layer 12 is transferred to flexible bottom-sinking PET with one surface coated with ITO.
EXAMPLE six
Further, in a fifth comparative example, parameter settings in step 11 are modified in a sixth example, specifically, the tube furnace is removed, the sample is naturally cooled to room temperature, the channel layer 12 is prepared on the substrate layer 11, and the channel layer 12 is transferred to flexible bottom-sinking PET, one surface of which is covered with ITO and fixed to a curved surface.
EXAMPLE seven
Further, in a third comparative example, the parameter setting in step 10 of the seventh embodiment is modified, specifically, the tube furnace is kept at a constant temperature of 680-780 ℃ for 35min, so as to obtain a sample.
Example eight
Further, in a third comparative example, in the eighth example, the parameter settings are modified in step 10, specifically, the tube furnace is kept at a constant temperature of 700 ℃ for 35min, so as to obtain a sample.
Example nine
When the artificial synapse transistor array obtained in example two is tested, under the bias voltage of +1V of source and drain, the dark current is below 2nA, and under the irradiation of 405nm laser, the photocurrent is about four orders of magnitude higher than the dark current. The range of light detection is from visible light to near infrared. As in table 1, the optical response of the device under stimulation by a single optical pulse of different pulse widths was tested and its power consumption was calculated. The response speed of the device to a single optical pulse is as low as 5 mus, the power consumption is about 40aJ, and the power consumption is far lower than that of biological synapses by 50ms and 10 fJ. The negative grid voltage can enhance the light response, and the positive grid voltage can weaken the light response, and can be used for simulating the influence of emotion on the human brain memory function. Meanwhile, the device can simulate a classical pavlov experiment and can be used for simulating the associative learning ability of human brain. These results show that the molybdenum disulfide-based artificial synapse transistor array provided by the invention can simulate biological synapses related to human vision and brain storage, and has an ultra-fast single optical pulse response speed, ultra-low power consumption and a widened visual range.
Table 1 power consumption at different individual optical pulse widths in example two
Figure BDA0003042569330000121
The specific unit is as follows: nJ 10 (-9) J pJ 10 (-12) J fJ 10 (-15) J10 (-18) J
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and these modifications and adaptations should be considered within the scope of the invention.

Claims (10)

1. An artificial synapse transistor array is characterized in that a substrate layer, a channel layer and an electrode layer are sequentially arranged from bottom to top.
2. The array of artificial synapse transistors of claim 1, wherein the substrate layer is made of silicon and silicon dioxide, wherein the silicon dioxide is used as a gate oxide layer and the silicon is used as a back gate, and the silicon dioxide is prepared by magnetron sputtering with a thickness of 285nm, which is easy for subsequent channel layer growth and is a suitable gate oxide layer thickness that is not easily broken down by gate voltage. And the back gate structure device is simpler to prepare.
3. The array of artificial synapse transistors of claim 1, wherein the channel layer material is molybdenum disulfide.
4. The array of artificial synapse transistors of claim 1, wherein the channel layer is fabricated by chemical vapor deposition.
5. The array of artificial synapse transistors of claim 4, wherein the chemical vapor deposition process comprises:
ultrasonically cleaning the substrate layer in acetone and isopropanol for 5min respectively;
mixing molybdenum oxide and sodium chloride according to a mass ratio of about 6:1 to form a molybdenum source precursor;
taking 255 parts of sulfur powder as a sulfur source precursor according to the mass parts;
then placing the molybdenum source precursor in the center of a 1-inch tubular furnace with a single temperature zone, and placing a sulfur source precursor at the upstream of the molybdenum source precursor, wherein the distance between the molybdenum source and the sulfur source precursor is about 23 cm;
then placing the substrate layers at the downstream of the molybdenum source precursor in a face-to-face manner, wherein the vertical distance between the substrate layers is about 2 mm;
exhausting residual gas in the tube furnace by using high-purity argon-hydrogen mixed gas, wherein the exhausting time is about 10 min;
pumping the vacuum pump for the tube furnace to low pressure, wherein the pressure is about 0.4 Torr;
respectively introducing argon gas at 32-48sccm and hydrogen gas at 4-6sccm into the quartz tube;
then the tube furnace is heated to the growth temperature of 680-780 ℃, wherein the heating rate is 50 ℃/min;
when the temperature of the tubular furnace is raised to 1.5min before the growth temperature, the sulfur powder is raised to 180-250 ℃ by a heating belt;
keeping the tube furnace at the growth temperature for half an hour at constant temperature to obtain a sample;
finally, the tube furnace is removed, and the sample is naturally cooled to room temperature.
6. The array of artificial synapse transistors of claim 1, wherein the electrode layer is grown by UV lithography and electron beam evaporation, wherein the electrode layer is made of titanium and gold, wherein the thickness of titanium is 5-10nm, and the thickness of gold is 50-100 nm.
7. The array of artificial synapse transistors of claim 1, wherein the electrode layer is formed by lift-off, and the stripping solution is acetone.
8. The array of artificial synapse transistors of claim 1, wherein the electrode layer is arranged in an array on the channel layer.
9. The method of any one of claims 1-8, wherein: the regulation and control method comprises the following steps:
(1) laser irradiation is carried out between electrodes of an artificial synapse transistor array, and the laser wavelengths are respectively 405, 520, 635,800 and 850 nm; the artificial synapse transistor array in the state is adopted to simulate the recognition of human eyes to visible light, and the visual boundary of the human eyes is expanded to near infrared light;
(2) gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; simulating the response of biological synapses to ultrashort light pulses by using the artificial synapse transistor array in the state;
(3) gradually decreasing the pulse width from 1s to 5 μ s by shining a single light pulse of different pulse widths between the electrodes of the array of artificial synapse transistors; adopting the artificial synapse transistor array in the state to simulate the power consumption of biological synapses on the ultra-short light pulse events;
(4) by shining a single light pulse of varying power between the electrodes of the array of artificial synapse transistors, the power is from 27.7mW/cm2Gradually reduced to 1mW/cm2(ii) a Adopting the artificial synapse transistor array in the state to simulate the response of human eyes to different light intensities;
(5) irradiating double light pulses with the same intensity and different intervals and time between the electrodes of the artificial synapse transistor array, wherein the interval is gradually reduced from 16s to 0.3 s; simulating double-pulse facilitation of biological synapses by adopting the artificial synapse transistor array in the state;
(6) gradually increasing the number of pulses from 10 to 100 by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain;
(7) gradually increasing the pulse frequency from 0.2Hz to 5Hz by shining successive pulses of light between the electrodes of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the long-term memory function and the forgetting curve of the human brain;
(8) inputting optical pulse, electric pulse, input optical electric pulse and input electric pulse only between the electrodes of the artificial synapse transistor array; adopting the artificial synapse transistor array in the state to simulate the associative learning function of the human brain;
(9) applying a voltage from a negative voltage to a positive voltage by applying a voltage to the substrate silicon of the array of artificial synapse transistors; the artificial synapse transistor array in the state is adopted to simulate the influence of negative emotion and positive emotion on the human brain memory function;
(10) by performing single and multiple letter identification on the artificial synapse transistor array; simulating neuro-visual imaging using the array of artificial synapse transistors in this state;
(11) sequentially identifying different images by carrying out different image identification on the artificial synapse transistor array; the artificial synapse transistor array in the state is adopted to simulate addition and subtraction calculation of a logic circuit.
10. Use of the artificial synapse transistor array of any one of claims 1-8 for simulating biological synapses for visual recognition and brain memory.
CN202110461811.1A 2021-04-27 2021-04-27 Artificial synapse transistor array and regulation and control method and application thereof Active CN113241387B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110461811.1A CN113241387B (en) 2021-04-27 2021-04-27 Artificial synapse transistor array and regulation and control method and application thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110461811.1A CN113241387B (en) 2021-04-27 2021-04-27 Artificial synapse transistor array and regulation and control method and application thereof

Publications (2)

Publication Number Publication Date
CN113241387A true CN113241387A (en) 2021-08-10
CN113241387B CN113241387B (en) 2023-07-28

Family

ID=77129606

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110461811.1A Active CN113241387B (en) 2021-04-27 2021-04-27 Artificial synapse transistor array and regulation and control method and application thereof

Country Status (1)

Country Link
CN (1) CN113241387B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620665B1 (en) * 2015-06-17 2017-04-11 The United States Of America As Represented By The Secretary Of The Army Method for improved growth of two-dimensional transition metal dichalcogenides
CN109023298A (en) * 2018-08-21 2018-12-18 清华-伯克利深圳学院筹备办公室 A kind of transient metal doped molybdenum disulfide layer material and its preparation method and application
CN109900750A (en) * 2019-04-04 2019-06-18 中国计量大学 A kind of improve is based on MoS2The structure of thin film transistor formula gas sensitivity designs
CN111525027A (en) * 2020-03-02 2020-08-11 中国科学院宁波材料技术与工程研究所 Method for reversibly regulating and controlling conductance of memristor by using optical signal
US20210098611A1 (en) * 2019-10-01 2021-04-01 Northwestern University Dual-gated memtransistor crossbar array, fabricating methods and applications of same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9620665B1 (en) * 2015-06-17 2017-04-11 The United States Of America As Represented By The Secretary Of The Army Method for improved growth of two-dimensional transition metal dichalcogenides
CN109023298A (en) * 2018-08-21 2018-12-18 清华-伯克利深圳学院筹备办公室 A kind of transient metal doped molybdenum disulfide layer material and its preparation method and application
CN109900750A (en) * 2019-04-04 2019-06-18 中国计量大学 A kind of improve is based on MoS2The structure of thin film transistor formula gas sensitivity designs
US20210098611A1 (en) * 2019-10-01 2021-04-01 Northwestern University Dual-gated memtransistor crossbar array, fabricating methods and applications of same
CN111525027A (en) * 2020-03-02 2020-08-11 中国科学院宁波材料技术与工程研究所 Method for reversibly regulating and controlling conductance of memristor by using optical signal

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
VINOD K. SANGWAN等: ""Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide"", 《NATURE》 *
马可: ""基于晶体管人工突触的光电调控的研究"", 《中国优秀博硕士学位论文全文数据库(硕士)信息科技辑》 *

Also Published As

Publication number Publication date
CN113241387B (en) 2023-07-28

Similar Documents

Publication Publication Date Title
Zhou et al. Optoelectronic resistive random access memory for neuromorphic vision sensors
Kim et al. Vertically aligned two-dimensional halide perovskites for reliably operable artificial synapses
Chen et al. Optoelectronic artificial synapses based on β-Ga2O3 films by RF magnetron sputtering
Li et al. Photonic synapses with ultralow energy consumption for artificial visual perception and brain storage
Li et al. CsPbBr3/graphene nanowall artificial optoelectronic synapses for controllable perceptual learning
CN111192938B (en) Preparation and modulation method of photoelectric synapse device
CN113161494B (en) Preparation method of photoelectric artificial synapse and photoelectric artificial synapse
Chung et al. Visible light-driven indium-gallium-zinc-oxide optoelectronic synaptic transistor with defect engineering for neuromorphic computing system and artificial intelligence
Mizuno et al. Optoelectronic synapses using vertically aligned graphene/diamond heterojunctions
Shang et al. ZnO photoconductive synaptic devices for neuromorphic computing
Guo et al. High-performance artificial synapse based on CVD-grown WSe2 flakes with intrinsic defects
CN111834530A (en) Two-end artificial synapse based on single crystal perovskite and preparation method thereof
CN113241387B (en) Artificial synapse transistor array and regulation and control method and application thereof
Dang et al. Ferroelectric Modulation of ReS2‐Based Multifunctional Optoelectronic Neuromorphic Devices for Wavelength‐Selective Artificial Visual System
Wang et al. Tailoring Classical Conditioning Behavior in TiO2 Nanowires: ZnO QDs-Based Optoelectronic Memristors for Neuromorphic Hardware
Zhang et al. A perovskite-based artificial photonic synapse with visible light modulation and ultralow current for neuromorphic computing
Wang et al. Operant conditioning reflex implementation in a transparent Ta2O5–3x/Ta2O5− x homo-structured optoelectronic memristor for neuromorphic computing application
CN116157004A (en) Memristor based on titanium trisulfide/titanium dioxide/titanium trisulfide transverse heterojunction and preparation method and application thereof
Ni et al. E-Synapse Based on Lead-Free Organic Halide Perovskite (CH 3 NH 3) 3 Sb 2 Cl 9 for Neuromorphic Computing
CN115117177A (en) Neuromorphic photoelectric sensor and preparation and regulation method thereof
Jo et al. Flexible Photonic Synapses Using Vertical ZnO Nanotubes on Graphene Films
CN111769194B (en) Flexible photoelectric sensing memristor based on sawtooth structure nanowire
Fu et al. High-performance IGZO/In2O3 NW/IGZO phototransistor with heterojunctions architecture for image processing and neuromorphic computing
Chen et al. Humidity-dependent synaptic characteristics in gelatin-based organic transistors
KR20190001647A (en) Microelectrode array chip capable of photothermal stimulation and control method of nerve cell using the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant