CN113241370B - Ferroelectric doping based tunneling field effect transistor and preparation method thereof - Google Patents

Ferroelectric doping based tunneling field effect transistor and preparation method thereof Download PDF

Info

Publication number
CN113241370B
CN113241370B CN202110501010.3A CN202110501010A CN113241370B CN 113241370 B CN113241370 B CN 113241370B CN 202110501010 A CN202110501010 A CN 202110501010A CN 113241370 B CN113241370 B CN 113241370B
Authority
CN
China
Prior art keywords
polarization
layer
electrode
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110501010.3A
Other languages
Chinese (zh)
Other versions
CN113241370A (en
Inventor
刘艳
闫钦元
周久人
韩根全
郝跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202110501010.3A priority Critical patent/CN113241370B/en
Publication of CN113241370A publication Critical patent/CN113241370A/en
Application granted granted Critical
Publication of CN113241370B publication Critical patent/CN113241370B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nanotechnology (AREA)
  • Thin Film Transistor (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention discloses a tunneling field effect transistor based on ferroelectric doping and a preparation method thereof, and mainly solves the problems of uneven impurity concentration, large switching current ratio and sub-threshold swing and high power consumption of the conventional device. It includes: the field emission display device comprises a substrate (1), an oxidation layer (2) and a channel layer (3), wherein a drain electrode (11) and a source electrode (12) are respectively arranged on two sides of the channel layer, a source electrode polarization grid (6) made of ferroelectric materials, a control insulation medium grid (4) and a drain electrode polarization grid (5) made of ferroelectric materials are sequentially arranged above the channel layer, isolation insulation media (7) are arranged on two sides of the source electrode polarization grid and the drain electrode polarization grid, a source electrode polarization electrode (8) is arranged above the source electrode polarization grid, a control grid electrode (9) is arranged above the control medium grid, and a drain electrode polarization electrode (10) is arranged above the drain electrode polarization grid. The invention utilizes the ferroelectric polarization properties of the drain electrode polarization grid and the source electrode polarization grid to realize the accurate control of the carrier concentration of the source drain doped region and improve the overall performance of the device.

Description

Tunneling field effect transistor based on ferroelectric doping and preparation method thereof
Technical Field
The invention belongs to the field of microelectronic devices, and particularly relates to a tunneling field effect transistor which can be used for manufacturing a next-generation low-power-consumption large-scale integrated circuit.
Background
With the development of integrated circuits, the size of a basic MOS transistor is continuously reduced, and excessive power consumption becomes an important factor restricting the development of integrated circuits. Therefore, the search for a new structure transistor continues to push the continuation of moore's law as one of the important hot topics in the field of integrated circuit research. The Tunneling Field Effect Transistor (TFET) is used as a novel physical device structure, the conduction of current between a source and a drain is realized through the principle of carrier band-to-band tunneling, and the low power consumption and the low sub-threshold swing can be still kept under the small size. TFETs hold great promise for the next generation of new devices.
At present, the TFET carries out N-type and P-type heavy doping at a source end and a drain end, so that the source end, a channel and the drain end can form a step shape. Under the requirement of a large-scale integrated circuit, ions can be diffused to a channel by doping the source and drain regions in a conventional doping mode, and the size reduction of a device is limited. As shown in fig. 1, the gate of the device is sequentially divided into three regions, namely a left polarization gate PG1, a control gate CG and a right polarization gate PG2, the channel is sequentially divided into a source, a source region, a channel region, a drain region and a drain from left to right, PG1 and PG2 are both conventional metal-oxide-semiconductor gate structures, positive voltage and negative voltage are continuously applied to PG1 and PG2 respectively in the structure, the channel layer controlled by PG1 accumulates high-concentration holes to form the source region, and the channel layer controlled by PG2 accumulates high-concentration electrons to form the drain region, so that the basic functional structure of the tunneling transistor is realized. Although this structure can solve the problem of ion doping diffusion, it needs to apply a constant voltage to PG1 and PG2, and the voltage fluctuation inevitably reduces the stability of the device and greatly increases the power consumption of the device.
Disclosure of Invention
The invention aims to provide a field effect tunneling transistor based on ferroelectric doping and a preparation method thereof aiming at the defects of the prior art, so that the concentration of current carriers is accurately and uniformly controlled by changing the doping mode, the working stability and the durability of the tunneling field effect transistor are improved, the power consumption and the subthreshold swing of a device are reduced, and the performance of the device is improved.
To achieve the above object, the present invention is based on a ferroelectric doped field effect tunneling transistor comprising, from bottom to top: the nano-channel structure comprises a substrate, an oxide layer and a nano-channel layer, wherein a drain electrode and a source electrode are respectively arranged on two sides of the channel layer, a source electrode polarization grid, a control insulation medium grid and a drain electrode polarization grid are sequentially arranged above the channel layer, isolation insulation media are arranged on two sides of the source electrode polarization grid and the drain electrode polarization grid, a drain electrode polarization electrode is arranged above the drain electrode polarization grid, a control grid electrode is arranged above the control medium grid, and a source electrode polarization electrode is arranged above the source electrode polarization grid, and the nano-channel structure is characterized in that:
the thickness of the channel layer is 5nm to 10 nm;
the source electrode polarization gate and the drain electrode polarization gate adopt any ferroelectric material with polarization property to realize the control of doping concentration of the channel layer with nanometer size under the excitation of pulses with different amplitudes, increase the change of the concentration gradient of carriers in the doping region and the channel region of the control gate and inhibit the diffusion of the carriers in the source electrode doping region to the channel.
Further, the ferroelectric material with polarization property comprises HZO and Al2O3、HfO2、ZrO2、BaTiO3、Cd2Nb2O7、BiFeO3、SBT、ZnSnO3And PVDF.
Furthermore, the channel is made of any one of Si, Ge, SiGe, GaN, GaAs and two-dimensional materials.
Further, the substrate is made of any one of Si, Ge, SiC, GaN, sapphire and diamond materials.
Further, the oxidation adopts SiO2Any one of borosilicate glass and BPSG.
Furthermore, the thickness of the drain electrode polarization grid and the source electrode polarization grid is 1 nm-40 nm, the distance between the drain electrode polarization grid electrode and the control grid electrode is 0-5 nm, and the distance between the source electrode polarization grid electrode and the control grid electrode is 0-8 nm.
In order to achieve the above object, the present invention provides a method for preparing a field effect tunneling transistor based on ferroelectric doping, which comprises the following steps:
1) selecting a substrate consisting of a substrate, an insulating oxide layer and a channel layer in sequence;
2) etching the thickness of the channel layer to 5 nm-10 nm by using an etching process;
3) growing a SiO2 medium layer with the thickness of 2-5 nm on the upper surface of the nanometer channel layer of the SOI substrate by utilizing a chemical vapor deposition process;
4) by etching process, SiO on the left and right sides of the symmetry axis of the substrate2Etching two same grooves with the width of 5-15 nm on the layer to form a control insulated dielectric gate;
5) depositing a ferroelectric material, i.e. tetrakis (dimethylamino) zirconium or HfCl, in two trenches on the upper surface of the substrate using an atomic layer deposition process4Or TEMAHf or TEMAZr or other ferroelectric elements as precursor sources, H2O or O3As precursor oxygen source, with N2As a purge gas, reacting and depositing at the temperature of 250-500 ℃ to form a ferroelectric layer with the thickness of 3-11 nm;
6) etching and removing the ferroelectric layer outside the groove by using an etching process to respectively form a drain electrode polarization gate and a source electrode polarization gate;
7) growing metal on the upper surfaces of the polarization gate and the control gate by using a reactive sputtering process to form a polarization gate electrode layer;
8) etching the polarized gate electrode layer and SiO at the edge of the substrate2Etching away the layer and the channel layer to form an isolation insulating medium layer;
9) performing metal sputtering on the surface of the etched sample by using a reactive sputtering process to form a contact electrode layer;
10) etching the contact electrode layer above the polarized gate electrode layer by using an etching process, and etching the gate electrode layer metal above the contact of the polarized gate and the control gate insulating medium to form a control gate electrode;
11) and etching the metal above the isolation insulated gate dielectric by using an etching process to form a source electrode, a drain electrode polarized electrode, a source electrode polarized electrode and a drain electrode in sequence from left to right, thereby finishing the manufacture of the whole device.
Compared with the prior art, the invention has the following advantages:
firstly, the invention can complete the doping of the target region by changing the materials of the drain electrode polarization gate and the source electrode polarization gate and applying pulses to the polarization gates, compared with the traditional electrostatic doping tunneling field effect transistor, avoids the need of applying continuous and stable voltage in the doping process, can inhibit the carrier concentration fluctuation of the source and drain regions, improves the working stability of the device, reduces the energy consumption required by the doping, and prolongs the working life of the device.
Secondly, the doping concentration of the source and drain regions is accurately controlled through pulses, the carrier concentration gradient of the source and drain regions and the channel region is increased, the control capability of a control grid on a channel can be further enhanced, the on-off current ratio is increased, the power consumption and the sub-threshold swing amplitude of the device during working are reduced, and the performance of the device is improved.
Drawings
FIG. 1 is a diagram of a conventional ESD-doped tunneling field effect transistor;
FIG. 2 is a block diagram of a ferroelectric doped tunneling field effect transistor based on the present invention;
fig. 3 is a schematic diagram of the process for manufacturing the tunneling field effect transistor based on ferroelectric doping according to the present invention.
Detailed Description
Referring to fig. 2, a ferroelectric doped based tunneling field effect transistor, comprising from bottom to top: the substrate 1, the oxide layer 2 and the channel layer 3 are respectively a drain electrode 11 and a source electrode 12 which are positioned on two sides of the channel layer, a source electrode polarization gate 6, a control insulation medium gate 4 and a drain electrode polarization gate 5 are sequentially arranged above the channel layer, an isolation insulation medium 7 is arranged on two sides of the source electrode polarization gate 6 and the drain electrode polarization gate 5, a source electrode polarization electrode 8 is arranged above the source electrode polarization gate 6, a control gate electrode 9 is arranged above the control insulation medium gate 4, and a drain electrode polarization electrode 10 is arranged above the drain electrode polarization gate 5. Wherein, the substrate layer 1 adopts any one of Si, Ge, SiC, GaN, sapphire and diamond; the oxide layer 2 adopts SiO2BPSG, borosilicate glass; the channel layer 3 is made of any one of Si, Ge, SiGe, GaN and GaO semiconductor materials, and the thickness of the channel layer is 5 nm-10 nm; the control insulated gate dielectric layer adopts SiO2、Si3N4、Ta2O5、TiO2One of them, the thickness range is 2-5 nm; the source electrode polarization grid 6 and the drain electrode polarization grid 5 are both adoptedA ferroelectric material with polarization property comprises HZO and Al2O3、HfO2、ZrO2、BaTiO3、Cd2Nb2O7、BiFeO3、SBT、ZnSnO3PVDF (polyvinylidene fluoride), the thickness of which is 3-11nm, wherein asymmetric electric dipoles contained in unit cells of the material are directionally inverted under the action of an external electric field, and the material can keep the directional inversion characteristic after the electric field is removed, the characteristic can generate quantitative polarization charges on the surface of the material, namely, before the polarization degree of the material reaches the saturation polarization strength, the density of the surface polarization charges is in direct proportion to the applied voltage, so that pulse excitation with different amplitudes is applied to a source electrode polarization gate 6 and a drain electrode polarization gate 5, the doping concentration of a channel layer 3 can be accurately controlled, the change of the carrier concentration gradient of a doping region and a control gate channel region is increased, and the diffusion of carriers of the source electrode doping region and the drain electrode doping region to a channel is inhibited; the drain electrode 11, the source electrode 12, the source polarization electrode 8, the control gate electrode 9 and the drain polarization electrode 10 are made of any one of metal tungsten, metal titanium, metal copper, metal aluminum, metal platinum, metal iridium, metal ruthenium, tungsten nitride, titanium nitride, tantalum nitride, iridium oxide, ruthenium oxide, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide and tantalum silicide.
When the device works, a negative pulse is applied to the source polarized gate electrode 8, a positive polarized pulse is applied to the drain polarized gate electrode 10, a channel layer below the source polarized gate 6 is doped with high-concentration holes, and a high-concentration electron is doped below the drain polarized gate 5, so that the function of a tunneling field effect transistor is realized.
Referring to fig. 3, the present invention presents three embodiments of fabricating a field effect tunneling transistor based on ferroelectric doping:
example 1: making Hf-based on Si substrate0.5Zr0.5O2A ferroelectric material doped silicon channel tunneling field effect transistor.
Step 1: the substrate is selected and the trench etched.
Si is selected as the substrate 1 and SiO in sequence2As an SOI substrate consisting of the insulating oxide layer 2 and Si as the channel layer 3, and etching the channel layer to 7nm using an etching process, as shown in fig. 3 (a).
Step 2: and depositing a control insulated gate dielectric layer.
Placing the etched SOI substrate into a reaction cavity, utilizing a chemical vapor deposition process, firstly extracting vacuum for 5-15 minutes in the reaction cavity, and then simultaneously introducing Si3H4And N2Taking O as a silicon source and an oxygen source, taking 75 ℃ as reaction temperature, and forming SiO with the thickness of 8nm on the surface of the SOI by inductive coupling growth2As a control insulated gate dielectric layer, fig. 3(b) is shown.
And step 3: and etching the grooves on two sides of the control polarization dielectric gate.
By etching process, SiO on the left and right sides of the symmetry axis of the SOI substrate2Two identical trenches 8nm wide are etched in the layer to form the control insulated dielectric gate 4, as shown in fig. 3 (c).
And 4, step 4: a polarized ferroelectric layer is deposited.
By utilizing an atomic layer deposition process, TEMAHf is taken as a precursor hafnium source, TEMAZr is taken as a precursor zirconium source, and O is3As a precursor oxygen source, with N2As a purge gas, an 8nm thick HZO ferroelectric layer was formed on the trench at 260 ℃ as a reaction temperature, and then the SOI substrate was annealed at 500 ℃ for 30min to form a polarization gate, and a source polarization gate 6 and a drain polarization gate 5 were formed from left to right, respectively, as shown in fig. 3 (d).
And 5: a layer of a gated electrode metal is deposited.
By using a reactive sputtering process, firstly, a molecular pump and a cold pump are used for vacuumizing a reaction cavity until the vacuum pressure is 8E-6Torr, and then, under the conditions of 350W of power and 5mTorr of Ar pressure, Al is used as a target material for sputtering the surface of the HZO polarization grid to form an Al polarization electrode layer, as shown in figure 3 (E).
Step 6: and etching the source drain metal electrode groove.
At the edge of the substratePolarized gate electrode Al layer, SiO2The layer and the Si channel layer are etched away to form the isolation insulating dielectric 7 and the source drain electrode metal trenches, as shown in fig. 3 (f).
And 7: and depositing a contact electrode metal layer.
By using a reactive sputtering process, firstly, a molecular pump and a cold pump are used for vacuumizing a reaction cavity until the vacuum pressure is 8E-6Torr, and then Cu is used as a target material for sputtering the surface of a sample under the conditions of 350W power and 5mTorr Ar pressure to form a Cu electrode as a contact electrode layer, as shown in figure 3 (g).
And 8: and etching to form a source/drain electrode, a source/drain polarized gate electrode and a control gate electrode.
8.1) etching away the contact electrode layer above the gated electrode layer;
8.2) etching the metal of the Al gate electrode layer above the contact of the polarization gate and the control gate insulating medium to form a control gate electrode 10;
8.3) SiO2The gate electrode metal above the isolated insulated gate dielectric is etched away to form the source 12, drain polarized electrode 8, source polarized electrode 9 and drain 11 from left to right as shown in fig. 3(h), completing the device fabrication.
Example 2: manufacturing method based on HfO on SiC substrate2The ferroelectric material is doped with a SiGe channel tunneling field effect transistor.
The method comprises the following steps: the substrate is selected and the trench etched.
A SiGeOI substrate composed of SiC as the substrate 1, BPSG as the insulating oxide layer 2, and SiGe as the channel layer 3 in this order was selected, and the channel layer was etched to 9nm by an etching process, as shown in fig. 3 (a).
Step two: and depositing a control insulated gate dielectric layer.
Placing the etched SiGeOI substrate into a reaction cavity, utilizing a chemical vapor deposition process, firstly pumping vacuum for 5-15 minutes into the reaction cavity, and then simultaneously introducing Si3H4And N2And O is used as a silicon source and an oxygen source, 75 ℃ is used as a reaction temperature, and SiO2 with the thickness of 10nm is formed on the surface of the SiGeOI in an inductively coupled growth mode and is used as a control insulated gate dielectric layer, as shown in figure 3 (b).
Step three: and etching the grooves on two sides of the control polarization dielectric gate.
By etching process, SiO on the left and right sides of the symmetry axis of the SiGeOI substrate2Two identical trenches 11nm wide are etched in the layer to form the control insulated dielectric gate 4, as shown in figure 3 (c).
Step four: a polarized ferroelectric layer is deposited.
Using an atomic layer deposition process with HfCl4H2O as precursor oxygen source and N as precursor hafnium source2As a purge gas, 300 ℃ is used as a reaction temperature to deposit and form HfO with the thickness of 10nm on the surface of the SiGeOI2The ferroelectric layer is used as a polarization gate, and a source polarization gate 6 and a drain polarization gate 5 are formed from left to right, respectively, as shown in fig. 3 (d).
Step five: a layer of a gated electrode metal is deposited.
By using a reactive sputtering process, firstly, a molecular pump and a cold pump are used for vacuumizing a reaction cavity until the vacuum pressure is 8E-6Torr, and then W is used as a target material to sputter the surface of the HZO polarization grid under the conditions that the power is 350W and the Ar pressure is 5mTorr, so as to form a W polarization electrode layer, as shown in figure 3 (E).
Step six: and etching the source drain metal electrode groove.
The polarized gate electrode W layer, BPSG layer and Si channel layer at the edge of the substrate are etched away to form an isolation insulating dielectric 7 and source and drain electrode metal trenches, as shown in fig. 3 (f).
Step seven: and depositing a contact electrode metal layer.
7.1) utilizing a reactive sputtering process, firstly, vacuumizing a reaction cavity by using a molecular pump and a cold pump until the vacuum pressure is 8E-6Torr,
7.2) sputtering the sample surface by using Au as a target under the conditions of 350W of power and 5mTorr of Ar pressure to form an Au electrode as a contact electrode, as shown in figure 3 (g).
Step eight: and etching to form a source/drain electrode, a source/drain polarized gate electrode and a control gate electrode.
The specific implementation of this step is the same as step 6 of example 1.
Example 3: production of ZrO-based on Ge substrate2The ferroelectric material is doped with Ge channel tunneling field effect transistor.
Step A: the substrate is selected and the trench etched.
A GOI substrate consisting of Ge as a substrate 1, borosilicate glass as an insulating oxide layer 2, and Ge as a channel layer 3 in this order was selected, and the channel layer was etched to 8nm using an etching process, as shown in fig. 3 (a).
And B: and depositing a control insulated gate dielectric layer.
Placing the etched GOI substrate into a reaction cavity, utilizing a chemical vapor deposition process, firstly extracting vacuum for 10 minutes from the reaction cavity, and then simultaneously introducing Si3H4And N2Taking O as a silicon source and an oxygen source, taking 75 ℃ as a reaction temperature, and forming SiO with the thickness of 7nm on the surface of GOI by inductive coupling growth2As a control insulated gate dielectric layer, fig. 3(b) is shown.
And C: and etching the grooves on two sides of the control polarization dielectric gate.
By utilizing etching process, SiO on the left side and the right side of the symmetry axis of the GOI substrate2Two identical trenches 10nm wide are etched in the layer to form the control insulated dielectric gate 4, as shown in fig. 3 (c).
Step D: a polarized ferroelectric layer is deposited.
With tetrakis (dimethylamino) zirconium as the precursor zirconium source, H2O or O3As a precursor oxygen source, with N2As a purge gas, a 7nm thick ZrO2 ferroelectric layer was deposited on the GOI surface as a polarization gate at 250 ℃ as a reaction temperature, and a source polarization gate 6 and a drain polarization gate 5 were formed from left to right, respectively, as shown in fig. 3 (d).
Step E: a layer of a gated electrode metal is deposited.
By utilizing a reactive sputtering process, firstly, a molecular pump and a cold pump are used for vacuumizing a reaction cavity until the vacuum pressure is 8E-6Torr, and then Ta is used as a target material to sputter the surface of the ZrO2 polarization grid under the conditions that the power is 350W and the Ar pressure is 5mTorr, so as to form a TaN polarization electrode layer, as shown in figure 3 (E).
Step F: and etching the source drain metal electrode groove.
The polarized gate electrode TaN layer, borosilicate glass layer and Si channel layer at the edge of the substrate are etched away to form an isolation insulating medium 7 and a source drain electrode metal trench, as shown in fig. 3 (f).
Step G: and depositing a contact electrode metal layer.
G1) By utilizing a reactive sputtering process, firstly, a molecular pump and a cold pump are used for vacuumizing a reaction cavity until the vacuum pressure is 8E-6Torr,
G2) the sample surface was sputtered using Cu as a target at a power of 350W and an Ar pressure of 5mTorr to form a Cu electrode as a contact electrode, as shown in fig. 3 (g).
Step H: and etching to form a source/drain electrode, a source/drain polarized gate electrode and a control gate electrode.
The specific implementation of this step is the same as step 6 of example 1, and the device fabrication is completed.
The above description is only three preferred embodiments of the present invention and should not be construed as limiting the invention in any way. It will be apparent to those skilled in the art that several modifications and finishes can be made without departing from the principles of the invention, for example, substrates including sapphire substrate materials in addition to Si, Ge and SiC are given in this example; the channel comprises GaN, GaAs and two-dimensional channel materials besides the Si, Ge and SiGe provided by the embodiment; the polarization grid is made of HZO and HfO as shown in the present example2And ZrO2Ferroelectric material, further comprising Al2O3、BaTiO3、Cd2Nb2O7、BiFeO3、SBT、PZT、ZnSnO3And a PVDF ferroelectric material; device process structures other than the planar processes presented in this example include the use of ferroelectric tunneling field effect transistors in the Nanowire, nanoshiet and FinFET type structures, and such modifications and refinements are considered to be within the scope of the present invention.

Claims (9)

1. A ferroelectric doping based tunneling field effect transistor comprising from bottom to top: substrate (1), oxide layer (2) and channel layer (3), this channel layer both sides are drain electrode (11) and source electrode (12) respectively, this channel layer top is source polarization bars (6), control insulating medium bars (4), drain electrode polarization bars (5) from left right side in proper order, source polarization bars (6) and drain electrode polarization bars (5) both sides are for keeping apart insulating medium (7), be source polarization gate electrode (8) above source polarization bars (6), control insulating medium bars (4) top is control gate electrode (9), drain electrode polarization gate electrode (5) top is drain electrode polarization gate electrode (10), its characterized in that:
the thickness of the channel layer (3) is 5 nm-10 nm;
the source electrode polarization grid (6) and the drain electrode polarization grid (5) adopt any ferroelectric material with polarization property to realize the control of doping concentration of the channel layer with nanometer size under the excitation of pulses with different amplitudes, increase the change of the concentration gradient of carriers in the doping area and the channel area of the control grid and inhibit the diffusion of the carriers in the source electrode doping area to the channel.
2. The tunneling field effect transistor according to claim 1, wherein the ferroelectric material with polarization properties comprises HZO, Al2O3、HfO2、ZrO2、BaTiO3、Cd2Nb2O7、BiFeO3、SBT、PZT、ZnSnO3And PVDF.
3. A tunneling field effect transistor according to claim 1, characterized in that the channel layer (3) is made of any one of Si, Ge, SiGe, GaN, GaAs, two-dimensional materials.
4. The tunneling field effect transistor according to claim 1, wherein the thickness of the drain polarization gate and the source polarization gate ranges from 1nm to 40nm, the distance between the source polarization gate electrode (8) and the control gate electrode (9) ranges from 0nm to 5nm, and the distance between the drain polarization gate electrode (10) and the control gate electrode (9) ranges from 0nm to 8 nm.
5. A tunneling field effect transistor according to claim 1, characterized in that said substrate (1) is of any of Si, Ge, SiC, sapphire material.
6. The tunneling field effect transistor according to claim 1, wherein the oxide layer (2) is made of SiO2Any one of borosilicate glass and BPSG.
7. A preparation method of a tunneling field effect transistor based on ferroelectric doping is characterized by comprising the following steps:
1) selecting a substrate consisting of a substrate (1), an oxide layer (2) and a channel layer (3) in sequence;
2) etching the thickness of the channel layer to 5 nm-10 nm by using an etching process;
3) growing SiO 2-5 nm thick on the upper surface of the channel layer (3) of the SOI substrate by using a chemical vapor deposition process2A layer;
4) by etching process, SiO on the left and right sides of the symmetry axis of the substrate2Etching two same grooves with the width of 5-15 nm on the layer to form a control insulated dielectric gate (4);
5) depositing a ferroelectric material, i.e. tetrakis (dimethylamino) zirconium or HfCl, in two trenches in the upper surface of the substrate using an atomic layer deposition process4Or ferroelectric elements such as TEMAHf or TEMAZr as precursor source, H2O or O3As precursor oxygen source, with N2As a purge gas, reacting and depositing at the temperature of 250-500 ℃ to form a ferroelectric layer with the thickness of 3-11 nm;
6) etching the ferroelectric layer outside the groove by using an etching process to remove the ferroelectric layer outside the groove and respectively form a source electrode polarization gate (6) and a drain electrode polarization gate (5);
7) growing metal on the upper surfaces of the polarization gate and the control gate by using a reactive sputtering process to form a polarization gate electrode layer;
8) etching the polarized gate electrode layer and SiO at the edge of the substrate2Etching away the layer and the channel layer to form an isolating insulating medium (7);
9) performing metal sputtering on the surface of the etched sample by using a reactive sputtering process to form a contact electrode layer;
10) etching the contact electrode layer above the polarized gate electrode layer by using an etching process, and etching the gate electrode layer metal above the contact of the polarized gate and the control gate insulating medium to form a control gate electrode (9);
11) and etching the metal above the isolation insulating medium (7) by using an etching process to form a source (12), a source polarization gate electrode (8), a drain polarization gate electrode (10) and a drain (11) in sequence from left to right, thereby completing the manufacture of the whole device.
8. The method as claimed in claim 7, wherein the chemical vapor deposition process in 2) is an inductively coupled growth process, wherein the reaction chamber is evacuated for 5-15 min and then Si is introduced simultaneously3H4And N2And taking O as a silicon source and an oxygen source, and reacting at the temperature of 50-100 ℃ to grow SiO 2.
9. The method of claim 7, wherein the reactive sputtering process in 6) and 8) is performed by first using a molecular pump and a cold pump to evacuate the reaction chamber until the vacuum pressure is 8E-6 Torr; and sputtering any one of the materials of tungsten, titanium, copper, aluminum and platinum under the conditions that the power is 350W and the Ar pressure is 5mTorr to form the metal electrode.
CN202110501010.3A 2021-05-08 2021-05-08 Ferroelectric doping based tunneling field effect transistor and preparation method thereof Active CN113241370B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110501010.3A CN113241370B (en) 2021-05-08 2021-05-08 Ferroelectric doping based tunneling field effect transistor and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110501010.3A CN113241370B (en) 2021-05-08 2021-05-08 Ferroelectric doping based tunneling field effect transistor and preparation method thereof

Publications (2)

Publication Number Publication Date
CN113241370A CN113241370A (en) 2021-08-10
CN113241370B true CN113241370B (en) 2022-07-12

Family

ID=77133068

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110501010.3A Active CN113241370B (en) 2021-05-08 2021-05-08 Ferroelectric doping based tunneling field effect transistor and preparation method thereof

Country Status (1)

Country Link
CN (1) CN113241370B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116782658B (en) * 2022-03-07 2024-06-07 长鑫存储技术有限公司 Semiconductor structure and forming method thereof
CN117295341A (en) * 2023-09-28 2023-12-26 北京大学 Ferroelectric nonvolatile memory and preparation method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103500758A (en) * 2013-10-12 2014-01-08 沈阳工业大学 Semi-gate controlled source schottky barrier type tunneling field effect transistor
CN103606563A (en) * 2013-10-22 2014-02-26 清华大学 Junctionless tunneling field effect transistor and formation method thereof
KR20160097448A (en) * 2015-02-06 2016-08-18 서강대학교산학협력단 Low-power tunnel field-effect transistor and method for fabricating the same
CN109004031A (en) * 2018-08-01 2018-12-14 中国科学技术大学 Ferroelectrical thin film transistor, organic light emitting array substrate driving circuit and display device
CN109104880A (en) * 2016-04-01 2018-12-28 英特尔公司 The field effect transistor based on ferroelectricity with threshold voltage switching of on-state and off-state performance for enhancing

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11488978B2 (en) * 2018-09-27 2022-11-01 Intel Corporation Ferroelectric gate oxide based tunnel feFET memory
US11101290B2 (en) * 2019-04-29 2021-08-24 International Business Machines Corporation Cross-point multilayer stackable ferroelectric field-effect transistor random access memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103500758A (en) * 2013-10-12 2014-01-08 沈阳工业大学 Semi-gate controlled source schottky barrier type tunneling field effect transistor
CN103606563A (en) * 2013-10-22 2014-02-26 清华大学 Junctionless tunneling field effect transistor and formation method thereof
KR20160097448A (en) * 2015-02-06 2016-08-18 서강대학교산학협력단 Low-power tunnel field-effect transistor and method for fabricating the same
CN109104880A (en) * 2016-04-01 2018-12-28 英特尔公司 The field effect transistor based on ferroelectricity with threshold voltage switching of on-state and off-state performance for enhancing
CN109004031A (en) * 2018-08-01 2018-12-14 中国科学技术大学 Ferroelectrical thin film transistor, organic light emitting array substrate driving circuit and display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Effects of Electrostatically Doped Source/Drain and Ferroelectric Gate Oxide on Subthreshold Swing and Impact Ionization Rate of Strained-Si-on-Insulator Tunnel Field-Effect Transistors;Mirgender Kumar，Satyabrata Jit;《 IEEE Transactions on Nanotechnology》;20150731;第14卷(第4期);第597-599页 *

Also Published As

Publication number Publication date
CN113241370A (en) 2021-08-10

Similar Documents

Publication Publication Date Title
US10269571B2 (en) Methods for fabricating nanowire for semiconductor applications
CN113241370B (en) Ferroelectric doping based tunneling field effect transistor and preparation method thereof
CN113140449B (en) Semiconductor doping method based on ferroelectric material
CN109585296A (en) The forming method of semiconductor device
CN108122765A (en) The forming method of semiconductor device
US10141454B2 (en) Field-effect transistors having black phosphorus channel and methods of making the same
CN109355622A (en) A kind of magnetron sputtering prepares the method and ferroelectric thin film of ferroelectric thin film
CN114093927B (en) Complementary field effect transistor based on ferroelectric doping and manufacturing method thereof
CN110649092A (en) Two-dimensional material heterojunction back gate negative capacitance tunneling transistor and preparation method thereof
CN115498035A (en) Reconfigurable high-mobility field effect transistor and preparation method thereof
CN113140675B (en) PN junction storage device based on ferroelectric doping
CN103855022B (en) The forming method of fin formula field effect transistor
KR20120047537A (en) Method of fabricating gate and method of manufacturing semiconductor device using thereof
CN113241373B (en) Ferroelectric doping-based field effect transistor and preparation method thereof
CN111430228A (en) Preparation method of dielectric film with ultrahigh dielectric constant
CN113224170A (en) Ferroelectric doping based negative capacitance field effect transistor
CN114429992A (en) Ferroelectric doping-based arched asymmetric reconfigurable field effect transistor and manufacturing method thereof
CN113921617B (en) Ga 2 O 3 Metal oxide semiconductor field effect transistor and preparation method thereof
WO2019007346A1 (en) Method for manufacturing semiconductor device having field plate structure with gradually varying thickness in trench
TW202145356A (en) Method of forming semiconductor device
CN107039283A (en) Transistor device based on variable work function grid electrode and preparation method thereof
TW202230533A (en) Formation of gate all around device
CN118380475B (en) Silicon carbide MOSFET power device and preparation method thereof
CN118315412A (en) Having NiOx/Ga2O3Ga of heterojunction structure2O3Fin type field effect transistor and preparation method thereof
TWI740465B (en) Ferroelectric fet device with ultra thin gate dielectric layer of crystallinity hfzro

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant