CN113241111A - Method for detecting contact between tube pin and tube seat of PROM chip - Google Patents
Method for detecting contact between tube pin and tube seat of PROM chip Download PDFInfo
- Publication number
- CN113241111A CN113241111A CN202110537133.2A CN202110537133A CN113241111A CN 113241111 A CN113241111 A CN 113241111A CN 202110537133 A CN202110537133 A CN 202110537133A CN 113241111 A CN113241111 A CN 113241111A
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000001514 detection method Methods 0.000 claims abstract description 19
- 230000015654 memory Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000003471 anti-radiation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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Abstract
The invention provides a method for detecting the contact between a PROM chip pin and a tube seat, wherein I/O pins of the PROM chip are provided with ESD protection diode circuits, each ESD protection diode circuit comprises a diode D1 and a diode D2, the diodes are connected with the I/O pins, and the detection method comprises the following steps: disconnecting a VCC (voltage converter) pin of a PROM chip from a power supply, and connecting the VCC pin of the PROM chip to an FPGA (field programmable gate array) detection pin; disconnecting a GND pin of the PROM chip from a GND network, and loading a power supply to the GND pin of the PROM chip after connecting the power supply in series with a loading resistor; and checking the high and low level states of the rest pins through the FPGA: if the FPGA detects that the I/O level is high, the contact between the PROM pins and the tube seats is good, otherwise, the contact between the PROM pins and the tube seats is poor. The method can effectively detect the contact between the PROM chip and the tube seat, thereby effectively avoiding the PROM programming failure caused by poor pin contact, greatly improving the PROM programming success rate, reducing the loss, and having simple and effective method without any damage to the chip.
Description
Technical Field
The invention relates to an anti-fuse PROM chip, in particular to a method for detecting the contact between a base pin and a base of the PROM chip.
Background
With the development of aerospace science and technology, satellite articles need more and more read-only memories as boot program memories for starting, stopping or resetting programs, and the anti-fuse type one-time programmable ROM memory for aerospace is widely applied to aerospace single machines and aerospace components due to the characteristics of high reliability, radiation resistance and the like, and becomes an indispensable link in the aerospace field.
The anti-fuse PROM for aerospace has complex manufacturing process and higher production cost, and can be programmed only once. Therefore, it is desirable to minimize the program failure rate to reduce the loss when using a programmer to program a PROM. According to the requirement of an anti-radiation PROM programmer on PROM programming reliability, before PROM programming, the programmer is required to complete self-checking of the contact integrity of each pin of the PROM and a programming tube seat of the programmer so as to prevent the programming failure of a PROM chip caused by pin virtual connection. In order to ensure the programming success rate of PROM, it is necessary to ensure the complete contact between chip pin and tube seat, and there is no virtual connection.
Disclosure of Invention
Aiming at the defects of the related prior art, the invention provides a method for detecting the contact between the pin and the tube seat of the PROM chip, which can effectively detect the contact between the PROM chip and the tube seat, thereby effectively avoiding the failure of PROM programming caused by poor pin contact, greatly improving the success rate of PROM programming, reducing the loss, and having simple and effective method without any damage to the chip.
In order to realize the purpose of the invention, the following scheme is adopted:
a method for detecting the contact between a pin and a tube seat of a PROM chip is characterized in that an I/O pin of the PROM chip is provided with an ESD protection diode circuit, the ESD protection diode circuit comprises a diode D1 and a diode D2 which are connected with the I/O pin, the anode of a diode D2 is connected with GND of the PROM chip, the cathode of a diode D2 is connected with the anode of a diode D1 and the I/O pin, and the cathode of a diode D1 is connected with VCC of the PROM chip;
the detection method comprises the following steps:
disconnecting a VCC (voltage converter) pin of a PROM chip from a power supply, and connecting the VCC pin of the PROM chip to an FPGA (field programmable gate array) detection pin;
disconnecting a GND pin of the PROM chip from a GND network, and loading a power supply to the GND pin of the PROM chip after connecting the power supply in series with a loading resistor;
and checking the high and low level states of the rest pins through the FPGA: if the FPGA detects that the I/O level is high, the contact between the PROM pins and the tube seats is good, otherwise, the contact between the PROM pins and the tube seats is poor.
Wherein, the power supply is 3.3V, and the loading resistor adopts 100 ohms.
The FPGA detection pin is also connected with GND through a grounding resistor, and the grounding resistor adopts 10K ohm.
The invention has the beneficial effects that:
1. the contact between the PROM chip and the tube seat can be effectively detected, so that the PROM programming failure caused by poor pin contact can be effectively avoided, the PROM programming success rate can be greatly improved, and the loss is reduced;
2. the chip is not damaged in the contact detection process, and the detection method is simple, reliable and effective;
3. the configurable characteristic of the pin direction of the FPGA is adopted to realize the contact detection before PROM programming;
4. by using the ESD protection diode on the PROM pin, the contact test is realized on the premise of not damaging the PROM.
Drawings
The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.
Fig. 1 is an internal ESD protection diode circuit of a PROM chip according to an embodiment of the present disclosure.
Fig. 2 is a circuit configuration diagram of an embodiment of a detection method according to an embodiment of the present application.
Fig. 3 is a PROM chip pin layout according to an embodiment of the present disclosure.
Fig. 4 is an overall functional block diagram of a PROM chip according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings, but the described embodiments of the present invention are a part of the embodiments of the present invention, not all of the embodiments of the present invention.
The example provides a method for detecting the contact between the pin and the tube seat of a PROM chip, which is applied to detecting the contact between the pin and the tube seat of the PROM chips such as XY28F256KLV, XY6664RH and the like.
FIG. 3 shows the pin layout of a high performance, asynchronous, radiation-resistant 256kbit programmable memory PROM chip, and FIG. 4 shows its overall functional block diagram. The anti-radiation anti-fuse fusing technology adopted by the device has very good stability and radiation resistance in the aerospace field.
The device tap function is defined in the following table:
for all functional I/O keys of such aerospace PROM chips, ESD protection diode circuits are typically designed at the I/O terminals or I/O pins for ESD protection purposes, as shown in fig. 1: the ESD protection diode circuit comprises a diode D1 and a diode D2 which are connected with an I/O pin, the anode of the diode D2 is connected with GND of a PROM chip, the cathode of the diode D2 is connected with the anode of the diode D1 and the I/O pin, and the cathode of the diode D1 is connected with VCC of the PROM chip.
As can be seen from the ESD protection diode circuit structure of the I/O pin of the chip in fig. 2, in addition to the power and ground pins, other functional pins will be connected to power and ground through two diodes. Based on the test circuit, the PROM chip pin and socket contact is tested as shown in FIG. 2.
Based on this, the detection method comprises:
disconnecting a VCC (voltage converter) pin of a PROM chip from a power supply, and connecting the VCC pin of the PROM chip to an FPGA (field programmable gate array) detection pin;
disconnecting a GND pin of the PROM chip from a GND network, and loading a power supply to the GND pin of the PROM chip after connecting the power supply in series with a loading resistor;
and checking the high and low level states of the rest pins through the FPGA: if the FPGA detects that the I/O level is high, the contact between the PROM pins and the tube seats is good, otherwise, the contact between the PROM pins and the tube seats is poor.
After the pin contact detection is completed, the programming of the PROM chip can be continuously completed on the basis of passing the detection by utilizing the configurable flexible characteristic of the input/output state of the FPGA pin, so that the programming success rate is ensured.
Wherein, the power supply is 3.3V, and the loading resistor adopts 100 ohms.
The FPGA detection pin is also connected with GND through a grounding resistor, and the grounding resistor adopts 10K ohm.
The detection method of the embodiment can effectively detect the contact between the PROM chip and the tube seat, thereby effectively avoiding the PROM programming failure caused by poor pin contact, greatly improving the PROM programming success rate and reducing the loss.
The foregoing is only a preferred embodiment of the present invention and is not intended to be exhaustive or to limit the invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention.
Claims (5)
1. A method for detecting the contact between a base pin and a tube seat of a PROM chip is characterized in that an I/O (input/output) base pin of the PROM chip is provided with an ESD (electro-static discharge) protection diode circuit, the ESD protection diode circuit comprises a diode D1 and a diode D2 which are connected with the I/O base pin, the anode of a diode D2 is connected with GND (ground) of the PROM chip, the cathode of a diode D2 is connected with the anode of a diode D1 and the I/O base pin, and the cathode of a diode D1 is connected with VCC of the PROM chip;
the detection method comprises the following steps:
disconnecting a VCC (voltage converter) pin of a PROM chip from a power supply, and connecting the VCC pin of the PROM chip to an FPGA (field programmable gate array) detection pin;
disconnecting a GND pin of the PROM chip from a GND network, and loading a power supply to the GND pin of the PROM chip after connecting the power supply in series with a loading resistor;
and checking the high and low level states of the rest pins through the FPGA: if the FPGA detects that the I/O level is high, the contact between the PROM pins and the tube seats is good, otherwise, the contact between the PROM pins and the tube seats is poor.
2. The method of claim 1 wherein the power supply is 3.3V and the loading resistance is 100 ohms.
3. The method for detecting the contact between the pin and the tube seat of the PROM chip according to claim 1, wherein the FPGA detection pin is further connected to GND through a ground resistor.
4. The method of claim 1 wherein the ground resistance is 10K ohms.
5. The method of claim 1 for detecting the pin-to-socket contact of a PROM chip, wherein after the pin-to-socket contact is detected, programming of the PROM chip is continued based on the detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110537133.2A CN113241111A (en) | 2021-05-18 | 2021-05-18 | Method for detecting contact between tube pin and tube seat of PROM chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110537133.2A CN113241111A (en) | 2021-05-18 | 2021-05-18 | Method for detecting contact between tube pin and tube seat of PROM chip |
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| Publication Number | Publication Date |
|---|---|
| CN113241111A true CN113241111A (en) | 2021-08-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110537133.2A Pending CN113241111A (en) | 2021-05-18 | 2021-05-18 | Method for detecting contact between tube pin and tube seat of PROM chip |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100214705A1 (en) * | 2009-02-26 | 2010-08-26 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection element and electrostatic discharge protection circuit including the same |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| US20140286085A1 (en) * | 2013-03-22 | 2014-09-25 | Kabushiki Kaisha Toshiba | Power supply circuit and protection circuit |
| CN108519541A (en) * | 2018-04-23 | 2018-09-11 | 珠海深圳清华大学研究院创新中心 | A kind of detection circuit and detection device |
-
2021
- 2021-05-18 CN CN202110537133.2A patent/CN113241111A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100214705A1 (en) * | 2009-02-26 | 2010-08-26 | Samsung Electronics Co., Ltd. | Electrostatic discharge protection element and electrostatic discharge protection circuit including the same |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| US20140286085A1 (en) * | 2013-03-22 | 2014-09-25 | Kabushiki Kaisha Toshiba | Power supply circuit and protection circuit |
| CN108519541A (en) * | 2018-04-23 | 2018-09-11 | 珠海深圳清华大学研究院创新中心 | A kind of detection circuit and detection device |
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