CN113239348A

CN113239348A - Multi-core redundancy system

Info

Publication number: CN113239348A
Application number: CN202110432568.0A
Authority: CN
Inventors: 张永壮; 张会彬; 张�杰; 高文杰; 李欣
Original assignee: Beijing University of Posts and Telecommunications
Current assignee: Beijing University of Posts and Telecommunications
Priority date: 2021-04-21
Filing date: 2021-04-21
Publication date: 2021-08-10
Anticipated expiration: 2041-04-21
Also published as: CN113239348B

Abstract

The present disclosure provides a multi-core redundancy system, comprising: the main core is configured to receive first data from the programmable logic component and pack the first data when a preset timing expires, so as to obtain a first data packet; the first secondary core is configured to receive second data from the programmable logic component and pack the second data when a preset timing expires, so that a second data packet is obtained; a first memory, coupled to the primary core and the first secondary core, configured to store a second data packet; wherein the primary core is further configured to: reading the second data packet from the first memory; judging based on the first data packet and the second data packet to obtain a judgment result; determining a correct data packet in response to determining that the decision result indicates that the decision is successful; and sending the correct data packet to an application layer. According to the method and the device, efficient communication of the data is achieved, correct data are transmitted after all data are judged through the main core, and reliability of data transmission is guaranteed.

Description

Multi-core redundancy system

Technical Field

The present disclosure relates to the field of computer technology, and more particularly, to a multi-core redundancy system.

Background

With the rapid development of electronic technology, large-scale integrated circuits and embedded computers are widely used in electronic products, and have become the cornerstones for normal operation of modern electronic devices. However, along with the popularization of electronic products, the increasing rampant of hacking and the existence of various loopholes make electronic systems with originally lower security become more vulnerable. This makes the electronic product put higher demands on the efficiency, reliability and safety of the embedded control system. In the aspect of improving the reliability and safety of the system, error avoidance and fault tolerance of the system are relatively critical links. In the prior art, the embedded system has the technical problems of single structure, low risk resistance and low safety.

Disclosure of Invention

In view of the above, the present disclosure is directed to a multi-core redundancy system.

In view of the above, the present disclosure provides a multi-core redundancy system, including:

the main core is configured to receive first data from the programmable logic component and pack the first data when a preset timing expires, so as to obtain a first data packet;

the first secondary core is configured to receive second data from the programmable logic component and pack the second data when the preset timing expires, so as to obtain a second data packet;

a first memory coupled to the primary core and the first secondary core and configured to store the second packet;

wherein the primary core is further configured to:

reading the second data packet from the first memory;

judging based on the first data packet and the second data packet to obtain a judgment result;

determining a correct data packet in response to determining that the decision result indicates that the decision was successful;

and sending the correct data packet to an application layer.

Optionally, the master core comprises: a main timer module, a main core receiving module, a main database module, a main core packing module, a judgment module and a transmission module, wherein,

the master core receiving module receives the first data and stores the first data in the master database module;

when the preset timing of the master timer module expires, the master core packaging module packages the first data in the master database module into the first data packet;

the primary core receiving module is also used for reading the second data packet from the first memory;

the decision module makes a decision based on the first data packet and the second data packet to obtain the decision result, and determines a correct data packet in response to determining that the decision result indicates that the decision is successful;

and the transmission module sends the correct data packet to the application layer.

Optionally, the first secondary core comprises: a first timer module, a first database module, and a first packetization module, wherein,

the first data receiving module receives the second data and stores the second data in the first database module;

when the preset timing of the first timer module expires, the first packetizing module packetizes the second data in the first database module into the second data packet, and sends the second data packet to the first memory.

Optionally, the first secondary core includes at least one first core, and the first memory includes at least one first data storage sub-region and at least one first flag bit sub-region;

for each first core, the first data storage sub-region corresponds to store a second data packet of the first core, and the first flag bit sub-region corresponds to store a flag bit of the second data packet of the first core.

Optionally, the determining based on the first data packet and the second data packet obtains a determining result; and in response to determining that the decision result indicates a successful decision, determining a correct data packet, comprising:

and determining that the data packet with the most occurrence times among all the data packets subjected to the judgment and the occurrence times larger than or equal to a preset value is the correct data packet.

Optionally, the system further comprises:

a second secondary core, different from the first secondary core, configured to receive third data from the programmable logic component, and package the third data when the preset timing expires, so as to obtain a third data package;

the primary core is further configured to:

performing the decision based on the first data packet, the second data packet and the third data packet to obtain a decision result;

and sending the correct data packet to the application layer.

Optionally, the second secondary core includes at least one second core, and the first memory further includes at least one second data storage area and at least one second flag area; for each second core, the second data storage sub-region corresponds to store a third data packet of the second core, and the second flag bit sub-region corresponds to store a flag bit of the third data packet of the second core.

Optionally, the second secondary core comprises at least one second core, the system further comprising: the second memory is connected to the primary core and the second secondary core and comprises at least one third data storage area and at least one third zone bit area; wherein the content of the first and second substances,

for each second core, the third data storage sub-region corresponds to store a third data packet of the second core, and the third flag bit sub-region corresponds to store a flag bit of the third data packet of the second core.

Optionally, the second secondary core comprises: a second timer module, a second database module, and a second packaging module, wherein,

the second data receiving module receives the third data and stores the third data in the second database module;

when the preset time of the second timer module expires, the second packetization module packetizes the third data in the second database module into the third data packet.

Optionally, the primary core further reads the second data packet and the third data packet from the first memory and the second memory through a plurality of parallel threads, where each of the threads reads the second data packet of each of the first secondary cores or the third data packet of each of the second secondary cores, respectively.

As can be seen from the above, according to the multi-core redundancy system of the embodiment of the present disclosure, efficient data communication is achieved through the structure of the multi-core and the shared memory, and correct data is transmitted after all data are determined by the master, so that reliability of data transmission is ensured.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic block diagram of a multi-core redundancy system in accordance with an embodiment of the present disclosure;

FIG. 2 is a schematic block diagram of a primary core according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram of an example of a first memory according to an embodiment of the present disclosure;

fig. 4 is a schematic diagram of an example of a first memory according to an embodiment of the present disclosure;

FIG. 5 is an example flow diagram of a process for a primary core to read a second data packet from a first memory in accordance with an embodiment of the present disclosure;

FIG. 6 is an exemplary flow chart for a process of majority decision according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of an example of a second memory according to an embodiment of the present disclosure;

FIG. 8 is a schematic block diagram of an example of a multi-core redundancy system in accordance with an embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical terms or scientific terms used in the embodiments of the present disclosure should have a general meaning as understood by those having ordinary skill in the art to which the present disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

The traditional embedded system has the advantages of single structure, risk resistance and lower safety, and the electronic system becomes more fragile due to various loopholes, backdoors and rampant hacker trojan horse. With the development of technology, the requirements of users on electronic products are increasing, which puts higher requirements on the efficiency, reliability and safety of the embedded control system. Meanwhile, the existing defense system is also an accurate defense based on threat characteristic perception. For example, common defense measures such as firewalls, intrusion detection, situation awareness and the like are established and can be effectively implemented on the premise of obtaining prior knowledge such as known attack models, attack mechanisms, attack characteristics and the like. In the whole attack and defense system, the defense is usually in a passive situation of 'attack finding, vulnerability finding and vulnerability repairing' sheep death reinforcement type. Therefore, the traditional embedded system can not ensure the complex information system or the ecological environment of the network space to be 'without holes and backdoors' or 'non-toxic and sterile', the safety can only expect 'acquired immunity', namely, a novel attack characteristic and a latest vulnerability patch are obtained to perfect a defense system, and the defense system can not be overcome from the self structure.

In addition, in the data transmission process of the conventional embedded system, an Arm core is selected, information and data are periodically acquired from Programmable Logic (PL), and then the information and the data are reported. This may cause a hacker or a trojan horse to intercept or modify the ethernet packet during transmission, and eventually cause an error in information transmission.

In view of the above, the embodiments of the present disclosure provide a multi-core redundancy system, which can enhance the ability of risk resistance and active defense from the system structure, and enhance the safety and reliability of data transmission. Referring to FIG. 1, FIG. 1 shows a schematic block diagram of a multi-core redundancy system according to an embodiment of the present disclosure. As shown in fig. 1, a multi-core redundancy system 100 includes:

the main core 110 is configured to receive first data from the programmable logic component, and package the first data when a preset timing expires, so as to obtain a first data package;

the first secondary core 120 is configured to receive second data from the programmable logic component, and package the second data when the preset timing expires, so as to obtain a second data packet;

a first memory 130, connected to the primary core 110 and the first secondary core 120, configured to store the second data packet;

wherein the primary core 110 is further configured to:

reading the second data packet from the first memory 130;

and sending the correct data packet to an application layer.

The multi-core redundancy system of the embodiment of the disclosure uses a main core and a first secondary core to realize data transmission together, the main core and the first secondary core respectively receive data from a programmable logic component, and the received data are packed at intervals of preset time to obtain a second data packet; the first secondary core stores the second data into the first memory; the main core reads the second data packet from the first memory, judges the second data packet together with the first data packet packaged by the main core and sends the judged correct data packet to the application layer, so that a multi-core redundant system structure is formed based on the main core, the first auxiliary core and the first memory, the risk resistance and the active defense capability are enhanced from the system structure, and the safety and the reliability of data transmission are enhanced. The conventional system structure data errors are mainly caused by the fact that when a core acquires data from a PL query, the data errors are caused by the fact that the core is attacked and tampered by a virus or a Trojan horse. Compared with the traditional system structure, according to the multi-core redundancy system disclosed by the invention, the plurality of cores acquire data from the PL, the accuracy is increased, and the problems that the system structure is single, the system safety is poor and data transmission errors are easy to occur are solved.

In some embodiments, the multi-core redundancy system 100 may be implemented based on ZCU102 development boards. Currently, the types of Arm processors are diverse, mainly including Arm7, Arm9, Arm9E, Arm10E, Arm10, Cortex, SecureCore, Xscale, StrongArm Arm 11 series. However, the more used Arm processors in the market can be classified into 5 types: Cortex-A (advanced), Cortex-R (Real-time), Cortex-M (microprocessor), Machine Learning, and SecurCore (Security kernel). Of these, Cortex-A is the "advanced processor" and is the most widely used processor. Cortex-a performance and efficiency are balanced to achieve maximum performance with optimal power consumption. Cortex-A53 is a typical processor in the Cortex-A family. It supports the selection of high thread and FPU/NEON performance; various applications of automobiles and networks are supported; and is also the most widely deployed 64-bit Cortex-a processor. The Cortex-R processor is a real-time processor, providing seamless, real-time performance and security. Cortex-R5 is one representative thereof. The dual core-R5 configuration has twice the performance of previous Cortex-R processors, is well suited for developing safety critical products, and is commonly used in large volume deeply embedded SOC applications. Cortex-M is a microprocessor, the most power-efficient processor in embedded devices, and is therefore often used in smart cards, smart devices, sensors, etc. Other processors, such as Machine-learning and Secure-core, are also used in the fields of Machine learning, edge computing, SIM cards, etc. with their own features. The Xilinx Zynq UltraScale ZCU102 development board integrates a 64-bit quad Arm core-A53, a dual-core Arm core-R5 Processing System (PS) and a Serpentine Programmable Logic (PL) that are rich in functionality within a single device. ZCU102 development board Cortex-A53 core is in APU (accelerated processor) unit in PS. The Cortex-R5 core is in an RPU (real time processing unit) unit in the PS.

Alternatively, primary core 110 may be implemented based on any one Cortex-A53 core, or any one Cortex-R5 core.

Optionally, referring to fig. 2, fig. 2 shows a schematic block diagram of a primary core according to an embodiment of the present disclosure. As shown in fig. 2, the main core 110 includes: a master timer module 111, a master core reception module 112, a master database module 113, a master core packaging module 114, a decision module 115, and a transmission module 116, wherein,

the master core receiving module 112 receives the first data and stores the first data in the master database module 113;

when the preset timing of the master timer module 112 expires, the master core packing module 114 packs the first data in the master database module 113 into the first data packet;

the primary core receiving module 112 further reads the second data packet from the first memory;

the decision module 115 makes a decision based on the first data packet and the second data packet to obtain the decision result, and determines a correct data packet in response to determining that the decision result indicates that the decision is successful;

the transmission module 116 sends the correct data packet to the application layer.

In some embodiments, the primary core 110 may further include an initialization module configured to initialize the primary core 110. Further, the initialization module may initialize the master timer module, the master database module, and the transmission module.

In some embodiments, the transmission module 116 transmits the correct packet based on a lwip function.

Alternatively, the preset timing may be 100 ms. It should be understood that the preset timing can be set as desired, and is not limited herein.

Optionally, the first secondary core 120 comprises: a first timer module, a first database module, and a first packetization module, wherein,

In some embodiments, the first secondary core may further include: a first type initialization module configured to initialize a first secondary core. Further, the first type initialization module can also initialize the first timer module and the first database module.

In some embodiments, the first timer module is time synchronized with the master timer module.

Optionally, the first memory 130 may be a shared memory of the primary core 110 and the first secondary core 120.

The shared memory refers to a large-capacity memory that can be accessed by different Central Processing Units (CPUs) in an embedded system. Since a plurality of CPUs needs to access the memory quickly, the memory is cached (Cache). Referring to fig. 3, fig. 3 is a schematic diagram illustrating an example of a first memory according to an embodiment of the present disclosure. As shown in fig. 3, in the ZCU102 development board, the shared Memory mainly includes two parts, namely DDR SDRAM (Double Data Rate SDRAM) and OCM (On Chip Memory). Wherein the DDR may further comprise: DDR0 and DDR 1. DDR1 memory size is 256MB, and may only be used for communication between Cortex-A53 cores. The OCM memory size is 32KB, and can be used for communication between Cortex-A53 cores and between Cortex-R5 cores.

In some embodiments, referring to fig. 3, first memory 130 may include DDR1 and/or OCM.

Alternatively, the primary core 110 may be the same type of core as the first secondary core 120, or may be a different type of core.

In some embodiments, primary core 110 is the same type of core as first secondary core 120, and may be a Cortex-A53 core or a Cortex-R5 core.

Further, in some embodiments, when the primary core 110 and the first secondary core 120 are both Cortex-a53 cores, the first memory 130 may be DDR1 and/or OCM.

Further, in some embodiments, when the primary core 110 and the first secondary core 120 are both Cortex-R5 cores, the first memory 130 may be an OCM.

In some embodiments, primary core 110 is a different type of core than first secondary core 120, and may include: the primary core 110 is a Cortex-A53 core and the first secondary core is a Cortex-R5 core, or the primary core 110 is a Cortex-R5 core and the first secondary core is a Cortex-A53 core.

Further, in some embodiments, the first memory 130 may be an OCM when the primary core 110 and the first secondary core 120 belong to different types of cores.

Optionally, the first secondary core 120 may include at least one first core. Further, the first core may be a Cortex-A53 core or a Cortex-R5 core.

Accordingly, optionally, the first memory 130 includes at least one first data storage sub-region and at least one first flag bit sub-region;

In some embodiments, the first memory may be partitioned according to a number of first cores included by the first secondary core. The main core and the first secondary core share the first memory. Therefore, efficient communication among the multiple cores can be ensured by dividing the storage area of the shared first memory.

In some embodiments, referring to fig. 4, fig. 4 shows a schematic diagram of an example of a first memory according to an embodiment of the present disclosure. As shown in fig. 4, with the master core being the core0 and the first slave core including the core1, the core2 and the core3, the first memory may be divided into 6 blocks according to the starting address, and include 3 memory address spaces (e.g., 10KB) as the first data storage sub-region and 3 memory address spaces (e.g., 5KB) as the first flag bit sub-region, and the memory addresses of the respective memory regions are consecutive. Specifically, the starting address of the 3 memory address spaces that are the first data storage sub-regions may be labeled in order Share _ Base1, Share _ Base2, Share _ Base3, Share _ Base1 for data packets storing core1, Share _ Base2 for data packets storing core2, Share _ Base3 for data packets storing core3, and master core0 may access any of Share _ Base1, Share _ Base2, and Share _ Base 3. The starting addresses of the 3 memory address spaces as the first flag sub-regions may be sequentially marked LEN _1, LEN _2, LEN _3, LEN _1 indicates the flag bit of the packet storing the core1, LEN _2 indicates the flag bit of the packet storing the core2, LEN _3 indicates the flag bit of the packet storing the core3, and the master core0 may access any one of LEN _1, LEN _2, and LEN _ 3. The address spaces of Share _ Base1, Share _ Base2, Share _ Base3, and LEN _1, LEN _2, LEN _3 are contiguous.

Optionally, the reading, by the primary core 110, the second data packet from the first memory 130 may further include: the primary core 110 reads the second data packet from the first memory through a plurality of parallel threads, wherein each thread reads the second data packet of each first secondary core.

Specifically, referring to fig. 5, fig. 5 shows a flowchart of a process in which a primary core reads a second packet from a first memory according to an embodiment of the present disclosure. As shown in fig. 5, in step S510, a flag send _ id is set for the first secondary core. Specifically, a flag bit send _ id is set for each of the first secondary cores core1, core2, and core3, which indicates the number of times that the core writes data to the corresponding address of the first memory, and the initial value of the send _ id is 0; for example, in the above embodiment, the send _ ids of the first secondary cores core1, core2, and core3 are send _ id1, send _ id2, and send _ id3, respectively.

Step S520, a flag bit recv _ id corresponding to the first secondary core is set for the primary core. Specifically, 3 flag bits recv _ id1, recv _ id2 and recv _ id3 are correspondingly set in the master core0, the flag bits recv _ id1, recv _ id2 and recv _ id3 indicate the number of times the core0 receives a packet from the core1-core3, and the initial values of recv _ id1, recv _ id2 and recv _ id3 are 0. A variable count is further set in the master core0, and the initial value is 0, which indicates the total number of times of receiving packets from the core1-core3 cores after the preset time of the master timer module expires (i.e., after the master core0 completes the packaging of its own data). It may be arranged that when the variable count is not equal to the loop threshold, e.g. 3 (i.e. the number of first secondary cores), the following procedure is looped:

step S530, after the preset timing expires, each core (including the primary core and the first secondary core) writes data into a corresponding first data storage sub-area in the first memory; and writing the flag bit send _ id + + into a corresponding first flag bit sub-area in the first memory. Specifically, for the first secondary core1-core3, each time the preset time of the respective first timer module expires, a first packetization module (e.g., a packet function) in the respective core may be called to packetize the data received from the PL, so as to form a second packet of the respective core, where the second packet may be of a string type. After the packaging is completed, the first secondary cores core1-core3 write the respective second data packets into the corresponding first data storage sub-regions Share _ Base1, Share _ Base2, Share _ Base3 in the first memory; then, the respective send _ id + +, writing into the corresponding first flag bit sub-regions LEN _1, LEN _2, LEN _3 in the first memory.

In step S540, the main core starts multithreading to read the flag bit in the first memory, and waits for the flag bit to change. Specifically, at this time, since the main timer module and the first timer module perform synchronous timing, the main core0 completes the packing of the data received from the PL after the preset time of the main timer module expires, so as to obtain a first data packet; the primary core0 may read the data of each of the first secondary cores in the first memory through the primary core receiving module (i.e., call the recv function). Specifically, the master core0 establishes multiple threads, e.g., 3.

In step S550, if the flag bit in the first flag bit sub-area changes, the corresponding data packet in the first memory starts to be read. Specifically, for each thread, the flag bits in the respective corresponding first flag bit sub-regions are detected (i.e., read in a loop) by the waitID () function, and the read results are denoted as the compound, and the read results of the flag bits in the first flag bit sub-regions LEN _1, LEN _2, LEN _3 are respectively compound 1, compound 2, and compound 3. If the compID is recv _ id +1, the fact that the first core corresponding to the area in the first memory has new data written in is represented, and the waitID1() function is exited; and reading the newly written second data packet from the corresponding first data storage subarea, and adding 1 to count.

Step S560, after the data packets of all the first secondary cores are completely read, entering a decision. Specifically, when the count is equal to 3, it indicates that the core0 has completed receiving all the second packets of the first secondary core1-core3, and the decision module may be entered to make a decision.

Therefore, according to the embodiment of the disclosure, a plurality of parallel threads and a polling mode are arranged in the main core to capture the change of the status of the flag bit, and the data in the shared first memory is read only when the flag bit changes, so that the problems that a plurality of cores trigger core0 core interrupt at the same time to cause interrupt conflict and the received data is not synchronous due to the adoption of a traditional interrupt mode are avoided. The problems of timer delay and the disorder of the received data of the main core are solved.

Optionally, the main core 100 makes a decision based on the first data packet and the second data packet to obtain a correct data packet, where the decision is a majority decision, and includes determining that the data packet having the largest occurrence number among all data packets making the decision and the occurrence number greater than or equal to a preset value is the correct data packet.

Under normal conditions, the data returned by each core is correct, and the data of each core is consistent during judgment; under abnormal conditions, the data returned by each core from the PL may not all be consistent, but the correct data can still be determined by a decision algorithm, and the wrong core can be found.

In some embodiments, the master core 100 makes a decision based on the first packet and the second packet to obtain the correct packet, and the decision may further include a confidence-based decision method. The trust level may include the number of successful attacks and the degree of heterogeneity of each core. The number of successful attacks, that is, the number of times of erroneous evaluation of each core in the whole history process, is recorded, and the higher the number of successful attacks is, the lower the trust level is. The degree of isomerism is the degree of isomerism of each core in the whole system, and the higher the degree of isomerism is, the higher the trust level of the core is. The best result in the system probability sense can be obtained by the confidence index and the Bayesian algorithm estimation as the correct data packet.

In some embodiments, the preset value may be set as needed, and is not limited herein.

Specifically, referring to fig. 6, fig. 6 shows an example flow chart of a process of decision according to an embodiment of the present disclosure. As shown in FIG. 6, in step S610, an array char str [ ] is set in the primary core0 to store packets from the first secondary core1-core3, and an array b [ i ] is set to indicate the total number of occurrences of each str [ i ]. Specifically, the data packets obtained by packing the data checked by the core 0-core 3 may be labeled as companebuf 0, companebuf 1, companebuf 2, and companebuf 3 in sequence. A charstr [ ], storing character strings of compoebuf 0 to compoebuf 3, and an int-type array b [ i ] may be set in the decision block of the core0, with an initial value set to 0, and b [ i ] representing the total number of occurrences of each str [ i ] (0< ═ i < ═ 3) in the entire str array (including the array str [ i ] itself).

Step S620, finding out the maximum Flag in the array b [ i ], wherein the character string corresponding to the Flag is finalbuf. Specifically, the decision module also sets a Flag, which has an initial value of 0 and represents the maximum value in b [ i ] (0< ═ i < ═ 3). Comparing str [ i ] with str [ j ] to determine if they are equal (0 ═ i ═ 3,0 ═ j ═ 3), and if they are equal, adding 1 to the value of b [ i ]; the str [ i ] array is traversed sequentially until each b [ i ] value is found, e.g., b [ i ] ═ b0, b1, b2, b 3. Sequentially traversing values in the b [ i ] array (0< ═ i < ═ 3), finding the maximum value, and recording the maximum value as Flag; if b0, b1, b2 and b3 are traversed to obtain the maximum value b2, then b2 is set as flag.

In step S630, it is determined whether Flag is greater than or equal to a predetermined value.

In step S640, if Flag > is equal to the preset value (e.g., 3), it indicates that the decision is successful, and str [ i ] corresponding to b2 indicates the character string with the largest occurrence frequency, which is denoted as finalbuf. Finalbuf may also be sent to the application layer through the transport module. Meanwhile, the count value and the flag are set to be 0, and the arrays b [ ], str [ ]andfinalbuf are all cleared to be configured as the next round of judgment.

In step S650, if 0 ═ flag < preset value, it indicates that the decision failed, and the error may be reported to the upper layer.

Therefore, according to the multi-core redundancy system disclosed by the embodiment of the disclosure, data is processed based on a multi-core structure, and a majority decision mechanism is adopted to decide the data of a plurality of cores, so that the correctness of finally sent data is ensured, and the reliability and the safety in the data transmission process are improved.

It should be understood that the number of cores in the first secondary core is merely an example, and is not intended to be limited thereto, and the number of cores in the first secondary core may be set as needed, and is not limited herein.

Optionally, the multi-core redundancy system according to the embodiment of the present disclosure may further include:

the primary core is further configured to:

and sending the correct data packet to the application layer.

In some embodiments, the second secondary core comprises: a second timer module, a second database module, and a second packaging module, wherein,

In some embodiments, the second secondary core may further include: a second class initialization module configured to initialize a second secondary core. Further, the second type initialization module can also initialize the second timer module and the second database module.

In some embodiments, the first timer module is time synchronized with the timer module.

In some embodiments, where the first subcore is a Cortex-A53 nucleus, the second subcore may be a Cortex-R5 nucleus.

In some embodiments, where the first subcore is a Cortex-R5 core, the second subcore may be a Cortex-A53 core.

In some embodiments, the second secondary core comprises at least one second core.

In some embodiments, when the first memory is an OCM, the primary core, the first secondary core, and the second secondary core may share the first memory.

In some embodiments, the first memory further comprises at least one second data storage region and at least one second flag region; for each second core, the second data storage sub-region corresponds to store a third data packet of the second core, and the second flag bit sub-region corresponds to store a flag bit of the third data packet of the second core.

At this time, in some embodiments, the first memory may be partitioned according to a sum of the number of first cores included in the first secondary core and the number of second cores included in the second secondary core. The first memory is shared by the main core, the first auxiliary core and the second auxiliary core. Therefore, efficient communication among the multiple cores can be ensured by dividing the storage area of the shared first memory.

Specifically, referring to fig. 7, fig. 7 shows a schematic diagram of an example of a second memory according to an embodiment of the present disclosure. With reference to fig. 4 and 7, the primary core is a core0, the first secondary core includes a core1, a core2, and a core3, the second secondary core includes a core4 and a core5, and the first memory may be divided into 10 parts according to the starting address, and the first memory includes 5 memory address spaces (e.g., 10KB) as the first data storage sub-region and the second data storage sub-region, and 5 memory address spaces (e.g., 5KB) as the first flag bit sub-region and the second flag bit sub-region, and the memory addresses of the memory regions are consecutive. Specifically, the starting address of the 3 memory address spaces that are the first data storage sub-regions may be labeled in order Share _ Base1, Share _ Base2, Share _ Base3, Share _ Base1 for storing packets of core1, Share _ Base2 for storing packets of core2, Share _ Base3 for storing packets of core 3; the starting address of the 2 memory address spaces that are the second data storage sub-regions may be labeled in order Share _ Base4, Share _ Base5, Share _ Base4 for data packets storing core4, Share _ Base5 for data packets storing core5, and primary core0 may access any of Share _ Base1 through Share _ Base 5. The starting addresses of the 3 memory address spaces serving as the first flag bit sub-regions can be sequentially marked as LEN _1, LEN _2 and LEN _3, LEN _1 represents a flag bit of a packet storing core1, LEN _2 represents a flag bit of a packet storing core2, and LEN _3 represents a flag bit of a packet storing core 3; the starting addresses of the 2 memory address spaces as the second flag sub-region may be sequentially marked as LEN _4, LEN _5, LEN _4 indicates the flag bit of the packet storing core4, LEN _5 indicates the flag bit of the packet storing core5, and the core0 of the primary core may access any one of LEN _1 to LEN _ 3. Share _ Base1, address space continuation to Share _ Base5 and LEN _1 to LEN _ 5.

In some embodiments, the system may further comprise: the second memory is connected to the primary core and the second secondary core and comprises at least one third data storage area and at least one third zone bit area; wherein the content of the first and second substances,

In some embodiments, the second memory may include DDR1 or OCM. Further, the second memory is different from the first memory.

In some embodiments, referring to fig. 8, fig. 8 shows a schematic block diagram of an example of a multi-core redundancy system in accordance with an embodiment of the present disclosure. As shown in fig. 8, if the first secondary core is a Cortex-a53 core, one of the Cortex-a53 cores may be the primary core, and the second secondary core is a Cortex-R5 core, the first memory is DDR1, and the second memory is OCM.

In some embodiments, the first subcore is a Cortex-R5 core and the second subcore is a Cortex-a53 core, then the first memory is an OCM and the second memory is a DDR 1.

Optionally, the reading, by the master core, the third data packet from the first memory may further include: and the main core reads the third data packet from the first memory through a plurality of parallel threads, wherein each thread reads the third data packet of each second auxiliary core respectively.

Optionally, the reading, by the master core, the third data packet from the second memory may further include: and the main core reads the third data packet from the first memory through a plurality of parallel threads, wherein each thread reads the third data packet of each second auxiliary core respectively.

It should be noted that a process of the primary core reading the third data from the first memory or a process of the primary core reading the third data from the second memory is similar to the process shown in fig. 5, and only the difference is that the primary core obtains the data packet from cores of different numbers (where a loop threshold of the variable count is a sum of the numbers of the first cores in the first secondary core and the second cores in the second secondary core), and data reading is performed from the storage region and the flag region corresponding to each core, which is not described herein again.

Optionally, at this time, the main core performs a decision based on the first data packet, the second data packet, and the third data packet to obtain a correct data packet, where the decision is a majority decision, and includes determining that a data packet with the most occurrence times among all data packets subjected to the decision and the occurrence times greater than or equal to a preset value is the correct data packet.

It should be understood that the process of the main core performing majority decision based on the first data packet, the second data packet, and the third data packet to obtain the correct data packet is similar to the process shown in fig. 6, except that the number of data packets participating in decision is different, and other specific processes are the same, and are not described herein again.

It should be noted that the above describes some embodiments of the disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments described above and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the present disclosure, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present disclosure are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the embodiments of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A multi-core redundancy system, comprising:

wherein the primary core is further configured to:

reading the second data packet from the first memory;

and sending the correct data packet to an application layer.

2. The system of claim 1, wherein the master core comprises: a main timer module, a main core receiving module, a main database module, a main core packing module, a judgment module and a transmission module, wherein,

3. The system of claim 1, wherein the first secondary core comprises: a first timer module, a first database module, and a first packetization module, wherein,

4. The system of claim 1, wherein the first secondary core comprises at least one first core, the first memory comprising at least one first data storage sub-region and at least one first flag bit sub-region;

5. The system of claim 1, wherein the making a decision based on the first packet and the second packet results in a decision result; and in response to determining that the decision result indicates a successful decision, determining a correct data packet, comprising:

6. The system of any of claims 1-5, further comprising:

the primary core is further configured to:

and sending the correct data packet to the application layer.

7. The system of claim 6, wherein the second secondary core comprises at least one second core, the first memory further comprising at least one second data storage region and at least one second flag region; for each second core, the second data storage sub-region corresponds to store a third data packet of the second core, and the second flag bit sub-region corresponds to store a flag bit of the third data packet of the second core.

8. The system of claim 6, wherein the second secondary core comprises at least one second core, the system further comprising: the second memory is connected to the primary core and the second secondary core and comprises at least one third data storage area and at least one third zone bit area; wherein the content of the first and second substances,

9. The system of claim 6, wherein the second secondary core comprises: a second timer module, a second database module, and a second packaging module, wherein,

10. The system of claim 6, wherein the primary core further reads the second and third data packets from the first and second memories through a plurality of parallel threads, wherein each of the threads reads the second data packet of each of the first secondary cores or the third data packet of each of the second secondary cores, respectively.