CN113238416A - Line driving circuit, driving method and display panel - Google Patents
Line driving circuit, driving method and display panel Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000013461 design Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000012423 maintenance Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13454—Drivers integrated on the active matrix substrate
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The application discloses a row driving circuit, a driving method and a display panel, wherein the row driving circuit comprises a charging module, an output module, a power supply module and a pull-down maintaining module; the control end of the charging module is connected with a grid starting signal or a superior grid driving signal; the control end of the output module is connected with the output end of the charging module, and the input end of the output module is connected with the current stage clock signal; the power supply module provides a continuous high level, and the output end of the power supply module is connected with the input end of the charging module; the first control end of the pull-down maintaining module is connected to the output end of the power supply module, the second control end is connected to the output end of the charging module, the input end is connected to the output end of the charging module, the output end is connected with a standard low level signal, the pull-down maintaining module is controlled to be opened and closed through the power supply module and the charging module, the potential of the output end of the charging module is effectively pulled down, other transistors controlled by a time sequence do not need to be arranged, the number of the transistors is reduced, and the narrow frame is favorably realized.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a row driving circuit, a driving method, and a display panel.
Background
Liquid Crystal Display (LCD) devices have many advantages such as thin body, power saving, no radiation, etc., and thus are widely used, and with the continuous development of LCD device production technology, LCD devices gradually tend to narrow frames and thin.
The current GDL circuit (Gate Driver Less) is applied to ultra high definition large-size products, but due to the change of customer consumption requirements, the improvement of factory technical requirements and the improvement of process capability, the screen resolution is increased, the frame width is reduced, the screen occupation ratio of the screen is increased, and the resolution is increased on the screen with the same size, which means that the size of each pixel is reduced; this requires that the GDL circuit should ensure performance and safety in a limited space and also exert its intended function; however, due to design reasons such as timing control and control connection of a plurality of signals to transistors, the number of transistors of the GDL circuit is as many as several tens, so that the layout design of the GDL circuit cannot meet the frame specification requirement; therefore, the design of the GDL circuit is modified again, and the occupied space of the GDL circuit is reduced as much as possible under the condition of meeting the driving capability, so that the requirements of narrow frame and high resolution are met.
Disclosure of Invention
The application aims to provide a row driving circuit, a driving method and a display panel, which are convenient for pulling down the electric potential of the row driving circuit, reduce the number of transistors and further realize a narrow frame.
The application discloses a row driving circuit, which comprises a charging module, an output module, a power supply module and a pull-down maintaining module; the control end of the charging module is connected to a gate starting signal or a superior gate driving signal; the control end of the output module is connected with the output end of the charging module, the input end of the output module is connected with the current-stage clock signal, and the output end of the output module outputs the current-stage grid driving signal; the power supply module provides a continuous high-level signal, and the output end of the power supply module is connected with the input end of the charging module; the first control end of the pull-down maintaining module is connected with the output end of the power supply module, the second control end of the pull-down maintaining module is connected with the output end of the charging module, the input end of the pull-down maintaining module is connected with the output end of the charging module, and the output end of the pull-down maintaining module is connected with a standard low level signal.
Optionally, the charging module includes a first transistor, the output module includes a second transistor, and the pull-down maintaining module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the control end of the first transistor is connected to a gate start signal or a superior gate drive signal, and the input end of the first transistor is connected to the output end of the power supply module; the output end of the first transistor is connected to the control end of the second transistor; the input end of the second transistor is connected to the current-stage clock signal, and the output end of the second transistor outputs a current-stage grid driving signal; the control end of the third transistor is connected with the control end of the first transistor, the input end of the third transistor is connected with the output end of the sixth transistor, and the output end of the third transistor is connected with the standard low-level signal; a control end of the fourth transistor is connected to an output end of the sixth transistor, an input end of the fourth transistor is connected to an output end of the first transistor, and an output end of the fourth transistor is connected to the standard low-level signal; a control end of the fifth transistor is connected to an output end of the first transistor, an input end of the fifth transistor is connected to an output end of the sixth transistor, and an output end of the fifth transistor is connected to the standard low-level signal; the control end and the input end of the sixth transistor are respectively connected to the output end of the power supply module; wherein a channel width-to-length ratio of the third transistor and the fifth transistor is larger than a channel width-to-length ratio of the sixth transistor.
Optionally, the channel width-to-length ratio of the third transistor to the fifth transistor is 500-600/4um, and the channel width-to-length ratio of the sixth transistor is 35-45/4 um.
Optionally, the pull-down maintaining module includes a seventh transistor, a control terminal of the seventh transistor is connected to a lower-level gate driving signal, an input terminal of the seventh transistor is connected to the output terminal of the first transistor, and an output terminal of the seventh transistor is connected to the standard low-level signal.
Optionally, the row driving circuit further includes a pull-down module, the pull-down module includes an eighth transistor, a control end of the eighth transistor is connected to an output end of the sixth transistor, an input end of the eighth transistor is connected to the current stage of the gate driving signal, and an output end of the eighth transistor is connected to the standard low level signal.
Optionally, the row driving circuit includes a ninth transistor, a control terminal of the ninth transistor is connected to a reset signal, an input terminal of the ninth transistor is connected to the output terminal of the first transistor, and an output terminal of the ninth transistor is connected to the standard low level signal.
The application also discloses a driving method applied to any one of the row driving circuits, which comprises the following steps:
starting a power supply module and keeping the output of a high-level signal;
receiving a frame starting signal or a superior grid driving signal;
outputting a current-level gate driving signal according to the high-level signal and the frame starting signal or a superior-level gate driving signal;
and after the current-stage grid driving signal is output, controlling the pull-down maintaining module to enable the level of the output end of the charging module to be at the potential of a standard low-level signal.
Optionally, after outputting the current-stage gate driving signal, the step of controlling the pull-down maintaining module to adjust the level of the output terminal of the charging module to the level of a standard low-level signal further includes:
and controlling the pull-down maintaining module to pull down the level of the output end of the output module to the potential of the standard low level signal.
Optionally, the driving method further includes the steps of:
and pulling down the level of the output end of the output module to the level of the standard low level according to a reset signal.
The application also discloses a display panel, the display panel comprises the line driving circuit, and the line driving circuit is used for driving and displaying the display panel.
Compared with the scheme that the potential corresponding to the row driving circuit needs to be pulled down according to the time sequence control in the current large-size liquid crystal, so that dozens of transistors are designed, the power supply module and the charging module are used for controlling the pull-down maintaining module to be turned on and off, the potential of the output end of the charging module is effectively pulled down, other transistors controlled by the time sequence are not needed to be arranged, the number of the transistors is reduced, the design of the GDL circuit needs to be modified again, the driving capability condition is met, the occupied space of the GDL circuit is reduced, and the requirements of narrow frames and high resolution are met.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic structural diagram of a row driving circuit according to an embodiment of the present application;
FIG. 2 is a circuit schematic of a row driver circuit according to an embodiment of the present application;
FIG. 3 is a circuit schematic of a row driver circuit of another embodiment of the present application;
FIG. 4 is a circuit (including pull-down modules) schematic diagram of a row driver circuit according to another embodiment of the present application;
FIG. 5 is a schematic diagram of circuitry (including reset signals) of a row driver circuit of an embodiment of the present application;
FIG. 6 is a schematic diagram of a row driver circuit according to another embodiment of the present application;
FIG. 7 is an idealized waveform diagram of a row driver circuit of an embodiment of the present application;
FIG. 8 is a diagram illustrating actual waveforms of a row driver circuit according to an embodiment of the present application;
FIG. 9 is a schematic diagram of a driving method according to an embodiment of the present application;
FIG. 10 is a schematic view of a display panel according to an embodiment of the present application; .
100, a row driving circuit; 110. a charging module; 120. an output module; 130. a power supply module; 140. a pull-down maintenance module; 150. a pull-down module; 200. a display panel; 210. scanning a line; 220. a clock signal module; 300. a display device; 400. a drive module; m1 — first transistor; m2 — second transistor; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; m8 — eighth transistor; m9 — ninth transistor; c-capacitance; STV-frame start signal.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application will now be described in detail with reference to the drawings and alternative embodiments, it being understood that any combination of the various embodiments or technical features described below may form new embodiments without conflict.
As shown in fig. 1 to 2, as another embodiment of the present application, a row driving circuit is disclosed, the row driving circuit 100 includes a charging module 110, an output module 120, a power supply module 130, and a pull-down maintaining module 140; the control terminal of the charging module 110 is connected to the gate start signal STV or the upper stage gate driving signal, if the current stage is n stages, the upper stage may be the (n-1) th stage, the (n-2) th stage, the (n-3) th stage, the (n-4) th stage, and so on, or even the (n-m) th stage, n and m are any natural numbers, and n is greater than m; the control end of the output module 120 is connected to the output end of the charging module 110, the input end is connected to the current-stage clock signal, and the output end outputs the current-stage gate driving signal; the power supply module 130 provides a continuous high level signal, and the output end of the power supply module is connected with the input end of the charging module; a first control terminal of the pull-down maintaining module 140 is connected to the output terminal of the power supply module 130, a second control terminal of the pull-down maintaining module 140 is connected to the output terminal of the charging module 110, an input terminal of the pull-down maintaining module is connected to the output terminal of the charging module 110, and an output terminal of the pull-down maintaining module 140 is connected to a standard low level signal.
In the existing large-size liquid crystal, as the number of wires and signals to be controlled is too many, dozens of transistors are usually required to be arranged, so that the GDL layout design cannot meet the frame specification requirement; compared with the existing small-size display, when the current row driving circuit is subjected to potential pull-down, the pull-down time is limited due to the fact that the current row driving circuit is pulled down by the existing small-size display, the transistor corresponding to the time sequence control circuit is troublesome to switch on and off due to the fact that the period of the clock signal is determined, software data needs to be modified for a long time due to the fact that the gate driving signal of the later stage is limited, the later stage signal is used for pull-down, a fixed interval number needs to be set to feed back the gate signal, and the transistor is easy to switch on and switch off due to the fact that the later stage signal fluctuates.
The GDL circuit design is to be revised again in the application, through opening and closing of power module and the module control pull-down maintenance module that charges, effectively pull down the electric potential of the output of the module that charges, need not to set up other transistors that receive sequential control, reduce transistor quantity, therefore GDL design is to be revised again, satisfy under the driving capability condition, make GDL circuit take up the space and reduce, under the unchangeable condition of circuit stability and security, reduce GDL circuit layout area occupied, can play a role in limited space, guarantee GDL circuit normal work, can reduce the technology risk in the technology preparation, reduce GDL circuit short circuit and failure probability, reach the narrow frame, the requirement of high resolution.
Further, as shown in fig. 2, the charging module includes a first transistor M1, the output module includes a second transistor M2, and the pull-down maintaining module includes a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6; a control end of the first transistor M1 is connected to a gate start signal STV or an upper gate driving signal, and an input end of the first transistor M1 is connected to an output end of the power supply module VDD; the output end of the first transistor M1 is connected to the control end of the second transistor M2; the input end of the second transistor M2 is connected to the current-stage clock signal, and the output end of the second transistor outputs the current-stage gate driving signal; the control end of the third transistor is connected with the control end of the first transistor, the input end of the third transistor M3 is connected with the output end of the sixth transistor, and the output end of the third transistor is connected with the standard low-level signal; a control end of the fourth transistor is connected to an output end of the sixth transistor, an input end of the fourth transistor is connected to an output end of the first transistor, and an output end of the fourth transistor is connected to the standard low-level signal; a control end of the fifth transistor is connected to an output end of the first transistor, an input end of the fifth transistor is connected to an output end of the sixth transistor, and an output end of the fifth transistor is connected to the standard low-level signal; the control end and the input end of the sixth transistor are respectively connected to the output end of the power supply module; the output module further comprises a storage capacitor, the input end of the storage capacitor is respectively connected with the output end of the first transistor and the control end of the second transistor, and the output end of the storage capacitor is connected with the output end of the second transistor.
In the present application, all the transistors are turned on at a high level and turned off at a low level, a channel width-to-length ratio of the third transistor and the fifth transistor is greater than a channel width-to-length ratio of the sixth transistor, and generally, the channel width-to-length ratio of the third transistor M3 and the fifth transistor M5 is 500 to 600/4um, and the channel width-to-length ratio of the sixth transistor is 35 to 45/4 um.
Specifically, refer to fig. 7 and 8, where fig. 7 is a waveform in an ideal state, fig. 8 is an actual waveform in a test, and fig. 8 takes n equal to 4 as an example to correspond, where the corresponding waveforms from top to bottom, that is, the first row waveform is a CK _4 waveform, the second row waveform is VDD/VSS/G _1(G _ n-3), the third row waveforms are G _4(G _ n) and q _4, the fourth row waveform is a qb _4 waveform, the fifth row waveform is G _8(G _ n + m), and the sixth row waveform is Reset; specifically, the fifth transistor M5 and the sixth transistor M6 are used in combination to control the qb voltage, the M1 receives the upper gate driving signal G _ n-3, when the gate driving signal is at a high level, the M1 is turned on, and when the q point is at a high level, the M3 and the M5 are turned on, since the channel widths of the M3 and the M5 are much larger than the channel width of the M6, the qb can be quickly pulled down to a low voltage level when the transistor is turned on. When the upper stage gate driving signal is at low level, M3 and M5 are turned off, M6 is kept on to continuously output high level VDD, qb is at high level, VDD turns on M4 to pull down q level.
As shown in fig. 3, as another embodiment of the present application, the pull-down maintaining module includes a seventh transistor M7, a control terminal of the seventh transistor M7 is connected to the lower-level gate driving signal, an input terminal of the seventh transistor M7 is connected to the output terminal of the first transistor, an output terminal of the seventh transistor is connected to the standard low-level signal, and is connected to the lower-level gate driving signal through the added seventh transistor, when the lower-level gate driving signal is driven, the potential of the gate driving circuit corresponding to the current gate driving signal is further pulled down, and the lower-level gate driving signal is connected as a control signal for turning on the seventh transistor, so that the potential of the q-point is further pulled down.
As shown in fig. 4, as another embodiment of the present application, the row driving circuit further includes a pull-down module, the pull-down module includes an eighth transistor M8, a control terminal of the eighth transistor is connected to an output terminal of the sixth transistor, an input terminal of the eighth transistor is connected to the current stage of the gate driving signal, and an output terminal of the eighth transistor is connected to the normal low level signal, and the eighth transistor continuously pulls down the potential of Gn.
As shown in fig. 5, as another embodiment of the present application, the row driving circuit includes a ninth transistor M9, a control terminal of the ninth transistor is connected to a reset signal, an input terminal of the ninth transistor is connected to the output terminal of the first transistor, and an output terminal of the ninth transistor is connected to the standard low level signal, and referring to fig. 7 and 8, the ninth transistor M9 is turned on after a frame is finished, so as to clear a potential at a point q on the row driving circuit.
As shown in fig. 6 to 8, as another embodiment of the present application, the above embodiments may be combined to obtain the present embodiment, it should be noted that the above embodiments may be combined arbitrarily, and only the latter case of the combination is stated herein for explanation.
In fig. 8, specifically, assuming that m/n is a positive integer, the GDL circuit turns on the nth GDL circuit through the output of the (n-3) th GDL Gate (Gate), so as to implement transmission of each stage; the potential pull-down unit clears the nth-stage GDL circuit through the (n + m) th-stage (m is 3 or 4 or 5) Gate; the front three stages of the GDL circuit are opened through an STV starting signal, and the rear m-stage signal clears the potential in the GDL circuit through a Reset clearing signal (Reset, rst); the middle GDL circuit is opened through the n-3 level and closed through the n +3 level, so that a narrower frame can be achieved, the manufacturing process is facilitated, and the process difficulty is reduced; on the other hand, the potential maintenance of the point q can be ensured, and the reliability and the safety are guaranteed to a certain extent.
As shown in fig. 9, as another embodiment of the present application, there is disclosed a driving method including the steps of:
s1: starting a power supply module and keeping the output of a high-level signal;
s2: receiving a frame starting signal or a superior grid driving signal;
s3: outputting a current-level gate driving signal according to the high-level signal and the frame starting signal or a superior-level gate driving signal;
s4: and after the current-stage grid driving signal is output, controlling the pull-down maintaining module to enable the level of the output end of the charging module to be at the potential of a standard low-level signal.
The current stage grid driving signal is output according to the continuous high level signal and the starting signal or the superior stage grid driving signal of the power supply module, so that the grid driving signal is ensured to be stably output, and meanwhile, the setting of a time sequence control signal and the improvement of software are reduced.
Further, after outputting the current-stage gate driving signal, the step of controlling the pull-down maintaining module to adjust the level of the output terminal of the charging module to the level of a standard low-level signal further includes:
and controlling the pull-down maintaining module to pull down the level of the output end of the output module to the potential of the standard low level signal.
In the row driving circuit, in order to prevent the electric charge residue of the row driving circuit from influencing the output of the next or next gate driving signal, the electric potential of the row driving circuit is pulled down, the electric charge residue is clear, and the stability of the waveform of the gate driving signal output is improved.
In addition, the driving method further includes the steps of:
and pulling down the level of the output end of the output module to the level of the standard low level according to a reset signal.
The step can pull down the potential of all the row driving circuits again after one frame is finished, so that the situation that even after the last row is finished, if the previous scanning line generates charges due to the influence of parasitic capacitance and the like, the previous scanning line is clear, and the stable output of the grid driving signal of the next frame is ensured.
As shown in fig. 10, as another embodiment of the present application, a display device 300 is disclosed, the display device 300 includes a display panel 200 and a driving module 400, the display panel 200 includes the row driving circuit 100 as described in any of the embodiments, and the driving module 400 and the row driving circuit 100 are used for driving display of the display panel.
It should be noted that, in the whole display panel, a plurality of row driving circuits 100 are arranged corresponding to the scan lines 210 of the display panel, each row driving circuit 100 opens the corresponding second transistor by controlling the clock signal of the clock signal module to output the corresponding gate driving signal to the scan lines 210, as explained in any of the above embodiments, the plurality of GDL circuits are provided, the plurality of GDL circuits are cascaded, so as to ensure that the GDL circuits output normally, and on the premise that the performance and reliability of the GDL circuits are ensured, the number of TFTs is relatively small, so that the risk of short circuit failure can be reduced during the process manufacturing, and a narrower frame can be achieved, and the display panel is suitable for a model design with a narrow frame and high resolution.
In addition, the row driving circuits in the above embodiments may be used in combination to output the gate driving signal together, so as to complete the display of the display panel.
It should be noted that, the limitations of each step in the present disclosure are not considered to limit the order of the steps without affecting the implementation of the specific embodiments, and the steps written in the foregoing may be executed first, or executed later, or even executed simultaneously, and as long as the present disclosure can be implemented, all the steps should be considered as belonging to the protection scope of the present application.
The technical solution of the present application can be widely applied to various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, and the above solution can be applied thereto.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. A row driver circuit, comprising:
the control end of the charging module is connected with a grid starting signal or a superior grid driving signal;
the control end of the output module is connected with the output end of the charging module, the input end of the output module is connected with the current-stage clock signal, and the output end of the output module outputs the current-stage grid driving signal;
the power supply module provides a continuous high-level signal, and the output end of the power supply module is connected with the input end of the charging module;
and the first control end of the pull-down maintaining module is connected with the output end of the power supply module, the second control end of the pull-down maintaining module is connected with the output end of the charging module, the input end of the pull-down maintaining module is connected with the output end of the charging module, and the output end of the pull-down maintaining module is connected with a standard low level signal.
2. The row driver circuit of claim 1, wherein the charge module comprises a first transistor, the output module comprises a second transistor, and the pull-down sustain module comprises a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor;
the control end of the first transistor is connected to a gate start signal or a superior gate drive signal, and the input end of the first transistor is connected to the output end of the power supply module; the output end of the first transistor is connected to the control end of the second transistor;
the input end of the second transistor is connected to the current-stage clock signal, and the output end of the second transistor outputs a current-stage grid driving signal;
the control end of the third transistor is connected with the control end of the first transistor, the input end of the third transistor is connected with the output end of the sixth transistor, and the output end of the third transistor is connected with the standard low-level signal;
a control end of the fourth transistor is connected to an output end of the sixth transistor, an input end of the fourth transistor is connected to an output end of the first transistor, and an output end of the fourth transistor is connected to the standard low-level signal;
a control end of the fifth transistor is connected to an output end of the first transistor, an input end of the fifth transistor is connected to an output end of the sixth transistor, and an output end of the fifth transistor is connected to the standard low-level signal;
the control end and the input end of the sixth transistor are respectively connected to the output end of the power supply module;
wherein a channel width-to-length ratio of the third transistor and the fifth transistor is larger than a channel width-to-length ratio of the sixth transistor.
3. The row driver circuit of claim 2, wherein the third transistor and the fifth transistor have a channel width to length ratio of 500-600/4um, and the sixth transistor has a channel width to length ratio of 35-45/4 um.
4. The row driver circuit as claimed in claim 2, wherein the pull-down sustain module comprises a seventh transistor, a control terminal of the seventh transistor is connected to a lower level gate driving signal, an input terminal of the seventh transistor is connected to the output terminal of the first transistor, and an output terminal of the seventh transistor is connected to the normal low level signal.
5. The row driver circuit of claim 2, further comprising a pull-down module comprising an eighth transistor, wherein a control terminal of the eighth transistor is connected to an output terminal of the sixth transistor, an input terminal of the eighth transistor is connected to the current stage of the gate drive signal, and an output terminal of the eighth transistor is connected to the normal low signal.
6. The row driver circuit as claimed in claim 2, wherein the row driver circuit comprises a ninth transistor, a control terminal of the ninth transistor is connected to a reset signal, an input terminal of the ninth transistor is connected to the output terminal of the first transistor, and an output terminal of the ninth transistor is connected to the normal low signal.
7. A driving method applied to the row driving circuit of any one of claims 1 to 6, comprising the steps of:
starting a power supply module and keeping the output of a high-level signal;
receiving a frame starting signal or a superior grid driving signal;
outputting a current-level gate driving signal according to the high-level signal and the frame starting signal or a superior-level gate driving signal;
and after the current-stage grid driving signal is output, controlling the pull-down maintaining module to enable the level of the output end of the charging module to be at the potential of a standard low-level signal.
8. The driving method as claimed in claim 7, wherein the step of controlling the pull-down maintaining module to maintain the level of the output terminal of the charging module to the level of a normal low level signal after outputting the current stage gate driving signal further comprises:
and controlling the pull-down maintaining module to pull down the level of the output end of the output module to the potential of the standard low level signal.
9. The driving method according to claim 7 or 8, characterized by further comprising the steps of:
and pulling down the level of the output end of the output module to the level of the standard low level according to a reset signal.
10. A display panel comprising a row driver circuit as claimed in any one of claims 1 to 6 for driving a display of the display panel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110332580.4A CN113238416A (en) | 2021-03-29 | 2021-03-29 | Line driving circuit, driving method and display panel |
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| CN202110332580.4A CN113238416A (en) | 2021-03-29 | 2021-03-29 | Line driving circuit, driving method and display panel |
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| CN105702190A (en) * | 2014-12-10 | 2016-06-22 | 乐金显示有限公司 | Gate driving circuit and display device including the same |
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