CN113238139A - Circuit fault detection method, device, equipment and computer readable storage medium - Google Patents
Circuit fault detection method, device, equipment and computer readable storage medium Download PDFInfo
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- CN113238139A CN113238139A CN202110457992.0A CN202110457992A CN113238139A CN 113238139 A CN113238139 A CN 113238139A CN 202110457992 A CN202110457992 A CN 202110457992A CN 113238139 A CN113238139 A CN 113238139A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/50—Systems or methods supporting the power network operation or management, involving a certain degree of interaction with the load-side end user applications
- Y04S10/52—Outage or fault management, e.g. fault detection or location
Abstract
The invention discloses a circuit fault detection method, which comprises the following steps: when a detection instruction is received, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result; stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result; and acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result. The invention also discloses a circuit fault detection device, equipment and a computer readable storage medium. According to the invention, the electrical state value of the preset node is detected to obtain a first detection result, a second detection result is obtained according to the first detection result and the topological position of the preset node, and the actual position of the abnormal node is obtained according to the first detection result and the second detection result, so that the efficiency and the accuracy of circuit fault detection are improved.
Description
Technical Field
The present invention relates to the field of power transmission technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for detecting a circuit fault.
Background
Electricity is an indispensable resource in daily life of people, but various circuits are easy to break down while providing power for each household, and the current method for judging the circuit equipment faults mainly adopts manual judgment according to a circuit drawing. Because electronic circuit drawings are complicated, the manual searching and judging are time-consuming and long, errors are easy to occur, and the fault delay is prolonged, the circuit drawings are checked manually at present, and the fault circuit is detected and maintained by adopting voltage detection, impedance detection and current detection, so that the efficiency is low, the fault position is not accurate enough, and the normal power utilization of people is seriously influenced.
Therefore, how to improve the efficiency of circuit fault detection and the accuracy of fault location is an urgent problem to be solved.
Disclosure of Invention
The invention mainly aims to provide a circuit fault detection method, a circuit fault detection device, circuit fault detection equipment and a computer readable storage medium, and aims to solve the problem of circuit fault detection of an electric automobile at any time and any place.
In order to achieve the above object, the present invention provides a circuit fault detection method, including the steps of:
when a detection instruction is received, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result;
stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result;
and acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
Preferably, when a detection instruction is received, acquiring a preset node in the detection instruction, detecting an electrical state of the preset node, and before the step of obtaining a first detection result, the method for detecting a circuit fault further includes:
when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting actual position information of all nodes in the target circuit diagram;
and generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
Preferably, the step of detecting the electrical state of the preset node and obtaining a first detection result comprises:
detecting an electrical state value of the preset node, and subtracting the electrical state value from a standard electrical state value to obtain an electrical state difference value;
comparing the electrical state difference value with a preset error range to obtain the first detection result;
preferably, the step of comparing the electrical state difference value with a preset error range to obtain the first detection result includes:
comparing the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, obtaining a first detection result that the preset node is normal;
and if the electrical state difference is determined to be out of the preset error range according to the comparison result, obtaining the first detection result as the preset node is abnormal.
Preferably, the step of stopping or continuing to detect all the remaining nodes according to the first detection result and the topology position of the preset node, and obtaining a second detection result includes:
if the first detection result indicates that the preset node is normal, stopping detection or continuously detecting all nodes behind the preset node according to the topological position of the preset node;
and if the first detection result is that the preset node is abnormal, stopping detection or continuously detecting all nodes positioned in front of the preset node according to the topological position of the preset node.
Preferably, if the first detection result indicates that the preset node is normal, the step of stopping detecting or continuously detecting all nodes located behind the preset node according to the topological position of the preset node includes:
if the first detection result indicates that the preset node is normal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the rearmost end, continuously detecting all nodes behind the preset node to obtain a second detection result;
and if the topological position of the preset node is the rearmost end, stopping detection.
Preferably, if the first detection result is that the preset node is abnormal, the step of stopping detecting or continuously detecting all nodes located before the preset node according to the topological position of the preset node includes:
if the first detection result is that the preset node is abnormal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the front end, continuously detecting all nodes positioned in front of the preset node to obtain a second detection result;
and if the topological position of the preset node is the foremost end, stopping detection.
Further, to achieve the above object, the present invention also provides a circuit failure detection device including:
the first detection module is used for acquiring a preset node in a detection instruction when the detection instruction is received, and detecting an electrical state value of the preset node to obtain a first detection result;
the second detection module is used for stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node so as to obtain a second detection result;
and the recording module is used for acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
Preferably, the first detection module further comprises an extraction module, the extraction module is configured to:
when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting actual position information of all nodes in the target circuit diagram;
and generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
Preferably, the first detection module is further configured to:
detecting an electrical state value of the preset node, and subtracting the electrical state value from a standard electrical state value to obtain an electrical state difference value;
and comparing the electrical state difference value with a preset error range to obtain the first detection result.
Preferably, the first detection module is further configured to:
comparing the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, obtaining a first detection result that the preset node is normal;
and if the electrical state difference is determined to be out of the preset error range according to the comparison result, obtaining the first detection result as the preset node is abnormal.
Preferably, the second detection module is further configured to:
if the first detection result indicates that the preset node is normal, stopping detection or continuously detecting all nodes behind the preset node according to the topological position of the preset node;
and if the first detection result is that the preset node is abnormal, stopping detection or continuously detecting all nodes positioned in front of the preset node according to the topological position of the preset node.
Preferably, the second detection module is further configured to:
if the first detection result indicates that the preset node is normal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the rearmost end, continuously detecting all nodes behind the preset node to obtain a second detection result;
and if the topological position of the preset node is the rearmost end, stopping detection.
Preferably, the second detection module is further configured to:
if the first detection result is that the preset node is abnormal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the front end, continuously detecting all nodes positioned in front of the preset node to obtain a second detection result;
and if the topological position of the preset node is the foremost end, stopping detection.
Further, to achieve the above object, the present invention also provides a circuit failure detection apparatus comprising: a memory, a processor and a circuit failure detection program stored on the memory and executable on the processor, the circuit failure detection program when executed by the processor implementing the steps of the circuit failure detection method as described above.
Further, to achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon a circuit failure detection program which, when executed by a processor, realizes the steps of the circuit failure detection method as described above.
The circuit fault detection method provided by the invention comprises the steps of acquiring a preset node in a detection instruction when the detection instruction is received, and detecting an electrical state value of the preset node to obtain a first detection result; stopping detecting or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result; and acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result. According to the invention, the electrical state value of the preset node is detected to obtain a first detection result, a second detection result is obtained according to the first detection result and the topological position of the preset node, and the actual position of the abnormal node is obtained according to the first detection result and the second detection result, so that the efficiency and the accuracy of circuit fault detection are improved.
Drawings
FIG. 1 is a schematic diagram of an apparatus architecture of a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a first embodiment of a circuit fault detection method according to the present invention;
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, fig. 1 is a schematic device structure diagram of a hardware operating environment according to an embodiment of the present invention.
The device of the embodiment of the invention can be a PC or a server device.
As shown in fig. 1, the apparatus may include: a processor 1001, such as a CPU, a network interface 1004, a user interface 1003, a memory 1005, a communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a wireless interface (e.g., WI-FI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the configuration of the apparatus shown in fig. 1 is not intended to be limiting of the apparatus and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, a memory 1005, which is a kind of computer storage medium, may include therein an operating system, a network communication module, a user interface module, and a circuit failure detection program.
The operating system is a program for managing and controlling the portable circuit fault detection equipment and software resources, and supports the operation of a network communication module, a user interface module, a circuit fault detection program and other programs or software; the network communication module is used for managing and controlling the network interface 1002; the user interface module is used to manage and control the user interface 1003.
In the circuit failure detection apparatus shown in fig. 1, the circuit failure detection apparatus calls a circuit failure detection program stored in a memory 1005 by a processor 1001 and performs operations in various embodiments of a circuit failure detection method described below.
Based on the hardware structure, the embodiment of the circuit fault detection method is provided.
Referring to fig. 2, fig. 2 is a schematic flow chart of a first embodiment of the circuit fault detection method of the present invention, where the method includes:
step S10, when a detection instruction is received, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result;
step S20, according to the first detection result and the topological position of the preset node, stopping detecting or continuously detecting all the remaining nodes to obtain a second detection result;
and step S30, acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
The circuit fault detection method is applied to portable circuit fault detection equipment, the circuit fault detection equipment can be a terminal or PC equipment, and for convenience of description, the circuit fault detection equipment is taken as an example for description; when the circuit fault detection equipment receives a detection instruction, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result; the circuit fault detection equipment stops detecting or continues to detect all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result; the circuit fault detection equipment acquires and records the actual position of the abnormal node according to the first detection result and the second detection result, and related circuit maintenance personnel can maintain the abnormal node according to the actual position of the abnormal node. It should be noted that the preset nodes are selected by the relevant operators according to experience, and in the man-machine interaction screen of the circuit fault detection device, the corresponding preset nodes are selected as initial nodes, and the confirmation button is clicked, so that the circuit fault detection device starts fault detection; the topological position refers to the relative position of each node in the circuit recorded by the circuit fault detection equipment, the actual position refers to the position of each node in the circuit in reality, and related maintenance personnel maintain abnormal nodes according to the actual position; the electrical state values include: voltage value, current value, and resistance value.
In the circuit fault detection method of the embodiment, when a detection instruction is received, a preset node in the detection instruction is obtained, and an electrical state value of the preset node is detected to obtain a first detection result; stopping detecting or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result; and acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result. The method comprises the steps of obtaining a first detection result by detecting an electrical state value of a preset node, obtaining a second detection result according to the first detection result and the topological position of the preset node, obtaining the actual position of an abnormal node according to the first detection result and the second detection result, and improving the efficiency and the accuracy of circuit fault detection.
The respective steps will be described in detail below:
step S10, when a detection instruction is received, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result;
in this embodiment, when the circuit fault detection device receives a detection instruction, a preset node in the detection instruction is obtained, a voltage value, a current value, and a resistance value of the preset node are detected, the detected voltage value, current value, and resistance value are respectively and correspondingly subtracted from a standard voltage value, a standard current value, and a standard resistance value, so as to obtain a voltage difference value, a current difference value, and a resistance difference value, the obtained voltage difference value, current difference value, and resistance difference value are respectively and correspondingly compared with a preset voltage error range, a preset current error range, and a preset resistance error range, and according to a comparison result, a first detection result is obtained.
Specifically, step S10 further includes:
step a, detecting an electrical state value of the preset node, and subtracting the electrical state value from a standard electrical state value to obtain an electrical state difference value;
in the step, the circuit fault detection equipment detects the electrical state value of a preset node, and subtracts the electrical state value from the standard electrical state value to obtain an electrical state difference value; for example, when detecting a fault of a railway frequency shift signal circuit, the circuit fault detection device acquires a preset node, detects an electrical state value of the preset node, and obtains a voltage value of 3V, a current value of 3A and a resistance value of 1 Ω, where a standard electrical state value corresponding to the preset node is: and the standard voltage value is 3.1V, the standard current value is 3.1A and the standard resistance value is 1 omega, and the voltage value, the current value and the resistance value which are obtained by detection are correspondingly subtracted from the standard voltage value, the standard current value and the standard resistance value respectively to obtain the voltage difference value of 0.1V, the current difference value of 0.1A and the resistance difference value of 0 omega. It should be noted that the standard electrical state value includes a standard voltage value, a standard current value, and a standard resistance value, and the electrical state difference value includes a voltage difference value, a current difference value, and a resistance difference value.
And b, comparing the electrical state difference value with a preset error range to obtain the first detection result.
In the step, after the circuit fault detection device obtains the electrical state difference value, the electrical state difference value is compared with a preset error range to obtain a comparison result, and a first detection result is obtained according to the comparison result. Such as: when the fault of the railway frequency shift signal circuit is detected, the circuit fault detection equipment obtains a voltage difference value of 0.1V, a current difference value of 0.1A and a resistance difference value of 0 omega, and a preset error range set by related researchers is assumed to comprise: the voltage error range is-0.2V to 0.2V, the current error range is-0.2A to 0.2A, the resistance error range is-0.2 omega to 0.2 omega, and the circuit fault detection equipment correspondingly compares the obtained voltage difference value, current difference value and resistance difference value with the voltage error range, current error range and resistance error range respectively to obtain a first detection result.
Further, the step of obtaining the first detection result further includes:
comparing the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, obtaining a first detection result that the preset node is normal;
in the step, the circuit fault detection equipment compares the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, the first detection result is obtained as that the preset node is normal; such as: assuming that the preset error range set by the relevant researchers includes: the voltage error range is-0.2V to 0.2V, the current error range is-0.2A to 0.2A, the resistance error range is-0.2 omega to 0.2 omega, the circuit fault detection equipment obtains a voltage difference value of 0.1V, a current difference value of 0.1A and a resistance difference value of 0 omega, the voltage difference value, the current difference value and the resistance difference value are obtained through comparison and are all in the error range, and the first detection result is that the preset node is normal. It should be noted that, the voltage difference, the current difference, and the resistance difference are within the error range, and the first detection result is that the preset node is normal.
And if the electrical state difference is determined to be out of the preset error range according to the comparison result, obtaining the first detection result as the preset node is abnormal.
In the step, the circuit fault detection equipment compares the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be out of the preset error range according to the comparison result, a first detection result is obtained as the preset node abnormality; such as: assuming that the preset error range set by the relevant researchers includes: the voltage error range is-0.05V to 0.2V, the current error range is-0.2A to 0.2A, the resistance error range is-0.2 omega to 0.2 omega, the circuit fault detection equipment obtains a voltage difference value of 0.1V, a current difference value of 0.1A and a resistance difference value of 0 omega, the voltage difference value is obtained through comparison and is out of the error range, and a first detection result is obtained and is that the preset node is abnormal.
Step S20, according to the first detection result and the topological position of the preset node, stopping detecting or continuously detecting all the remaining nodes to obtain a second detection result;
in this embodiment, the circuit fault detection device stops detecting or continues to detect all remaining nodes according to the first detection result and the topology position of the preset node to obtain a second detection result; it should be noted that, the circuit fault detection device determines whether to stop detection or continue to detect all remaining nodes in the following step according to the first detection result and the topology position of the preset node, since the circuit node is chained, the detection is started from the preset node from the foremost segment to the rearmost segment, the detection is started from the preset node, if the preset node is normal, all remaining nodes are detected in the rearmost direction, if the preset node is abnormal, all remaining nodes are detected in the foremost direction, and if the foremost segment or the rearmost segment is detected, the detection is ended.
Specifically, step S20 further includes:
c, if the first detection result indicates that the preset node is normal, stopping detecting or continuously detecting all nodes behind the preset node according to the topological position of the preset node;
in the step, the circuit fault detection device obtains a first detection result that the preset node is normal, and stops detecting or continues to detect all nodes behind the preset node according to the topological position of the preset node; it should be noted that, when the circuit fault detection device continues to detect all nodes located behind the preset node, optionally, the circuit fault detection device detects each node from the next node of the preset node according to the setting of the relevant maintenance personnel and according to the sequence of the nodes, and stops when the last end node is detected, and obtains a second detection result; optionally, the circuit fault detection device selects any node from all nodes behind the preset node for detection according to the setting of the relevant maintenance personnel, stops detecting or continues detecting all nodes behind or in front of the any node according to the obtained detection result and the topological position of the any node, and repeats the steps if the circuit fault detection device continues detecting all nodes behind or in front of the any node.
Further, step c further comprises:
if the first detection result indicates that the preset node is normal, acquiring the topological position of the preset node;
in this step, if the first detection result obtained by the circuit fault detection device indicates that the preset node is normal, the topology position of the preset node is obtained, where the topology position of the preset node includes a non-rearmost end and a rearmost end.
If the topological position of the preset node is not the rearmost end, continuously detecting all nodes behind the preset node to obtain a second detection result;
in this step, after the circuit fault detection device acquires the topology position of the preset node, if the topology position of the preset node is not the rearmost end, all nodes behind the preset node are continuously detected, and the second detection result is obtained.
And if the topological position of the preset node is the rearmost end, stopping detection.
In this step, after the circuit fault detection device acquires the topology position of the preset node, if the topology position of the preset node is the rearmost end, the detection is stopped.
And d, if the first detection result is that the preset node is abnormal, stopping detecting or continuously detecting all nodes positioned in front of the preset node according to the topological position of the preset node.
In the step, the circuit fault detection equipment obtains a first detection result that the preset node is abnormal, and stops detecting or continues to detect all nodes positioned in front of the preset node according to the topological position of the preset node; it should be noted that, when the circuit fault detection device continues to detect all nodes located before the preset node, optionally, the circuit fault detection device detects each node from the previous node of the preset node according to the setting of the relevant maintenance personnel, and stops when the foremost node is detected, and obtains a second detection result; optionally, the circuit fault detection device selects any node from all nodes before the preset node for detection according to the setting of the relevant maintenance personnel, and stops or continues to detect all nodes after or before the any node according to the obtained detection result and the topology position of the any node, and repeats the above steps if the circuit fault detection device continues to detect all nodes after or before the any node.
Further, step d further comprises:
if the first detection result is that the preset node is abnormal, acquiring the topological position of the preset node;
in this step, if the first detection result obtained by the circuit fault detection device is that the preset node is abnormal, the topology position of the preset node is obtained, where the topology position of the preset node includes a non-frontmost end and a frontmost end.
If the topological position of the preset node is not the front end, continuously detecting all nodes positioned in front of the preset node to obtain a second detection result;
in this step, after the circuit fault detection device obtains the topology position of the preset node, if the topology position of the preset node is not the frontmost end, all nodes located before the preset node are continuously detected, and the second detection result is obtained.
And if the topological position of the preset node is the foremost end, stopping detection.
In this step, after the circuit fault detection device acquires the topology position of the preset node, if the topology position of the preset node is the foremost end, the detection is stopped.
And step S30, acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
In this embodiment, the circuit fault detection device obtains and records the actual position of the abnormal node according to the first detection result and the second detection result, such as: the circuit fault detection equipment obtains the topological position of the abnormal node according to the first detection result and the second detection result, obtains the actual position of the abnormal node according to the topological position, and maintains the abnormal node according to the actual position by related maintenance personnel.
When receiving a detection instruction, the circuit fault detection device of the embodiment acquires a preset node in the detection instruction, and detects an electrical state value of the preset node to obtain a first detection result; the circuit fault detection equipment stops detecting or continues to detect all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result; the circuit fault detection equipment acquires and records the actual position of the abnormal node according to the first detection result and the second detection result, and related circuit maintenance personnel can maintain the abnormal node according to the actual position of the abnormal node; the method comprises the steps of obtaining a first detection result by detecting an electrical state value of a preset node, obtaining a second detection result according to the first detection result and the topological position of the preset node, obtaining the actual position of an abnormal node according to the first detection result and the second detection result, and improving the efficiency and the accuracy of circuit fault detection.
Further, based on the first embodiment of the circuit fault detection method of the present invention, a second embodiment of the circuit fault detection method of the present invention is proposed.
The second embodiment of the circuit failure detection method differs from the first embodiment of the circuit failure detection method in that step S10 is preceded by:
step e, when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting the actual position information of all nodes in the target circuit diagram;
and f, generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
In this embodiment, when receiving a start instruction, a circuit fault detection device acquires a target circuit diagram corresponding to the start instruction, extracts actual positions of all nodes in the target circuit diagram, generates a target circuit node topology relation table according to actual position information, and obtains topology numbers and topology positions of all nodes; it should be noted that, the target circuit node topology relation table is converted from the target circuit diagram, so that the circuit fault device can more easily obtain corresponding information from the target circuit diagram; the topology numbers are numbered in the order from the forefront to the rearmost according to the arrangement order of the nodes in the target circuit diagram so as to distinguish different nodes.
The respective steps will be described in detail below:
step e, when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting the actual position information of all nodes in the target circuit diagram;
in the step, when the circuit fault detection equipment receives a starting instruction, acquiring a corresponding target circuit diagram in the starting instruction, and extracting actual position information of all nodes in the target circuit diagram; it should be noted that the target circuit diagram is drawn by the circuit detected by the relevant maintenance personnel according to the requirement and uploaded to the circuit fault detection device, and the target circuit diagram includes the actual positions of all nodes in the circuit and the electrical relationships among all nodes.
And f, generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
In this step, the circuit fault detection device generates a target circuit node topology relationship table according to the actual position information of all nodes, and obtains the topology numbers and the topology positions of all nodes according to the target circuit node topology relationship table.
When the circuit fault detection device receives the starting instruction, the corresponding target circuit diagram in the starting instruction is obtained, the actual positions of all nodes in the target circuit diagram are extracted, the target circuit node topological relation table is generated according to the actual position information, the topological numbers and the topological positions of all the nodes are obtained, and the efficiency and the accuracy of circuit fault detection are improved.
The invention also provides a circuit fault detection device. The circuit fault detection device of the present invention includes:
the first detection module is used for acquiring a preset node in a detection instruction when the detection instruction is received, and detecting an electrical state value of the preset node to obtain a first detection result;
the second detection module is used for stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node so as to obtain a second detection result;
and the recording module is used for acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
Further, the first detection module further comprises an extraction module, and the extraction module is configured to:
when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting actual position information of all nodes in the target circuit diagram;
and generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
Further, the first detection module is further configured to:
detecting an electrical state value of the preset node, and subtracting the electrical state value from a standard electrical state value to obtain an electrical state difference value;
and comparing the electrical state difference value with a preset error range to obtain the first detection result.
Further, the first detection module is further configured to:
comparing the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, obtaining a first detection result that the preset node is normal;
and if the electrical state difference is determined to be out of the preset error range according to the comparison result, obtaining the first detection result as the preset node is abnormal.
Further, the second detection module is further configured to:
if the first detection result indicates that the preset node is normal, stopping detection or continuously detecting all nodes behind the preset node according to the topological position of the preset node;
and if the first detection result is that the preset node is abnormal, stopping detection or continuously detecting all nodes positioned in front of the preset node according to the topological position of the preset node.
Further, the second detection module is further configured to:
if the first detection result indicates that the preset node is normal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the rearmost end, continuously detecting all nodes behind the preset node to obtain a second detection result;
and if the topological position of the preset node is the rearmost end, stopping detection.
Further, the second detection module is further configured to:
if the first detection result is that the preset node is abnormal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the front end, continuously detecting all nodes positioned in front of the preset node to obtain a second detection result;
and if the topological position of the preset node is the foremost end, stopping detection.
The invention also provides a computer readable storage medium.
The computer-readable storage medium of the present invention has stored thereon a circuit failure detection program which, when executed by a processor, implements the steps of the circuit failure detection method as described above.
The method implemented when the circuit fault detection program running on the processor is executed may refer to each embodiment of the circuit fault detection method of the present invention, and details are not described here.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A circuit fault detection method, characterized in that the circuit fault detection method comprises the steps of:
when a detection instruction is received, acquiring a preset node in the detection instruction, and detecting an electrical state value of the preset node to obtain a first detection result;
stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node to obtain a second detection result;
and acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
2. The method for detecting circuit faults according to claim 1, wherein before the step of acquiring the preset node in the detection instruction and detecting the electrical state of the preset node to obtain the first detection result when the detection instruction is received, the method for detecting circuit faults further comprises:
when a starting instruction is received, acquiring a corresponding target circuit diagram in the starting instruction, and extracting actual position information of all nodes in the target circuit diagram;
and generating a target circuit node topological relation table according to the actual position information, and obtaining the topological numbers and the topological positions of all the nodes according to the target circuit node topological relation table.
3. The circuit fault detection method of claim 1, wherein the step of detecting the electrical state of the preset node and obtaining the first detection result comprises:
detecting an electrical state value of the preset node, and subtracting the electrical state value from a standard electrical state value to obtain an electrical state difference value;
and comparing the electrical state difference value with a preset error range to obtain the first detection result.
4. The circuit fault detection method of claim 3, wherein the step of comparing the electrical state difference with a preset error range to obtain the first detection result comprises:
comparing the electrical state difference value with a preset error range to obtain a comparison result, and if the electrical state difference value is determined to be within the preset error range according to the comparison result, obtaining a first detection result that the preset node is normal;
and if the electrical state difference is determined to be out of the preset error range according to the comparison result, obtaining the first detection result as the preset node is abnormal.
5. The circuit fault detection method according to claim 4, wherein the step of stopping detection or continuing detection of all remaining nodes according to the first detection result and the topological position of the preset node, and obtaining a second detection result comprises:
if the first detection result indicates that the preset node is normal, stopping detection or continuously detecting all nodes behind the preset node according to the topological position of the preset node;
and if the first detection result is that the preset node is abnormal, stopping detection or continuously detecting all nodes positioned in front of the preset node according to the topological position of the preset node.
6. The method according to claim 5, wherein if the first detection result indicates that the preset node is normal, the step of stopping detecting or continuing to detect all nodes behind the preset node according to the topological position of the preset node comprises:
if the first detection result indicates that the preset node is normal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the rearmost end, continuously detecting all nodes behind the preset node to obtain a second detection result;
and if the topological position of the preset node is the rearmost end, stopping detection.
7. The method according to claim 5, wherein if the first detection result indicates that the preset node is abnormal, the step of stopping detection or continuing to detect all nodes located before the preset node according to the topological position of the preset node comprises:
if the first detection result is that the preset node is abnormal, acquiring the topological position of the preset node;
if the topological position of the preset node is not the front end, continuously detecting all nodes positioned in front of the preset node to obtain a second detection result;
and if the topological position of the preset node is the foremost end, stopping detection.
8. A circuit fault detection device, characterized in that the circuit fault detection device comprises:
the first detection module is used for acquiring a preset node in a detection instruction when the detection instruction is received, and detecting an electrical state value of the preset node to obtain a first detection result;
the second detection module is used for stopping detection or continuously detecting all the remaining nodes according to the first detection result and the topological position of the preset node so as to obtain a second detection result;
and the recording module is used for acquiring and recording the actual position of the abnormal node according to the first detection result and the second detection result.
9. A circuit fault detection device, characterized in that the circuit fault detection device comprises: memory, processor and a circuit failure detection program stored on the memory and executable on the processor, the circuit failure detection program when executed by the processor implementing the steps of the circuit failure detection method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that a circuit failure detection program is stored thereon, which when executed by a processor implements the steps of the circuit failure detection method according to any one of claims 1 to 7.
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