CN113225109A

CN113225109A - Signal processing system and related electronic equipment

Info

Publication number: CN113225109A
Application number: CN202010062148.3A
Authority: CN
Inventors: 胡嘉怡; 尹学锋; 凌岑
Original assignee: Honor Device Co Ltd
Current assignee: Honor Device Co Ltd
Priority date: 2020-01-19
Filing date: 2020-01-19
Publication date: 2021-08-06
Anticipated expiration: 2040-01-19
Also published as: WO2021143649A3; CN113225109B; WO2021143649A2

Abstract

The application discloses a signal processing system and related electronic equipment, wherein the signal processing system comprises an antenna array, a receiver and a processor, wherein N receiving channels exist between the receiver and the antenna array, and the antenna array comprises M antennas; m, N is a positive integer, M > N. The signal sent by the base station is received by the antenna array, and then the antenna array transmits the signal to the receiver through the baseband receiving channel, and the receiver synchronously transmits the signal to the processor. Because the number of antennas of the antenna array is greater than the number of baseband receiving channels, antennas in the antenna array need to be switched, and different antennas are sequentially connected to the baseband receiving channels respectively. The total switching time length of the antenna array is a first time length, and signals received by the antenna array are transmitted to the processor within the first time length, wherein the error between the signals received by the processor and the signals received by the antenna array is smaller than a first threshold value. In this way, the multipath parameters of the overall channel can be extracted within the error range.

Description

Signal processing system and related electronic equipment

Technical Field

The present application relates to the field of communications, and in particular, to a signal processing system and a related electronic device.

Background

Multi-antenna technology is an important means to meet network capacity requirements in fifth generation wireless communication systems (5G). Different from 4G, 5G adopts a large amount of dynamic narrow beam transmission technology, and can realize high-precision matching between the receiving and transmitting of a system based on beams and the channels only when the multipath distribution of the channels in the direction domain is accurately tracked in real time, thereby completing the practice of a space-time-frequency joint equalization algorithm and ensuring the stable performance. The channel acquisition is restricted by the coherence time in the dynamic environment, the channel acquired in the coherence time can accurately extract the characteristics of multipath parameters and the like in the channel, and most multipath information is lost when the channel acquisition exceeds the range. The adoption of the antenna array to carry out spatial domain acquisition on the received signals is a necessary condition for analyzing the direction domain characteristics of the channel. Under the condition that the number of the baseband receiving channels is less than that of the antenna array elements, different antennas and a small number of channels need to be connected and disconnected at different moments by adopting a switch switching mode.

In the prior art, for channel spatial domain acquisition in a dynamic environment, the total switching duration of once switching of all array elements of an antenna array must be less than the channel coherence duration. In an environment with a Uniform distribution of Scattering points, i.e. for Uniform Scattering (US), the autocorrelation coefficient of the channel may decrease to 0 above a half-wavelength distance. Meanwhile, each antenna must receive a complete OFDM Symbol (Symbol), which means that when multiple antennas are used, each antenna needs to be switched once to keep the length of each frame of 5G downlink signals. Therefore, the multi-antenna round trip is completed once totally, and the required time may far exceed the relevant time, so that the channel sample collection of the airspace cannot be completed within the relevant time. In channel estimation, a single antenna needs to collect a complete frame to accurately calculate the channel impulse response, while the frame length in the 5G protocol is 10ms, and in addition, switching multiple antennas within 1.67ms also puts high requirements on a switch for controlling the switching speed.

These limitations have made it almost impossible to perform high-precision spatial domain acquisition and analysis on 5G channels, which has resulted in a very high performance requirement and a significant increase in the cost of the required equipment (e.g., switches) if it is only marginally feasible. Therefore, it is a research problem for those skilled in the art to develop an array antenna switching technique capable of exceeding the coherence time and accurately extracting spatial domain multipath of the time-varying channel.

Disclosure of Invention

The embodiment of the application provides a signal processing system and related electronic equipment, which can accurately extract space domain multipath data parameters of a time-varying channel and reduce the hardware requirement on the electronic equipment.

In a first aspect, the present application provides a signal processing system, which includes an antenna array, a receiver, and a processor, where there are N receive channels between the receiver and the antenna array, and the antenna array includes M antennas; m, N is a positive integer, M > N; the receiver acquires a first time length, wherein the first time length is longer than a first channel coherent time length and shorter than a second channel coherent time length; the first channel coherence duration is the coherence duration of the whole channel, and the second channel coherence duration is longer than the first channel coherence duration; the M antennas of the antenna array receive signals in the overall channel; during the first time period, the receiver controls the N receiving channels to transmit the signals received by the M antennas to the processor; wherein an error between the signal received by the processor and the signal received by the antenna array is less than a first threshold.

In the method provided by the embodiment of the application, the signal sent by the base station is received through the antenna array, then the antenna array transmits the signal to the receiver through the baseband receiving channel, and the receiver synchronously transmits the signal to the processor. Because the number of antennas of the antenna array is greater than the number of baseband receiving channels, antennas in the antenna array need to be switched, and different antennas are sequentially connected to the baseband receiving channels respectively. The total switching time length of the antenna array is a first time length, and signals received by the antenna array are transmitted to the processor within the first time length, wherein the error between the signals received by the processor and the signals received by the antenna array is smaller than a first threshold value. The processor receives the signal within the error range and extracts the multipath parameters of the overall channel according to the received signal. The first duration is set in relation to the coherence duration of the overall channel. The first time length in the prior art needs to be smaller than the coherence length of the overall channel. The embodiment of the application verifies that the coherent duration of a single path (component channel) can be longer than that of the whole channel under the condition of high-precision decomposition of the multipath channel, namely the first duration is longer than that of the first channel. And the first time length is less than the second channel coherence length under the condition that the signal error received by the processor is less than the first threshold. The method can accurately extract the multi-path parameters of the whole channel as long as the correlation of a certain path is satisfied.

In a possible implementation manner, in the first duration, the controlling, by the receiver, the N receiving channels to transmit the signals received by the M antennas to the processor includes: after K times of switching, transmitting the signals received by the M antennas to the processor through the N receiving channels, wherein: switching times K is M/N; each switching time length D is equal to the first time length/K; in one switching, the N receiving channels are configured to transmit signals received by N antennas of the M antennas to the processor. This provides a way for the receiver to switch the antennas in the antenna array. After the number of antennas of the antenna array, the number of receiving channels and the first time length are determined, the number of times required for switching the antenna array once can be calculated through the number of antennas of the antenna array and the number of receiving channels, and the time length of switching once can be calculated according to the number of times required for switching the antenna array once and the first time length.

In one possible implementation, the receiver includes a switching circuit and a controller; the transmitting the signals received by the M antennas to the processor through the N receiving channels after the K times of switching includes: controlling the switch circuit to switch for K times through the controller according to the first time length, and enabling the signals received by the M antennas to pass through the N receiving channels to the processor; in one switching, the switch circuit is used for communicating N antennas in the M antennas with the N receiving channels. This approach provides a hardware module for the receiver to switch the antennas in the antenna array. The receiver controls the switch circuit to switch the antennas of the antenna array through the controller, and the switch circuit is communicated with the antennas and the receiving channels in the antenna array.

In a possible implementation manner, if the first duration is greater than or equal to the second channel coherence duration, an error between the signal received by the processor and the signal received by the antenna array is greater than or equal to the first threshold in the first duration; if the first time length is less than the second channel coherence time length, the error between the signal received by the processor and the signal received by the antenna array is less than the first threshold value within the first time length. This way the coherence duration of the second channel is characterized. The second channel coherence duration may be regarded as a critical value, and when the first duration is greater than or equal to the second channel coherence duration, an error between the signal received by the processor and the signal received by the antenna array exceeds a preset error range.

In a possible implementation manner, when the first duration is a first value, if an error between a power delay spectrum of an overall channel reconstructed according to the first duration and an actual power delay spectrum of the overall channel is less than or equal to a second threshold, a second channel coherence duration is greater than or equal to the first value; otherwise, the second channel coherence length is less than the first value. This way it is described how the second channel coherence length is obtained. The second channel coherence length is determined by the error between the reconstructed power delay spectrum of the overall channel and the actual power delay spectrum of the overall channel. The power delay spectrum of the overall channel can be simulated and reconstructed through the first time length, and when the power delay spectrum of the overall channel reconstructed by the first numerical value meets an error condition, the second channel coherent time length covers the numerical value, namely the second channel coherent time length is greater than or equal to the first numerical value; if the error condition is not satisfied, the second channel coherence length does not cover the value, i.e., the second channel coherence length is smaller than the first value.

In a possible implementation manner, before the receiver acquires the first time length, the processor calculates the first time length according to environment information data of an overall channel; the processor calculates the first duration according to the environmental information data of the overall channel, and includes: the processor draws an analog measurement scene according to the environment information number of the integral channel, wherein the analog measurement scene comprises a transmitting end for transmitting signals, the signal processing system for receiving the signals and a scatterer; the processor acquires the coherence duration of the overall channel according to the simulation measurement scene, and determines that the value of the first duration is a second value, wherein the second value is L times of the coherence duration of the overall channel, L is an integer greater than 1, and the second value is smaller than the maximum coherence duration in the component channel of the overall channel; the processor reconstructs the power time delay spectrum of the integral channel according to the second numerical value; and if the error between the reconstructed power delay spectrum and the actual power delay spectrum of the whole channel is smaller than the second threshold, the processor determines that the value of the first duration is the second value. This implementation describes a way for the processor to calculate the first duration. The processor draws a simulation measurement scene according to the environmental information data of the whole channel, and compares the error of the reconstructed power delay spectrum and the actual delay spectrum in the simulation measurement scene so as to determine the first time length under the condition of meeting the error condition.

In a possible implementation manner, if an error between the reconstructed power delay profile and the power delay profile of the entire channel is greater than or equal to the second threshold, the processor further includes: determining that the value of the first duration is a third value, wherein the third value is smaller than the second value; reconstructing a power time delay spectrum of the whole channel according to the third numerical value; and if the error between the reconstructed power delay spectrum and the power delay spectrum of the whole channel is smaller than the second threshold, determining the value of the first duration to be the third value. The implementation mode describes that when the second value of the first duration does not meet the error condition, the value of the first duration is reduced to be a third value, and the power time delay spectrum is reconstructed again through the third value for comparison until the value of the first duration meets the error condition.

In a possible implementation manner, the reconstructing, by the processor, the power delay profile of the entire channel according to the second value includes: the processor simulates the receiver to switch the connection and disconnection between the M antennas and the N receiving channels according to the second numerical value in the simulation measurement scene to obtain the channel impulse response of the whole channel; the processor carries out parameter estimation on the simulated channel impulse response according to a preset algorithm to obtain the multipath parameters of the whole channel; and the processor reconstructs the power time delay spectrum of the whole channel according to the multipath parameters. This implementation provides a specific way for the processor to reconstruct the power delay profile of the overall channel from the first time length. And calculating the channel response of the simulated measurement scene through the first time length, and then acquiring the multipath parameters according to a preset algorithm, thereby obtaining a reconstructed power time delay spectrum.

In one possible implementation, the actual power-delay spectrum of the overall channel is plotted by calculating the channel response in the simulated measurement scenario. This implementation provides that the actual power delay profile of the overall channel is plotted in simulation in the measurement scenario.

In a second aspect, the present application provides an electronic device comprising: the antenna system comprises an antenna array, a receiver, a processor and a memory, wherein N receiving channels exist between the receiver and the antenna array, and the antenna array comprises M antennas; m, N is a positive integer, M > N; the processor is coupled with the receiver, the memory for storing computer program code, the computer program code including computer instructions, the electronic device to invoke the computer instructions to perform: the receiver acquires a first time length, wherein the first time length is longer than a first channel coherent time length and shorter than a second channel coherent time length; the first channel coherence duration is the coherence duration of the whole channel, and the second channel coherence duration is longer than the first channel coherence duration; the M antennas of the antenna array receive signals in the overall channel; during the first time period, the receiver controls the N receiving channels to transmit the signals received by the M antennas to the processor; wherein an error between the signal received by the processor and the signal received by the antenna array is less than a first threshold.

In a possible implementation manner, in the first duration, the controlling, by the receiver, the N receiving channels to transmit the signals received by the M antennas to the processor includes: after K times of switching, transmitting the signals received by the M antennas to the processor through the N receiving channels, wherein: switching times K is M/N; each switching time length D is equal to the first time length/K; in one switching, the N receiving channels are configured to transmit signals received by N antennas of the M antennas to the processor.

In one possible implementation, the receiver includes a switching circuit and a controller; the transmitting the signals received by the M antennas to the processor through the N receiving channels after the K times of switching includes: controlling the switch circuit to switch for K times through the controller according to the first time length, and transmitting signals received by the M antennas to the processor through the N receiving channels; in one switching, the switch circuit is used for communicating N antennas in the M antennas with the N receiving channels.

In a possible implementation manner, if the first duration is greater than or equal to the second channel coherence duration, an error between the signal received by the processor and the signal received by the antenna array is greater than or equal to the first threshold in the first duration; if the first time length is less than the second channel coherence time length, the error between the signal received by the processor and the signal received by the antenna array is less than the first threshold value within the first time length.

In a possible implementation manner, when the first duration is a first value, if an error between a power delay spectrum of an overall channel reconstructed according to the first duration and an actual power delay spectrum of the overall channel is less than or equal to a second threshold, a second channel coherence duration is greater than or equal to the first value; otherwise, the second channel coherence length is less than the first value.

In a possible implementation manner, before the receiver acquires the first time length, the processor calculates the first time length according to environment information data of an overall channel; the processor calculates the first duration according to the environmental information data of the overall channel, and includes: the processor draws an analog measurement scene according to the environment information number of the integral channel, wherein the analog measurement scene comprises a transmitting end for transmitting signals, the signal processing system for receiving the signals and a scatterer; the processor acquires the coherence duration of the overall channel according to the simulation measurement scene, and determines that the value of the first duration is a second value, wherein the second value is L times of the coherence duration of the overall channel, L is an integer greater than 1, and the second value is smaller than the maximum coherence duration in the component channel of the overall channel; the processor reconstructs the power time delay spectrum of the integral channel according to the second numerical value; and if the error between the reconstructed power delay spectrum and the actual power delay spectrum of the whole channel is smaller than the second threshold, the processor determines that the value of the first duration is the second value.

In a possible implementation manner, if an error between the reconstructed power delay profile and the power delay profile of the entire channel is greater than or equal to the second threshold, the processor further includes: determining that the value of the first duration is a third value, wherein the third value is smaller than the second value; reconstructing a power time delay spectrum of the whole channel according to the third numerical value; and if the error between the reconstructed power delay spectrum and the power delay spectrum of the whole channel is smaller than the second threshold, determining the value of the first duration to be the third value.

In a possible implementation manner, the reconstructing, by the processor, the power delay profile of the entire channel according to the second value includes: the processor simulates the receiver to switch the connection and disconnection between the M antennas and the N receiving channels according to the second numerical value in the simulation measurement scene to obtain the channel impulse response of the whole channel; the processor carries out parameter estimation on the simulated channel impulse response according to a preset algorithm to obtain the multipath parameters of the whole channel; and the processor reconstructs the power time delay spectrum of the whole channel according to the multipath parameters.

In one possible implementation, the actual power-delay spectrum of the overall channel is plotted by calculating the channel response in the simulated measurement scenario.

In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which includes computer instructions, and when the computer instructions are executed on an electronic device, the electronic device is caused to execute a method for signal processing provided by the first aspect of the embodiment or any implementation manner of the first aspect of the present application.

In a fourth aspect, the present application provides a computer program product, which when run on an electronic device, causes the electronic device to execute the method for signal processing provided in the first aspect of the present application or any implementation manner of the first aspect.

In a fifth aspect, the present application provides a chip system, which includes a processor, configured to enable a network device to implement the functions referred to in the first aspect or the second aspect, for example, to generate or process information referred to in the authentication method. In one possible design, the system-on-chip further includes a memory for storing program instructions and data necessary for the data transmission device. The chip system may be constituted by a chip, or may include a chip and other discrete devices.

It is to be understood that the advantageous effects of the second aspect, the third aspect, the fourth aspect and the fifth aspect provided above can refer to the advantageous effects in the signal processing system provided by the first aspect, and are not described herein again.

Drawings

FIG. 1 is a diagram of a system architecture according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

FIG. 3 is a schematic flow chart of a method provided by an embodiment of the present application;

FIG. 4 is a schematic flow chart of yet another method provided by an embodiment of the present application;

fig. 5 is a measurement scenario diagram of a method provided in an embodiment of the present application;

6-9 are graphs of relationships of a method provided by embodiments of the present application;

fig. 10 is a measurement scenario diagram of another method provided by an embodiment of the present application;

11-12 are graphs of relationships for yet another method provided by an embodiment of the present application;

fig. 13 is a schematic structural diagram of a chip according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described in detail and clearly with reference to the accompanying drawings. In the description of the embodiments herein, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" in the text is only an association relationship describing an associated object, and means that three relationships may exist, for example, a and/or B may mean: three cases of a alone, a and B both, and B alone exist, and in addition, "a plurality" means two or more than two in the description of the embodiments of the present application.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as implying or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of embodiments of the application, unless stated otherwise, "plurality" means two or more.

The electronic device related in the embodiment of the present application may be a mobile phone, a tablet Computer, a desktop Computer, a laptop Computer, a notebook Computer, an Ultra-mobile Personal Computer (UMPC), a handheld Computer, a netbook, a Personal Digital Assistant (PDA), a wearable electronic device, a virtual reality device, and the like.

First, some terms in the present application are explained so as to be easily understood by those skilled in the art.

(1) SAGE algorithm: all are called Generalized spatial maximum Expectation algorithm (SAGE) algorithm). A high-precision parameter estimation algorithm has high convergence speed and small error of an estimated value. In the implementation of the application, the SAGE is not only used for parameter estimation, but also can be used as a verification mode to reconstruct the power delay spectrum PDP of the signal, perform error analysis with the actual PDP, and verify whether the current switching duration is within the error range.

(2) Overall channel: the overall environment constitutes a channel. The coherence time of the whole channel is related to the position of the transmitting end, the position of the receiving end and the position and the number of scatterers.

(3) Component channel: the component channel is a channel formed by a part of the environment, compared with the whole channel. The coherence duration of a component channel is related to the position of the transmitting end, the position of the receiving end, the position and number of scatterers. Wherein the scatterers of the component channels are part of the scatterers in the overall channel.

(4) Channel coherence duration: the coherent duration is the maximum time difference range in which the channel is kept constant, the same signal at the transmitting end reaches the receiving end within the coherent time, the fading characteristics of the signals are completely similar, and the receiving end is regarded as a signal. That is, the coherence duration refers to a time interval during which two arriving signals have strong correlation and the channel characteristics do not change significantly during the coherence duration. In the embodiment of the present application, the channel coherence duration is the coherence duration of the entire channel.

(5) Golden section method: also known as the medium-to-external ratio, refers to dividing a line segment into two parts, where the ratio of one part to the total length is equal to the ratio of the other part to the one part. The ratio is an irrational number, and the approximation of the first three digits is 0.618, so it is also called 0.618 farad. In the embodiment of the present application, the golden section method is used for cutting a switching duration interval, after a switching duration interval is selected, the golden section method is used for cutting the switching duration interval, and then another smaller switching duration interval is determined.

Next, in order to facilitate understanding of the embodiments of the present application, the technical problems to be solved by the embodiments of the present application and the corresponding application scenarios are specifically analyzed below.

The existing theory considers that for channel airspace acquisition in a dynamic environment, the total switching time length of once switching of all array elements of an antenna array is necessarily smaller than the coherence time length of an integral channel. If the coherent time length of the whole channel is exceeded, the signals collected by the antenna array cannot be regarded as the same signal, and the high-precision collection of the channel data is difficult. In the environment of a uniform distribution of scattering points, i.e. US, the autocorrelation coefficient of the channel may decrease to 0 above a half wavelength distance. This means that in the millimeter wave case, when there is a fast moving object in a complex scattering environment, it may result in the coherence length being in the order of ms.

Each antenna must receive a complete OFDM Symbol (Symbol), which means that when multiple antennas are used, each antenna needs to be switched once to keep the length of each frame of 5G downlink signals. Therefore, the antenna array generally completes one-time multi-antenna round inspection, and the required time may far exceed the coherence duration of the whole channel, so that the channel sample collection of the airspace cannot be completed within the coherence duration of the whole channel. According to the calculation of the prior art, when the user drives to the base station at a speed of 100Km/h, the coherence time of the whole channel is only 1.67ms in the case of 2.6GHz radio frequency transmission, which is smaller in the higher frequency band. Considering that a single antenna needs to collect a complete frame to accurately calculate the channel impulse response when channel estimation is performed, the frame length in the 5G protocol is 10ms, and moreover, switching multiple antennas within 1.67ms also puts high requirements on a switch for controlling the switching speed. These limitations have made it almost impossible to perform high-precision spatial domain acquisition and analysis on 5G channels, which has resulted in a very high performance requirement and a significant increase in the cost of the required equipment (e.g., switches) if it is only marginally feasible.

Therefore, aiming at the technical problems, the application mainly solves the problem of how to accurately extract the spatial domain multipath of the time-varying channel under the condition that the switching time of the antenna array exceeds the coherent time of the whole channel. The method can reduce the switching speed among multiple antennas in the antenna array, and the requirement of meeting the requirement of overhigh hardware caused by short switching time length is omitted.

In view of the technical problems in the foregoing solutions, a system architecture to which the signal processing method in the present application is applied is exemplarily listed below, as shown in fig. 1, and fig. 1 shows a system architecture related to an embodiment of the present application. The following specifically analyzes and solves the technical problems in the above-mentioned schemes by combining the signal processing system architecture provided in the present application and a signal processing method flow provided based on the signal processing system architecture. In the system architecture of signal processing, a transmitting end device 11, a receiving end device 12, and a scatterer 13 may be included. The transmitting end device 11 may transmit a data signal to the receiving end device 12.

Wherein,

the transmitting device 11 may be a 5G Base Station, an NR Base Station, etc., where the Base Station may be a Base Transceiver Station (BTS) in a Time Division Synchronous Code Division Multiple Access (TD-SCDMA) system, or may be an evolved Node B (eNB) in a Long Term Evolution (Long Term Evolution, LTE) system, or a gbb in a 5G system or a New Radio (NR) system. In addition, the base station may also be a Transmission Receiving Point (TRP), a Central Unit (CU), or other network entities. In addition, in a distributed base station scenario, the transmitting end device 11 may be a Baseband processing Unit (BBU) and a Radio frequency Unit (RRU), and may be a Baseband pool BBU pool and a Radio frequency Unit RRU in a Cloud Radio Access Network (CRAN) scenario. The transmitting end device 11 may also be a network composed of a plurality of access nodes, and may implement functions such as a wireless physical layer function, resource scheduling, and wireless resource management.

The receiving end device 12 may be stationary or mobile. The receiving end device 12 may be an antenna array, and may also be a server or a terminal device installed with a functional module having the antenna array, where the server may include, but is not limited to, a backend server, a component server, a data processing server, a storage server, or a computing server, and the server may communicate with multiple devices through the internet. The terminal device may be a device located at the outermost periphery of a network in a computer network, such as a communication terminal, a mobile device, a User terminal, a mobile terminal, a wireless communication device, a portable terminal, a User agent, a User Equipment, a service device, or a User Equipment (UE), and is mainly used for data input, output or display of a processing result, and may also be a software client, an application program, and the like installed or run on any one of the above devices. For example, the terminal may be a mobile phone, a cordless phone, a smart watch, a wearable device, a tablet device, a handheld device with wireless communication capabilities, a computing device, an in-vehicle communication module, a smart meter or other processing device connected to a wireless modem, and so forth.

In this embodiment, the receiving end device 12 may be a measuring device, and is configured to perform channel data acquisition on a channel. The receiving end device 12 collects the data signal sent by the transmitting end device 11 through the antenna array, a plurality of scatterers 13 are arranged between the receiving end device 12 and the transmitting end device 11, and due to the difference of the direction, the angle, the number of the passing scatterers and the like of the signal transmitted by the transmitting end device 11, a multipath effect is generated, so that the time for the signal to reach the receiving end device 12 is different. The receiving end device 12 completes receiving the signal through the antenna array within the overall switching duration, where the overall switching duration of the antenna array is greater than the coherence duration of the overall channel. The embodiment of the application verifies that the correlation duration of a single path may be longer than the correlation duration of the entire channel under the condition of performing high-precision decomposition on the multipath, so that the receiving end device 12 can complete signal reception and complete accurate acquisition of channel data under the condition that the total switching duration is longer than the channel correlation duration.

Next, an exemplary receiving-end device 12 provided in the following embodiments of the present application is described.

Fig. 2 shows a schematic structural diagram of the receiving-end device 12.

The following describes an embodiment specifically by taking the receiving-end device 12 as an example. It should be understood that the receiving end device 12 may have more or fewer components than shown, may combine two or more components, or may have a different configuration of components. The various components shown in the figures may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and/or application specific integrated circuits.

The receiving end device 12 may include an antenna array 201, a receiver 202, a processor 203, and a baseband receive channel 204. Optionally, a memory may also be included. The antenna array 201 and the receiver 202 transmit signals through a baseband receiving channel 204, and the receiver 202 is coupled to the processor 203. Wherein,

the antenna array 201 includes a plurality of antennas for receiving and transmitting signals.

The receiver 202 includes a switching circuit 205 and a controller 206. The switch circuit 205 is configured to switch the operating states (connected and disconnected states) of the antennas in the antenna array 201, and the controller 206 is configured to control the switch circuit 205 to control the connected and disconnected states, the connection time and disconnection time, and the like of all the antennas in the antenna array 201.

The antenna array 201 and the receiver 202 transmit signals through a baseband receiving channel 204. Where the number of antennas in antenna array 201 is greater than the number of baseband receive channels 204. The connection and disconnection of the different antennas 201 and baseband reception channels 205 can be switched by the switching circuit 205.

Processor 203 may include one or more processing units, such as: the processor 203 may include a Baseband Processor (BP), an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a memory, a video codec, a Digital Signal Processor (DSP), and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate devices or may be integrated into one or more processors.

The baseband receive path 204 may be a physical interface, port. May be configured on the receiver 202.

The antenna array 201, the receiver 202, the processor 203, and the baseband receiving channel 204 may be implemented separately as a plurality of circuits, or may be combined with each other to form a chip, and the present application does not limit the combination structure of each functional module in the receiving end device 12.

In the method for processing a signal, the receiver 202 receives a signal sent by the transmitting end device 11 through the antenna array 201, and in a first time period, the receiver 202 receives the signal of the antenna array 201 through the baseband receiving channel 204 and transmits the signal to the processor 203, where the number of antennas in the antenna array 201 is greater than the number of the baseband receiving channels 204, and at this time, the controller 206 needs to control the switch circuit 205 to switch the antennas in the antenna array 201 to control different antennas to be connected to and disconnected from the baseband receiving channels. The first duration is the total time for all antennas in the antenna array 201 to switch once, and the first duration is longer than the coherence duration of the entire channel. The output of the signal is completed by the receiver 202 within the first time period, and the error between the signal received by the processor 203 and the signal received by the antenna array 201 is smaller than the first threshold.

The above briefly describes a system architecture and a receiving end device structure for signal processing, and the following introduces an embodiment related to the present application, in which a base station is used as a transmitting end device, and a receiving end device includes an antenna array, a receiver and a processor, to describe in detail how to solve the technical problem of accurately extracting spatial domain multipath of a time-varying channel when the total switching duration of the antenna array exceeds the channel coherence duration. As shown in fig. 3, a signal processing method provided in an embodiment of the present application may include the following steps:

step S301: the receiver acquires a first time length, wherein the first time length is longer than a first channel coherent time length and shorter than a second channel coherent time length; the first channel coherence duration is the coherence duration of the overall channel.

Specifically, the receiver obtains a first time duration, which is a total switching time duration for switching all antennas of the antenna array for one round. For example, the antenna array includes 16 antennas, if two antennas are switched at a time, all antennas need to be switched 8 times in one round, and if the first duration acquired by the receiver is 4 ms, the antennas are switched every 4 ÷ 8 ÷ 0.5 ms. If four antennas are switched at a time, all antennas need to be switched 4 times in one round, and if the first duration acquired by the receiver is 4 ms, the switching is performed every 4 ÷ 4 — 1 ms.

The first time length is longer than the first channel coherent time length and shorter than the second channel coherent time length; the first channel coherence duration is the coherence duration of the overall channel. The overall channel is a channel formed by the overall environment, that is, a transmitting end device and a receiving end device, and a channel formed by all scatterers in the environment. The second channel coherence duration may be a maximum coherence duration of a component channel of the entire channel, where the component channel is a channel formed in a part of the environment, that is, a channel formed by the transmitting end device, the receiving end device, and a part of scatterers in the environment.

Because the coherent time length of a single path (component channel) can be longer than that of the whole channel under the condition of carrying out high-precision decomposition on the multipath channel, the multipath data in the channel can be completely collected under the condition that the total switching time length of one round of antenna switching is longer than that of the whole channel.

Optionally, the manner of acquiring the first time length by the receiver may be acquired by other devices, or may be acquired by calculation of a processor. The specific manner of calculating the first duration can be seen in fig. 4 and the detailed description about fig. 4.

Step S302: signals are received in an overall channel through an antenna array.

Specifically, the receiver receives a signal in the overall channel through the antenna array, where the signal may be a 5G downlink signal transmitted by the base station.

A plurality of scatterers may be provided between the receiving end device and the base station, and due to differences in the direction and angle of signals transmitted by the base station, the signals are no longer transmitted through the same transmission path, and other transmission paths may occur, resulting in different times for the signals to reach the antenna array. The signals received by the antenna array are superposed after passing through a plurality of propagation paths.

Step S303: and within the first time length, the antenna array transmits signals received by the antenna array through the baseband receiving channels, and the number of antennas of the antenna array is greater than that of the baseband receiving channels.

Specifically, after the antenna array receives the signal in the overall channel, the receiver receives the signal of the antenna array through the baseband receiving channel and transmits the signal to the processor within the first time period. The antenna array is connected with a baseband receiving channel in the receiver, the receiver receives signals through the baseband receiving channel, and the receiver controls the antennas in the antenna array to be connected with the baseband receiving channel, wherein the number of the antennas in the antenna array is larger than that of the baseband receiving channel. The controller may control the antennas connected to the baseband receive path, as well as the timing, spacing, etc. of the connections.

Because the number of antennas of the antenna array is greater than the number of baseband receiving channels, when the receiver transmits signals through the baseband receiving channels, the antennas in the antenna array need to be switched and are sequentially connected with the baseband receiving channels. The receiver switches the antennas in the antenna array by using the radio frequency switch, and controls the connection and disconnection time of different antennas and the baseband receiving channel. And any antenna in the antenna array is connected with the baseband receiving channel, and after a switching duration or a preset data volume is transmitted, the antenna connected with the baseband receiving channel in the antenna array is switched through the radio frequency switch.

After the number of antennas of the antenna array, the number of receiving channels and the first time length are determined, the number of times required for switching the antenna array once can be calculated through the number of antennas of the antenna array and the number of receiving channels, and the time length of switching once can be calculated according to the number of times required for switching the antenna array once and the first time length. That is, there are N receive channels between the receiver and the processor, and the antenna array includes M antennas; wherein M, N is a positive integer and M > N. The receiver controls the antennas in the antenna array to switch for K times, and transmits signals received by the M antennas to the processor through the N receiving channels, wherein: switching times K is M/N; each switching time length D is equal to the first time length/K; in one switching, the N receiving channels are configured to transmit signals received by N antennas of the M antennas to a receiver, and the receiver synchronously transmits the signals to the processor.

For example, the first time duration is a total switching time duration of switching all antennas of the antenna array for one round. Illustratively, there are 16 antennas in the antenna array, antenna 1, antenna 2, …, and antenna 16, and there are two baseband receive paths connected to the processor. The first duration of the antenna array is 4 milliseconds. All antennas need to be switched 8 times in one turn, and the switching time duration of one time can be 0.5 ms. Firstly, an antenna 1 and an antenna 2 in an antenna array are connected with a baseband receiving channel to transmit signals, the switching time length is 0.5 millisecond, and after 0.5 millisecond, a receiver switches an antenna 3 and an antenna 4 to be connected with the baseband receiving channel to transmit signals; after another 0.5 milliseconds, the receiver switches the connection of the antenna 5 and the antenna 6 with the baseband receiving channel to transmit signals; … … are provided. And (4) periodically switching, and switching all the antennas of the whole antenna array once and for a whole time for 4 milliseconds to complete one round of switching. Within 4 milliseconds, the receiver receives the signals received by the antenna array through the baseband receiving channel, and the receiver synchronously transmits the received signals to the processor.

In one embodiment, the receiver comprises a switch circuit and a controller, wherein the controller controls the switch circuit to switch for K times according to a first time length, and signals received by the M antennas are transmitted through the N receiving channels; in one switching, the switch circuit is used for communicating N antennas in the M antennas with N receiving channels.

Step S304: the processor receives a signal, wherein an error between the signal received by the processor and the signal received by the antenna array is less than a first threshold.

Specifically, during the first time period, the receiver receives a signal received by the antenna array through the baseband receiving channel, and the processor receives the signal through the receiver. Wherein the error between the signal received by the processor and the signal received by the antenna array is less than a first threshold.

The first time length is longer than the coherent time length of the whole channel and shorter than the coherent time length of the second channel. If the first time length is greater than or equal to the second channel coherence time length, the error between the signal received by the processor and the signal received by the antenna array is greater than or equal to a first threshold value in the first time length; if the first time length is less than the second channel coherence time length, the error between the signal received by the processor and the signal received by the antenna array is less than a first threshold value within the first time length. That is, the second channel coherence duration is a critical value related to the predetermined error value, and when the first duration exceeds the critical value, the error of the signal received by the processor is greater than the predetermined first threshold, and the error condition is not satisfied.

By implementing the embodiment of the application, the receiver receives the signal sent by the base station through the antenna array, and then transmits the signal to the processor through the baseband receiving channel, and because the number of the antennas of the antenna array is greater than that of the baseband receiving channel, the antennas in the antenna array need to be switched, so that different antennas are respectively connected with the baseband receiving channel in sequence. The total switching time length of the antenna array is a first time length, and signals received by the antenna array are transmitted to the processor within the first time length, wherein the error between the signals received by the processor and the signals received by the antenna array is smaller than a first threshold value. The processor receives the signal within the error range and extracts the multipath parameters of the overall channel according to the received signal. The first duration is set subject to the coherence duration of the overall channel. The overall switching duration in the prior art needs to be smaller than the coherence duration of the overall channel. The embodiment of the application verifies that under the condition of carrying out high-precision decomposition on the multipath channel, the coherent time length of a single path (component channel) can be longer than the coherent time length of the whole channel and is shorter than the maximum coherent time length of the component channel of the whole channel within an error range, so that the possibility that the multipath parameters of the whole channel can be accurately extracted as long as the correlation of a certain path is met is provided.

One of the method flows of the specific calculation manner of the first duration is exemplarily described as follows:

step S401: and drawing a measurement scene, and acquiring an actual power delay spectrum PDP of the measurement scene.

Specifically, the processor first obtains data of the positions of the transmitting end and the receiving end, the number and the positions of the scatterers, and the like, wherein the obtaining mode may be manual input by a user, or obtained from other devices, or obtained by automatic measurement of the processor. The measurement scene is drawn according to the acquired data, and the drawing effect can be as shown in fig. 5. The channel impulse response CIR in the measurement scenario is calculated from the measurement scenario analog signal transmission in fig. 5. The power delay profile PDP of the channel is plotted against the channel impulse response CIR, as shown in fig. 6, fig. 6 exemplarily showing the power delay profile PDP in the measurement scenario of fig. 5. The delay is the time difference of the signal arriving at the receiving end, the channel PDP can be regarded as the superposition of the respective power spectrums of multiple paths, and the delay of each path is different because the directions of different paths and the number of the experienced scatterers are different. Where each peak in fig. 6 can be considered as a power spectrum of a path, the data of the peak indicates the strength of the signal transmitted through the path.

The PDP and the frequency domain autocorrelation coefficients are mutually Fourier transform pairs, the inverse Fourier transform of each power spectrum is transformed into the autocorrelation function of the path, and therefore the autocorrelation function of the whole channel is also complex domain superposition of the autocorrelation functions of a plurality of paths. Since the radio wave propagation channel can be regarded as a linear system, it is formed by combining a plurality of statistically independent Multipath Components (Multipath Components). Thus, the autocorrelation characteristics of each multipath component collectively determine the autocorrelation characteristics of the entire channel.

In one embodiment, the actual power delay profile PDP of the channel may be replaced by formal measurement data of the channel, that is, the processor may directly obtain the actual power delay profile PDP of the channel.

Step S402: and performing coherence analysis on the measurement scene.

Specifically, after the processor draws a measurement scene, the processor simulates the sending and receiving of signals according to the drawn measurement scene, and performs coherence analysis on the signals received by the receiving end. The coherence analysis comprises temporal coherence and spatial coherence, wherein the temporal coherence describes the relation between the correlation duration and the autocorrelation coefficient, and the spatial coherence describes the relation between the coherence distance and the autocorrelation coefficient. The correlation duration is proportional to the coherence distance, which is equal to the product of the correlation duration and the moving speed of the receiving end. For example, please refer to fig. 7 for spatial coherence. Fig. 7 illustrates an overall coherence curve of a channel.

Then, the multi-path component of the measuring scene is analyzed in a coherence manner, and the overall channel is separated by changing the number of scatterers in the measuring scene, so that a plurality of multi-path component channels are separated. The processor obtains the number and/or angle of scatterers input by the user. The signals received by the receiving end are subjected to coherence analysis under different conditions. For example, the number of all scatterers of the measurement scene is 100, and the processor obtains a comparison graph of the overall coherence of the measurement scene and the coherence of the multipath component by performing coherence analysis on 1 scatterer, 10 scatterers, and 50 scatterers. Please refer to fig. 8. Curve 1 is the coherence of the signal in the measurement scenario of 1 scatterer, curve 2 is the coherence of the signal in the measurement scenario of 10 scatterers, curve 3 is the coherence of the signal in the measurement scenario of 50 scatterers, and curve 4 is the coherence of the signal in the measurement scenario of 100 scatterers (i.e. the coherence analysis of the whole measurement scenario). In the existing algorithm, the switching duration is less than the minimum coherence duration of the entire channel, but in the case of performing high-precision decomposition on multipath, as shown in fig. 8, the correlation duration of a single path may be greater than the correlation duration of the entire channel, so that the possibility of accurately extracting the multipath parameter is provided as long as the correlation of a certain path is satisfied.

Step S403: according to the coherence analysis, the coherence distance or the correlation duration under a certain autocorrelation coefficient (above 0) is selected.

Specifically, after performing overall coherence analysis on the measurement scene, the processor selects a coherence distance under a certain autocorrelation coefficient (above 0) according to the coherence analysis. The autocorrelation coefficient represents the degree of correlation between values of the same signal at any two different moments. Illustratively, an autocorrelation coefficient between 0 and 0.3 may represent a micro correlation, between 0.3 and 0.5 may represent a real correlation, between 0.5 and 0.8 may represent a significant correlation, and so on.

And selecting the coherence distance of the autocorrelation coefficient according to the self requirement. For example, taking fig. 7 as an example, more than 0 autocorrelation coefficient 0.4 may be selected, and when the autocorrelation coefficient is 0.4, the coherence distance of the curve is about 0.4. When the autocorrelation coefficient is 0.2, the coherence length of the curve is about 0.45. That is, the coherence distance to be selected by the coherence analysis may be 0.4, 0.45, or another coherence coefficient of 0 or more. The correlation duration passing through the selected coherence distance is the lower bound of the first duration.

Step S404: and selecting a second value according to the coherent distance or the relevant time length, wherein the second value is the total switching time length of all antennas in the antenna array for switching one round, inputting the second value into the measurement scene, and generating the reconstructed PDP according to the SAGE algorithm.

Specifically, after the processor selects the coherence distance or the correlation duration under a certain autocorrelation coefficient (above 0), a second value is selected according to the coherence distance or the correlation duration. The correlation duration is equal to the ratio of the coherent distance to the moving speed of the receiving end, and the second value is the total switching duration of all antennas in the antenna array for one switching round. The second value is input into the measurement scenario and a reconstructed PDP is generated according to the SAGE algorithm.

More specifically, according to SAGE algorithm, a measurement scene is cut into an individual path observation value with coherent characteristics, the total switching duration of one round of switching of all antennas in an antenna array is a second numerical value, and antenna switching and signal transmission are simulated. Obtaining a series of channel impulse response CIRs in a measurement scene, inputting the channel impulse response CIRs into an SAGE algorithm, carrying out parameter estimation on an observed value of a single path of a coherent characteristic, wherein the estimated parameters comprise data of time delay, Doppler frequency shift, direction, complex loss coefficient and the like, and carrying out signal reconstruction according to the obtained estimation result to generate a reconstructed PDP.

For example, the processor selects the coherence distance, denoted by d, at some autocorrelation coefficient (above 0). Without knowing the upper bound of the first time duration, the coherence distance is continuously extended, assuming a maximum extension of 20 times d. I.e. the second value is 20 d/v. And using the distance to be measured in the range of d-20 d for simulating antenna switching to obtain a series of channel impulse response CIRs, and using the channel impulse response CIRs as input to carry out multipath parameter estimation by an SAGE algorithm. And reconstructing the PDP of the reconstructed signal according to the estimated parameters by using SAGE algorithm.

Step S405: and comparing whether the error of the reconstructed PDP and the actual PDP is less than a second threshold value.

Specifically, after generating the reconstructed PDP according to the SAGE algorithm, the processor compares the reconstructed PDP with the actual PDP in step S401, and obtains whether an error between the two is smaller than a second threshold.

If so, determining the second value as the first duration. If not, the value of the first duration is decreased to a third value, and step S404 is repeated until the error between the reconstructed PDP and the actual PDP is less than the second threshold.

For example, assume that the second value is 20 d/v. After the reconstructed PDP is obtained, the error between the reconstructed PDP and the actual PDP under the second numerical value of 20d/v is calculated. As shown in FIG. 9, FIG. 9 is an exemplary graph showing a comparison between the reconstructed PDP and the actual PDP, from which an error analysis between the reconstructed PDP and the actual PDP can be obtained, and if the error is within a preset range, it is assumed that the SAGE algorithm can extract accurate multi-path information at the second value of 20 d/v. If not, the value of the first duration is decreased.

For example, the initial setting range is [ d/v,20d/v ], where v is the moving speed of the receiving end. Assuming that when the second value is equal to the coherence distance 20d, i.e., the second value is 20d/v, the parameters of the path within 30dB in the channel cannot be completely estimated, i.e., the error between the PDP reconstructed by the SAGE algorithm according to the estimated parameters and the actual PDP is beyond the preset range. The second value is decreased and the moving distance d' is taken to be 10 d. At this time, the second value is 10d/v, and the parameters of the path within 30dB in the channel are estimated again. If the PDP reconstructed through the SAGE algorithm according to the estimated parameters exceeds the preset range with the actual PDP. It may be continued to assume that the upper limit of the second value is in the range of (d/v,10d/v) and the moving distance d' is taken to be 5d, i.e. the second value is decreased. At this point, the second value is 5d/v, and the parameters of the path in the channel within 30dB are estimated again. And continuously reducing the second value until the error between the reconstructed PDP and the actual PDP is within a preset range. And then determining that a second value meeting the error in a preset range is the total switching time length of the antenna array.

It is understood that the above method for selecting the second numerical interval in the interval can also be selected by using the golden section method. For example, when the initial setting range is [ d/v,20d/v ], and the second value is 20d/v, the parameters of the path within 30dB in the channel cannot be fully estimated. According to the golden ratio (1: 0.618), the second value is reduced, and the moving distance d' is set to 12.36 d. At this time, the second value is 12.36d/v, and the parameters of the path within 30dB in the channel cannot be completely estimated. According to the golden ratio (1: 0.618), the second value is reduced, and the moving distance d' is set to 7.64 d. Such a reciprocating cycle will not be described herein.

Step S406: and if the second value is within the preset range, determining that the second value is the total switching duration of the antenna array.

Specifically, the processor compares whether the error between the reconstructed PDP and the actual PDP is within a preset range, and if so, obtains the second value and determines that the second value is the total switching duration of the antenna array.

In one embodiment, if d ' is 10d, the second value is 10d/v, the error between the PDP reconstructed by the SAGE algorithm according to the estimated parameters and the actual PDP is within the preset range, and when d ' is 15d, the error is large, the second value may be further increased, the upper limit range is narrowed to (10d/v,15d/v), d ' is 12d, the error value is repeatedly calculated, and whether the error value is within the preset range is determined. If so, increasing the second value, and if not, decreasing the second value. Repeating the steps until the error is close to 0%, finding the upper limit of the second value, and defining the most suitable range of the second value.

For example, the coherence distance d to 20d used in fig. 9, the error between the reconstructed PDP and the actual PDP is within the preset range, the coherence distance may be further enlarged, that is, the second value is enlarged, the above steps are repeated to reconstruct the PDP to calculate the error between the reconstructed PDP and the actual PDP, the distance to be measured within the range of d to 30d is used for simulating antenna switching to obtain a series of channel impulse response CIRs, and the channel impulse response CIRs are used as input to perform multipath parameter estimation by the SAGE algorithm. After the estimation parameter result is obtained, the error between the PDP obtained by reconstruction and the actual PDP is calculated under the second value of 30 d/v; when the error exceeds the preset range, the SAGE algorithm cannot accurately extract the multipath information, which means that the current second value cannot guarantee the coherence time of the multipath, and the value 20d/v before the time can be set as the second value and corresponds to the actual scene.

According to the above method flow, the following exemplary embodiment provides a detailed embodiment, in a preset environment: transmitting terminal coordinate T_x(100,0,0) m, receiver coordinates R_x(0,0,0) m, the moving speed v of the receiving end is 100 Km/h; the number of the antennas is 16; the center frequency is 2.6GHz, and 360 scatterers are uniformly distributed around the receiving end in the environment; d' is the moving distance of the receiving end. Maximum value of switching duration T_max＝d’/v。

First, a measurement scene is drawn according to the data, please refer to fig. 10. Fig. 10 shows a measurement scenario generated from the above data. Further, according to the measurement scene graph, the coherence of the whole channel and the component channel is analyzed, and the shortest coherence distance which is larger than the coherence distance of the whole channel under the same coherence coefficient is taken. Referring to fig. 11, curve 1 is coherence of a signal in a measurement scenario of 300 scatterers (i.e., coherence analysis of the entire measurement scenario), curve 2 is coherence of a signal in a measurement scenario of 30 scatterers, curve 3 is coherence of a signal in a measurement scenario of 30 scatterers, and curve 4 is coherence of a signal in a measurement scenario of 30 scatterers. The measurement angles of the

curves

1, 2, 3, 4 are different. When the autocorrelation coefficient is taken to be 0.4, the coherence distance of the curve 1 is about 0.5. And taking the coherence distance d as 0.5. This step is used to guide the range of values of the next coherence length. Wherein the preset range of the preset error is 0.1%.

Further, please refer to diagram a in fig. 12, where the moving distance d' is 20d, and the error is 31.35% and is greater than the preset range 0.2%, which is not satisfactory.

Further, please refer to fig. 12B, where the moving distance d' is 10d, and the error is 10.56% and is less than the preset range 0.2%, which is not satisfactory.

Further, referring to the diagram C in fig. 12, if D 'is 5D, where the error is 0.1518%, which is greater than the preset range 0.1%, which is not satisfactory, and for higher accuracy, D' may be further 3D, referring to the diagram D in fig. 12, where the error is 0.0165%, which is less than the preset range 0.2%, which is substantially 0 error, then the current moving distance is as follows:

in the measurement scenario drawn in the embodiment of the present application, the switching duration obtained by the conventional technology should be:

by the embodiment of the application, the switching time length is prolonged to three times of the switching time length in the traditional technology, the requirement on hardware is relieved to a certain extent, the integrity of a received signal can be basically guaranteed on the basis of prolonging the switching time length, and the characteristics of channel multipath and the like can be obtained.

In the embodiment of the application, a processor firstly draws a measurement scene to obtain a coherent distance under a certain autocorrelation coefficient in the whole environment, selects a second numerical value according to the coherent distance, performs channel parameter estimation on observations obtained under different second numerical values by using an SAGE algorithm, reconstructs and compares a PDP (packet data protocol) with an allowable error range until the second numerical value closest to an upper error limit is searched, wherein the second numerical value is considered to be the antenna array polling duration meeting the multipath parameter estimation requirement. Wherein, we determine the error index as: within the dynamic range of 0-30 dB of the peak value of the PDP, the error range of the reconstructed PDP and the actual PDP can be within 0.1%, namely the PDP obtained through observation can be accurately fitted, and the second numerical value under the current coherence distance can be used as the first duration. By the embodiment of the application, the condition that the first time length considered by the traditional theory is less than the coherent time length of the whole channel is abandoned. Under the condition of carrying out high-precision decomposition on the multi-path channel, the correlation duration of a single path (component channel) is verified to be longer than the coherence duration of the whole channel, so that the multi-path data of the channel can be accurately acquired when the switching duration of the antenna array is longer than the channel coherence duration.

It is to be understood that the method flow for the first duration acquisition is not limited to the method flow provided above. In the process of confirming the first time length, as long as the PDP of the reconstructed signal and the PDP of the actual observed signal are within the preset second threshold, it can be confirmed that the time length is applicable to the period required by the multi-antenna array switching in the scene.

Referring to fig. 13, a chip 1300 provided in an embodiment of the present application includes one or more processors 1301 and an interface circuit 1302. Optionally, the chip 1300 may further include a bus 1303. Wherein:

processor 1301 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 1301. The processor 1301 described above may be a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The methods, steps disclosed in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The interface circuit 1302 may complete transmission or reception of data, instructions, or information, and the processor 1301 may perform processing using the data, instructions, or other information received by the interface circuit 1302, and may transmit processing completion information through the interface circuit 1302.

Optionally, the chip further comprises a memory, which may include read only memory and random access memory, and provides operating instructions and data to the processor. The portion of memory may also include non-volatile random access memory (NVRAM).

Optionally, the memory stores executable software modules or data structures, and the processor may perform corresponding operations by calling the operation instructions stored in the memory (the operation instructions may be stored in an operating system).

Alternatively, the chip may be used in an electronic device or a network device according to the embodiments of the present application. Optionally, the interface circuit 1302 may be configured to output the result of the execution by the processor 1301. For the authentication method provided in one or more embodiments of the present application, reference may be made to the foregoing embodiments, which are not described herein again.

It should be noted that the functions corresponding to the processor 1301 and the interface circuit 1302 may be implemented by hardware design, software design, or a combination of hardware and software, which is not limited herein.

The above description mainly introduces the solutions provided in the embodiments of the present application from the perspective of the method implemented by the electronic device. It is to be understood that each network element, such as an electronic device, a processor, etc., comprises corresponding hardware structures and/or software modules for performing each function in order to realize the functions described above. Those of skill in the art would readily appreciate that the present application is capable of being implemented as hardware or a combination of hardware and computer software for performing the exemplary network elements and algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiment of the present application, the electronic device, the image capturing device, and the like may be divided into the functional modules according to the above method examples, for example, each functional module may be divided for each function, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, in the embodiment of the present application, the division of the module is schematic, and is only one logic function division, and there may be another division manner in actual implementation.

The embodiment of the application also provides a computer readable storage medium. All or part of the processes in the above method embodiments may be performed by relevant hardware instructed by a computer program, which may be stored in the above computer storage medium, and when executed, may include the processes in the above method embodiments. The computer-readable storage medium includes: various media that can store program codes, such as a read-only memory (ROM) or a Random Access Memory (RAM), a magnetic disk, or an optical disk.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in or transmitted over a computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The steps in the method of the embodiment of the application can be sequentially adjusted, combined and deleted according to actual needs.

The modules in the device can be merged, divided and deleted according to actual needs.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A signal processing system comprising an antenna array, a receiver, and a processor, wherein there are N receive channels between the receiver and the antenna array, and wherein the antenna array comprises M antennas; m, N is a positive integer, M > N;

the receiver acquires a first time length, wherein the first time length is longer than a first channel coherent time length and shorter than a second channel coherent time length; the first channel coherence duration is the coherence duration of the whole channel, and the second channel coherence duration is longer than the first channel coherence duration;

the M antennas of the antenna array receive signals in the overall channel;

during the first time period, the receiver controls the N receiving channels to transmit the signals received by the M antennas to the processor; wherein an error between the signal received by the processor and the signal received by the antenna array is less than a first threshold.

2. The system according to claim 1, wherein said receiver controls said N receive channels to transmit signals received by said M antennas to said processor during said first duration, comprising:

after K times of switching, transmitting the signals received by the M antennas to the processor through the N receiving channels, wherein: switching times K is M/N; each switching time length D is equal to the first time length/K;

in one switching, the N receiving channels are configured to transmit signals received by N antennas of the M antennas to the processor.

3. The system of claim 2, wherein the receiver comprises a switching circuit and a controller; the transmitting the signals received by the M antennas to the processor through the N receiving channels after the K times of switching includes:

controlling the switch circuit to switch for K times through the controller according to the first time length, and enabling the signals received by the M antennas to pass through the N receiving channels to the processor;

in one switching, the switch circuit is used for communicating N antennas in the M antennas with the N receiving channels.

4. The system of claim 1, wherein if the first duration is greater than or equal to the second channel coherence duration, the error between the signal received by the processor and the signal received by the antenna array is greater than or equal to the first threshold for the first duration;

if the first time length is less than the second channel coherence time length, the error between the signal received by the processor and the signal received by the antenna array is less than the first threshold value within the first time length.

5. The system according to claim 1, wherein when the first duration is a first value, if an error between the power delay profile of the entire channel reconstructed according to the first duration and the actual power delay profile of the entire channel is smaller than or equal to a second threshold, the second channel coherence duration is greater than or equal to the first value; otherwise, the second channel coherence length is less than the first value.

6. The system of claim 1, wherein before the receiver obtains the first duration, the processor calculates the first duration according to environment information data of the entire channel;

the processor calculates the first duration according to the environmental information data of the overall channel, and includes:

the processor draws an analog measurement scene according to the environment information number of the integral channel, wherein the analog measurement scene comprises a transmitting end for transmitting signals, the signal processing system for receiving the signals and a scatterer;

the processor acquires the coherence duration of the overall channel according to the simulation measurement scene, and determines that the value of the first duration is a second value, wherein the second value is L times of the coherence duration of the overall channel, L is an integer greater than 1, and the second value is smaller than the maximum coherence duration in the component channel of the overall channel;

the processor reconstructs the power time delay spectrum of the integral channel according to the second numerical value;

and if the error between the reconstructed power delay spectrum and the actual power delay spectrum of the whole channel is smaller than the second threshold, the processor determines that the value of the first duration is the second value.

7. The system of claim 6, wherein if the error between the reconstructed power delay profile and the power delay profile of the overall channel is greater than or equal to the second threshold, the processor further comprises:

determining that the value of the first duration is a third value, wherein the third value is smaller than the second value;

reconstructing a power time delay spectrum of the whole channel according to the third numerical value;

and if the error between the reconstructed power delay spectrum and the power delay spectrum of the whole channel is smaller than the second threshold, determining the value of the first duration to be the third value.

8. The system of claim 6, wherein the processor reconstructs the power delay profile of the overall channel from the second values, comprising:

the processor simulates the receiver to switch the connection and disconnection between the M antennas and the N receiving channels according to the second numerical value in the simulation measurement scene to obtain the channel impulse response of the whole channel;

the processor carries out parameter estimation on the simulated channel impulse response according to a preset algorithm to obtain the multipath parameters of the whole channel;

and the processor reconstructs the power time delay spectrum of the whole channel according to the multipath parameters.

9. The method according to any of claims 6-8, wherein the actual power delay spectrum of the overall channel is plotted by calculating the channel response in the simulated measurement scenario.

10. An electronic device, comprising: the antenna system comprises an antenna array, a receiver, a processor and a memory, wherein N receiving channels exist between the receiver and the antenna array, and the antenna array comprises M antennas; m, N is a positive integer, M > N; the processor is coupled with the receiver, the memory for storing computer program code, the computer program code including computer instructions, the electronic device to invoke the computer instructions to perform:

the M antennas of the antenna array receive signals in the overall channel;

11. The electronic device of claim 10, wherein the receiver controlling the N receive channels to transmit signals received by the M antennas to the processor during the first duration comprises:

12. The electronic device of claim 11, wherein the receiver comprises a switching circuit and a controller; the transmitting the signals received by the M antennas to the processor through the N receiving channels after the K times of switching includes:

controlling the switch circuit to switch for K times through the controller according to the first time length, and transmitting signals received by the M antennas to the processor through the N receiving channels;

13. The electronic device of claim 10, wherein if a first time period is greater than or equal to a second channel coherence time period, an error between a signal received by the processor and a signal received by the antenna array is greater than or equal to the first threshold for the first time period;

14. The electronic device of claim 10, wherein when the first duration is a first value, if an error between a power delay profile of an overall channel reconstructed from the first duration and an actual power delay profile of the overall channel is less than or equal to a second threshold, a second channel coherence duration is greater than or equal to the first value; otherwise, the second channel coherence length is less than the first value.

15. The electronic device of claim 11, wherein before the receiver obtains the first duration, the processor calculates the first duration according to environment information data of an overall channel;

16. The electronic device of claim 11, wherein if the error between the reconstructed power delay profile and the power delay profile of the overall channel is greater than or equal to the second threshold, the processor further comprises:

17. The electronic device of claim 11, wherein the processor reconstructs the power delay profile of the overall channel from the first value, comprising:

18. The electronic device of any of claims 15-17, wherein the actual power delay spectrum of the overall channel is plotted by calculating a channel response in the simulated measurement scenario.

19. A computer readable storage medium comprising computer instructions which, when run on an electronic device, cause the electronic device to perform the method of any of claims 1-9.

20. A chip comprising at least one processor, memory, and interface circuitry, the memory, the interface circuitry, and the at least one processor interconnected by wires, the at least one memory having instructions stored therein; when the instructions are executed by the processor, the method of any one of claims 1 to 9 is implemented.