CN113224172A - Thin film transistor and preparation method thereof - Google Patents
Thin film transistor and preparation method thereof Download PDFInfo
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- CN113224172A CN113224172A CN202110485813.4A CN202110485813A CN113224172A CN 113224172 A CN113224172 A CN 113224172A CN 202110485813 A CN202110485813 A CN 202110485813A CN 113224172 A CN113224172 A CN 113224172A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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Abstract
The embodiment of the invention discloses a thin film transistor and a preparation method thereof, wherein the preparation method of the thin film transistor comprises the following steps: providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer; sequentially forming a first metal layer and a second metal layer on one side of the gate insulating layer, which is far away from the substrate, wherein the first metal layer and the second metal layer are made of different materials; etching the second metal layer by a dry etching method to form a second grid and expose the first metal layer; and etching the first metal layer by adopting a wet etching method to form a first grid. Compared with a dry etching method, the wet etching method has small damage to the gate insulating layer below the first gate, and is beneficial to ensuring the uniformity of the surface of the gate insulating layer, so that when ions are injected into the active layer through the gate insulating layer to form a source electrode and a drain electrode, the uniformity of the injected ions can be improved, the conductor of the active layer into which the ions are injected is more uniform, and the electrical property of the thin film transistor is further beneficial to improving.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a thin film transistor and a preparation method thereof.
Background
An OLED (Organic Light Emitting Diode) display panel generally uses thin film transistors as a switching transistor and a driving transistor to ensure that the Light Emitting Diode stably emits Light.
At present, in the process of manufacturing a thin film transistor, an active layer is generally made conductive by ion implantation, but in the prior art, the uniformity of ion implantation is poor, which causes a phenomenon that the uniformity of electrical property of the thin film transistor is reduced.
Disclosure of Invention
Embodiments of the present invention provide a thin film transistor and a method for manufacturing the same, so as to improve uniformity of ion implantation and further improve uniformity of electrical properties of the thin film transistor.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a thin film transistor, including:
providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer;
sequentially forming a first metal layer and a second metal layer on one side, far away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials;
etching the second metal layer by a dry etching method to form a second grid and expose the first metal layer;
etching the first metal layer by adopting a wet etching method to form a first grid; wherein a vertical projection of the first gate on the substrate falls within a vertical projection of the second gate on the substrate;
and implanting ions into the active layer to obtain a source electrode and a drain electrode.
Optionally, the etching the second metal layer by using a dry etching method to form a second gate and expose the first metal layer includes:
forming a light resistance layer on one side of the second metal layer far away from the substrate, and exposing the light resistance layer;
etching the second metal layer by using the exposed photoresist layer as a mask to form the second grid and expose the first metal layer;
wherein the etching selectivity of the etching gas to the second metal layer is greater than the etching selectivity to the first metal layer.
Optionally, the etching the first metal layer by using a wet etching method to form a first gate includes:
and etching the first metal layer by using etching liquid to form the first grid electrode with an undercut structure, wherein the selection ratio of the etching liquid to the first metal layer is higher than that of the etching liquid to the second metal layer.
Optionally, after implanting ions into the active layer to obtain a source and a drain, the method further includes:
and obtaining the lightly doped region through diffusion, annealing or aging processes.
Optionally, after obtaining the lightly doped region through a diffusion, annealing or aging process, further comprising:
forming an interlayer dielectric layer on one side of the second grid electrode, which is far away from the substrate;
etching the interlayer dielectric layer to form a first through hole and a second through hole; wherein the first via exposes the source region and the second via exposes the drain region;
and filling the first through hole and the second through hole with a conductive material to form the source electrode and the drain electrode.
In a second aspect, an embodiment of the present invention further provides a thin film transistor, including:
a substrate;
an active layer on one side of the substrate, the active layer including a source electrode and a drain electrode;
the gate insulating layer is positioned on one side, far away from the substrate, of the active layer, and covers the active layer;
the first grid is positioned on one side, far away from the substrate, of the grid insulating layer;
the second grid is positioned on one side of the first grid, which is far away from the substrate;
a source electrode connected to a source electrode of the active layer and a drain electrode connected to a drain electrode of the active layer;
wherein the materials of the first gate and the second gate are different, and the vertical projection of the first gate on the substrate falls into the vertical projection of the second gate on the substrate.
Optionally, a distance exists between a boundary of a vertical projection of the first gate on the substrate and a boundary of a vertical projection of the second gate on the substrate in any direction of the surface of the substrate.
Optionally, the active layer includes a channel region, and the source electrode and the drain electrode are respectively located at two sides of the channel region along a direction perpendicular to the thickness direction of the thin film transistor; the active layer further comprises a lightly doped region between the source electrode and the channel region and between the drain electrode and the channel region;
and the size of the lightly doped region is equal to the shortest distance between the same side edges of the first grid and the second grid along the direction vertical to the thickness direction of the thin film transistor.
Optionally, the length of the lightly doped region ranges from 2 μm to 3 μm.
Optionally, the thickness of the first gate is smaller than the thickness of the second gate.
The embodiment of the invention provides a thin film transistor and a preparation method thereof, wherein two layers of grids made of different materials are arranged, and different etching methods are respectively adopted for the two layers of grids, so that the uniformity of ion implantation is improved. The thin film transistor is provided with a substrate and an active layer, wherein the active layer comprises a source electrode and a drain electrode, a gate insulating layer is further arranged on one side, far away from the substrate, of the active layer, a first metal layer and a second metal layer are sequentially formed on one side, far away from the substrate, of the gate insulating layer, and the first metal layer and the second metal layer are respectively etched to form a first grid electrode and a second grid electrode, and materials of the first grid electrode and the second grid electrode are different. Because the materials of the first grid and the second grid are different, the first grid and the second grid can be formed by adopting different etching methods in different etching steps. When the first gate and the second gate are prepared, the first metal layer for preparing the first gate may be used as a barrier layer, the second metal layer for preparing the second gate is etched by a dry etching method to form the second gate, and then the first metal layer is etched by a wet etching method to form the first gate. Compared with a dry etching method, the wet etching method has small damage to the gate insulating layer below the first gate, and is beneficial to ensuring the uniformity of the surface of the gate insulating layer, so that when ions are injected into the active layer through the gate insulating layer to form a source electrode and a drain electrode, the uniformity of the injected ions can be improved, the conductor of the active layer is more uniform, and the uniformity of the electrical property of the thin film transistor is further beneficial to improving.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 2-7 are schematic cross-sectional views illustrating a thin film transistor according to an embodiment of the present invention during a manufacturing process thereof;
fig. 8 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 10 is a schematic cross-sectional view of a thin film transistor with lightly doped regions formed thereon according to an embodiment of the present invention;
fig. 11 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention;
fig. 12 and fig. 13 are schematic cross-sectional structure diagrams corresponding to source and drain electrodes formed on a thin film transistor according to an embodiment of the present invention;
fig. 14 is a schematic cross-sectional view of a thin film transistor according to an embodiment of the present invention;
fig. 15 is a schematic cross-sectional structure diagram of another thin film transistor according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
As described in the background art, the thin film transistor in the prior art has a problem of poor uniformity of ion implantation, thereby affecting the uniformity of electrical properties thereof. The inventors have found that the above problems occur because the tft is mostly designed to have a TG-TC (Top Gate Top Contact) structure, and a Gate insulating layer is disposed between the Gate and the active layer to avoid short circuit between the Gate and the active layer. And part of the active layer is conducted by means of ion implantation to form a source electrode and a drain electrode of the thin film transistor. In the prior art, ions are generally implanted into an active layer by using a patterned gate as a mask, and the patterned gate is generally formed by dry etching, so that the gate insulating layer is damaged greatly in the process of etching the gate, and the damage degree of the gate insulating layer is uneven, so that when ions are implanted into the active layer by using the patterned gate as the mask, the uniformity of the gate insulating layer is poor, the uniformity of ion implantation is affected, and the uniformity of the electrical property of a thin film transistor is affected.
In view of the foregoing problems, an embodiment of the present invention provides a method for manufacturing a thin film transistor, fig. 1 is a flowchart of the method for manufacturing the thin film transistor according to the embodiment of the present invention, and fig. 2 to 7 are schematic cross-sectional structures of the thin film transistor according to the embodiment of the present invention in a manufacturing process, and referring to fig. 1 to 7, the method for manufacturing the thin film transistor according to the embodiment of the present invention includes:
s110, providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer.
Specifically, referring to fig. 2, the substrate 10 may be a flexible substrate, and may be formed of any insulating material having flexibility; the substrate 10 may also be rigid, such as a glass substrate. A buffer layer 20 for protection is formed on one side of the substrate 10, wherein the buffer layer 20 may be a film formed by stacking silicon nitride and/or silicon oxide. Then, a semiconductor layer is formed on the buffer layer 20 at a side away from the substrate 10, and the semiconductor layer is etched to form an active layer 40, where the material of the active layer 40 may be polysilicon, indium tin oxide, indium gallium tin oxide, or the like, which is not particularly limited in this embodiment. A gate insulating layer 30 is formed on the active layer 40 at a side away from the substrate 10 for isolating the active layer 40, wherein the gate insulating layer 30 covers the active layer 40.
And S120, sequentially forming a first metal layer and a second metal layer on the side, far away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials.
Specifically, with continued reference to fig. 2, a first metal layer 51 is formed on the side of the gate insulating layer 30 away from the substrate 10, and a second metal layer 52 is formed on the side of the first metal layer 51 away from the substrate 10. The first metal layer 51 and the second metal layer 52 are made of different materials, for example, the first metal layer 51 may be made of titanium, molybdenum-titanium alloy, molybdenum-niobium alloy, or the like, and the second metal layer 52 may be made of molybdenum, copper, aluminum, or the like. The first and second metal layers 51 and 52 may be formed by a sputtering method, a thermal evaporation method, a plasma enhanced chemical vapor deposition method, or the like.
S130, etching the second metal layer by adopting a dry etching method to form a second grid, and exposing the first metal layer.
Specifically, as shown in fig. 5, since the first gate 510 and the second gate 520 are made of different materials, the first gate 510 and the second gate 520 may be formed by different etching methods in different etching steps. The second metal layer 52 is etched by dry etching to form the second gate 520, and for example, the material of the second metal layer 52 is molybdenum, the second metal layer 52 can be directly bombarded by plasma, so that the second metal layer 52 is etched and the first metal layer 51 is exposed, that is, the second metal layer is etched by using the first metal layer 51 as an etching barrier layer, so that the etched second metal layer 52 can expose the first metal layer 51. Since the etching is performed with the first metal layer 51 as a barrier layer when the second metal layer 52 is etched, the gate insulating layer 30 below is not damaged.
S140, etching the first metal layer by adopting a wet etching method to form a first grid; wherein the vertical projection of the first gate on the substrate falls within the vertical projection of the second gate on the substrate.
Specifically, as shown in fig. 6, after the second gate 520 is etched, the first metal layer is etched by wet etching to form a first gate 510. Taking the material of the first metal layer as titanium for example, the first metal layer may be etched by using an etching solution to obtain the first gate 510, and a vertical projection of the first gate 510 on the substrate 10 falls into a vertical projection of the second gate 520 on the substrate 10. Compared with the dry etching method, the wet etching method has less damage to the gate insulating layer 30 (made of silicon oxide), and therefore, after the first metal layer is etched by the wet etching method to obtain the first gate electrode 510, the surface of the gate insulating layer 30 located below the first metal layer has good uniformity.
And S150, implanting ions into the active layer to obtain a source electrode and a drain electrode.
Specifically, it is easily understood in the art that when ions are implanted into the active layer 40, if the ions implanted into the active layer 40 are not uniform, the conduction of the active layer 40 is not uniform, so that the resistance of the region which is conducted is not uniform, and the electrical property of the active layer 40 is not uniform, that is, the uniformity of the ion implantation directly affects the electrical property of the thin film transistor. Generally, when the gate electrode is formed by dry etching, ions are implanted into the active layer 40 through the gate insulating layer 30, which is likely to cause great damage to the gate insulating layer 30 below and reduce the uniformity of the surface of the gate insulating layer 30, so that the uniformity of the implanted ions is poor when the ions are implanted into the active layer 40 through the gate insulating layer 30.
In this embodiment, referring to fig. 7, since the first gate electrode 510 is formed by wet etching, the surface of the gate insulating layer 30 under the first metal layer has good uniformity, and the source electrode 401 and the drain electrode 402 formed by ion implantation have high uniformity. In addition, after the first gate 510 and the second gate 520 are formed by etching, boron ions (for example, indium gallium tin oxide is used as a material of the active layer 40) are implanted into the active layer 40 by using the second gate 520 as a mask. When ions are implanted into the active layer 40 by using the second gate 520 as a mask, due to the shielding effect of the second gate 520, the active layer 40 covered by the vertical projection of the second gate 520 on the substrate 10 is not implanted with ions, and the portion is still a semiconductor region (i.e., the channel region 403), while the regions of the active layer 40 not shielded by the second gate 520 form conductor regions (i.e., the source 401 and the drain 402). The vertical projection of the first gate 510 on the substrate 10 falls into the vertical projection of the second gate 520 on the substrate 10, and along the thickness direction perpendicular to the thin film transistor, the size of the first gate 510 is smaller than or equal to the size of the second gate 520, so that when ions are implanted into the active layer 40 by using the second gate 520 as a mask, the size of the formed channel region 403 is not smaller than the size of the first gate 510, which is beneficial to reducing the parasitic capacitance of the thin film transistor, and further improving the electrical property of the thin film transistor.
Of course, in other embodiments, the material of the active layer 40 may also be polysilicon, and boron ions or phosphorus ions are implanted into the active layer 40 by using the second gate 520 as a mask to form the source 401 and the drain 402.
According to the preparation method of the thin film transistor, provided by the embodiment of the invention, two layers of grids made of different materials are arranged, and different etching methods are respectively adopted for the two layers of grids, so that the uniformity of ion implantation is improved. The thin film transistor is provided with a substrate and an active layer, wherein the active layer comprises a source electrode and a drain electrode, a gate insulating layer is further arranged on one side, far away from the substrate, of the active layer, a first metal layer and a second metal layer are sequentially formed on one side, far away from the substrate, of the gate insulating layer, and the first metal layer and the second metal layer are respectively etched to form a first grid electrode and a second grid electrode, and materials of the first grid electrode and the second grid electrode are different. Because the materials of the first grid and the second grid are different, the first grid and the second grid can be formed by adopting different etching methods in different etching steps. When the first gate and the second gate are prepared, the first metal layer for preparing the first gate may be used as a barrier layer, the second metal layer for preparing the second gate is etched by a dry etching method to form the second gate, and then the first metal layer is etched by a wet etching method to form the first gate. Compared with a dry etching method, the wet etching method has small damage to the gate insulating layer below the first gate, and is beneficial to ensuring the uniformity of the surface of the gate insulating layer, so that when ions are injected into the active layer through the gate insulating layer to form a source electrode and a drain electrode, the uniformity of the injected ions can be improved, the conductor of the active layer is more uniform, and the uniformity of the electrical property of the thin film transistor is further beneficial to improving.
Fig. 8 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention, and with reference to fig. 8, on the basis of the foregoing embodiment, the method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s210, providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer.
And S220, sequentially forming a first metal layer and a second metal layer on the side, away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials.
And S230, forming a photoresist layer on the side, away from the substrate, of the second metal layer, and exposing the photoresist layer.
And S240, etching the second metal layer by using the exposed photoresist layer as a mask by using etching gas to form a second grid, and exposing the first metal layer.
Specifically, referring to fig. 3 to 5, the process of forming the second gate 520 by etching the second metal layer 52 by dry etching at least includes: forming a photoresist layer 60 on the side of the second metal layer 52 away from the substrate 10, and exposing the photoresist layer 60; the exposed photoresist layer 60 is used as a mask to etch the second metal layer 52 to form the second gate 520 and expose the first metal layer 51.
First, a photoresist layer 60 is coated on the surface of the second metal layer 52, wherein the photoresist layer 60 can be a positive photoresist, and the photoresist layer 60 includes a gate pattern. The photoresist layer 60 is exposed by using a mask 100, wherein the mask 100 includes a transparent region and a non-transparent region, the non-transparent region corresponds to the gate pattern on the photoresist layer 60, the photoresist layer 60 irradiated by light is dissolved in a developing solution, and the photoresist layer 60 not irradiated by light is not dissolved in the developing solution. Then, the exposed photoresist layer 60 is used as a mask to etch the second metal layer 52 by dry etching to form the second gate 520. The etching selectivity of the etching gas of the dry etching method to the second metal layer is greater than that of the etching selectivity to the first metal layer, so that the first metal layer is not etched in the process of etching the second metal layer, the first metal layer can be enabled to play a role in protecting the gate insulating layer 30, and the gate insulating layer 30 is prevented from being damaged by the etching gas of the dry etching method. The etching gas can be chlorine gas, carbon tetrafluoride gas or sulfur hexafluoride gas and the like, and the second metal layer made of different materials is etched by selecting the etching gas with larger etching ratio.
S250, etching the first metal layer by adopting a wet etching method to form a first grid electrode; wherein a vertical projection of the first gate on the substrate falls within a vertical projection of the second gate on the substrate.
And S260, implanting ions into the active layer to obtain a source electrode and a drain electrode.
Fig. 9 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention, and with reference to fig. 9, on the basis of the foregoing embodiment, the method for manufacturing a thin film transistor according to an embodiment of the present invention includes:
s310, providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer.
And S320, sequentially forming a first metal layer and a second metal layer on the side, away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials.
S330, forming a photoresist layer on the side of the second metal layer far away from the substrate, and exposing the photoresist layer.
S340, etching the second metal layer by using the exposed photoresist layer as a mask by using etching gas to form a second gate and exposing the first metal layer.
S350, etching the first metal layer by using etching liquid to form a first grid electrode with an undercut structure, wherein the selection ratio of the etching liquid to the first metal layer is higher than that of the etching liquid to the second metal layer.
Specifically, as shown in fig. 6, the material of the first metal layer 51 may be titanium, and the etching liquid selected by the wet etching method has a higher selection ratio for the first metal layer 51 than for the second metal layer 52, so as to ensure that the second metal layer 52 is not etched during the etching of the first metal layer 51. Because the wet etching method is to strip the first metal layer 51 to be etched away by adopting a reaction mode of chemical liquid and the first metal layer 51, compared with the dry etching, the wet etching has good etching surface uniformity, has small damage to the gate insulating layer 30 (made of silicon oxide), is beneficial to ensuring the uniformity of the surface of the gate insulating layer 30, and is further beneficial to improving the uniformity of ion implantation. For example, the etching solution may be hydrofluoric acid and Buffered Oxide etching solution (BOE).
In the present embodiment, the thickness of the first metal layer 51 is smaller than that of the second metal layer 52, and this is provided to prevent metal etching residue when the first metal layer 51 is etched. Since the etching solution has the characteristic of isotropy, when the first metal layer 51 is etched, the length (width) and thickness of the etched first metal layer 51 are the same in the direction perpendicular to the thickness direction of the thin film transistor, but since the upper surface of the first metal layer 51 is in contact with the second gate 520 and the selection ratio of the etching solution to the first metal layer 51 is higher than that to the second metal layer 52, the etching speed of the upper surface of the first metal layer 51 is lower than that of the lower surface thereof, so as to form the first gate 510 with an undercut structure. Along the thickness direction of being perpendicular to thin film transistor, there is the length difference between the one side that first grid 510 and gate insulation layer 30 contacted and the one side that contacts with second grid 520, because the isotropy of etching liquid for this length difference is positive correlation with the thickness of first metal level 51, consequently reduces the thickness of first metal level 51, is favorable to reducing the length difference between the upper and lower surface of first grid 510, and then is favorable to reducing the undercut structure, makes and is difficult for there being the metal etching to remain in undercut structure department.
And S360, implanting ions into the active layer to obtain a source electrode and a drain electrode.
And S370, obtaining the lightly doped region through diffusion, annealing or aging processes.
Specifically, referring to fig. 10, when ions are implanted into the active layer 40 by using the second gate 520 as a mask, referring to fig. 10, due to the shielding effect of the second gate 520, a portion of the active layer 40 covered by the vertical projection of the second gate 520 is not implanted with ions, the portion maintains a semiconductor state as the channel region 403 of the active layer 40, and a region not shielded by the second gate 520 is made conductive to form the source 401 and the drain 402, and a portion of the ions are migrated by natural diffusion, annealing or aging to form the lightly doped region 404. For example, by forming the lightly doped region 404 through an annealing process, applying a suitable temperature to the source electrode 401 and the drain electrode 402 to cause ions to migrate toward the side close to the channel region 403, and by controlling the heating time, the migration distance of the ions can be precisely controlled, so that the desired lightly doped region 404 can be obtained. A lightly doped region 404 may also be formed by an aging process, a start-up voltage is applied to the first gate 510 to make the first gate 510 and the channel region 403 conductive, and then voltages are applied to the source 401 and the drain 402 to make electric fields formed between the source 401 and the drain 402 and the channel region 403, respectively, and ions migrate to a side close to the channel region 403 under the action of the electric field force; by controlling the pressing time, the migration distance of the ions can be precisely controlled, so that the desired lightly doped region 404 can be obtained.
The off-state leakage current of the thin film transistor can be improved because the resistance of the lightly doped region 404 is between the conductor region and the semiconductor region. And partial ions are migrated through processes of natural diffusion, annealing or aging and the like, so that the source and drain regions and the lightly doped region 404 are formed simultaneously, the process steps can be reduced, and the production cost can be reduced. The size of the lightly doped region 404 can be controlled by the above process, so as to prevent the lightly doped region 404 from being too long and reducing the size of the channel region 403, and the size of the channel region 403 is smaller than that of the first gate 510. In this embodiment, along a direction perpendicular to the thickness direction of the thin film transistor, the size of the lightly doped region 404 is equal to the shortest distance between the same side edges of the first gate 510 and the second gate 520, and under the condition that the first gate 510 and the second gate 520 have a slope angle, the size of the lightly doped region 404 is equal to the shortest distance between the longer edge of the second gate 520 and the shorter edge of the first gate 510, so as to ensure that the size of the channel region 403 is equal to the size of the first gate 510 of the thin film transistor, thereby reducing the parasitic capacitance between the first gate 510 and the channel region 403, and facilitating to increase the driving current of the thin film transistor. Illustratively, the lightly doped region 404 has a size of 2-3 μm, i.e., the undercut structure has a size of 2-3 μm.
In this embodiment, since the dry etching method has a high precision, the second metal layer 52 is etched by the dry etching method, so that the second gate 520 can have a high etching precision, and when ions are subsequently implanted into the active layer 40 by using the second gate 520 as a mask, the precision of the channel region 403 can be ensured, which is beneficial to improving the electrical property of the thin film transistor.
Fig. 11 is a flowchart of another method for manufacturing a thin film transistor according to an embodiment of the present invention, and referring to fig. 11, the method for manufacturing a thin film transistor includes:
s410, providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer.
And S420, sequentially forming a first metal layer and a second metal layer on the side, away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials.
And S430, forming a photoresist layer on the side of the second metal layer far away from the substrate, and exposing the photoresist layer.
S440, with the exposed light resistance layer as a mask, etching the second metal layer by using etching gas to form a second grid, and exposing the first metal layer.
S450, etching the first metal layer by using etching liquid to form a first grid electrode with an undercut structure, wherein the selection ratio of the etching liquid to the first metal layer is higher than that of the etching liquid to the second metal layer.
And S460, implanting ions into the active layer to obtain a source electrode and a drain electrode.
And S470, obtaining the lightly doped region through diffusion, annealing or aging processes.
And S480, forming an interlayer dielectric layer on one side of the second grid electrode, which is far away from the substrate.
S490, etching the interlayer dielectric layer to form a first through hole and a second through hole; the first through hole exposes the source electrode, and the second through hole exposes the drain electrode.
And S500, filling the first through hole and the second through hole with conductive materials respectively to form a source electrode and a drain electrode.
Specifically, fig. 12 and fig. 13 are schematic cross-sectional structural diagrams corresponding to source and drain electrodes formed on the thin film transistor according to the embodiment of the present invention, and referring to fig. 12 and fig. 13, after a portion of the active layer 40 is conducted to form the source 401 and the drain 402, an interlayer dielectric layer 70 is formed on a side of the second gate 520 away from the substrate 10, and the interlayer dielectric layer 70 covers the second gate 520 and the first gate 510. And etching the interlayer dielectric layer 70 to form a first through hole 41 and a second through hole 42, wherein the first through hole 41 and the second through hole 42 respectively expose the source electrode 401 and the drain electrode 402 of the active layer 40, and the first through hole 41 and the second through hole 42 are filled with conductive materials to lead out the source electrode 401 and the drain electrode 402 so as to form a source electrode 410 and a drain electrode 420.
Fig. 14 is a schematic cross-sectional structure diagram of a thin film transistor according to an embodiment of the present invention, and referring to fig. 14, the thin film transistor includes a substrate 10; an active layer 40 on one side of the substrate 10, the active layer 40 including a source electrode 401 and a drain electrode 402; the gate insulating layer 30 is positioned on one side of the active layer 40, which is far away from the substrate 10, and the gate insulating layer 30 covers the active layer 40; a first gate electrode 510 located on a side of the gate insulating layer 30 away from the substrate 10; a second gate 520 located on a side of the first gate 510 away from the substrate 10; a source electrode 410 and a drain electrode 420, the source electrode 410 being connected to the source electrode 401 of the active layer 40, the drain electrode 420 being connected to the drain electrode 402 of the active layer 40; wherein, the materials of the first gate 510 and the second gate 520 are different, and the vertical projection of the first gate 510 on the substrate 10 falls into the vertical projection of the second gate 520 on the substrate 10.
Fig. 15 is a schematic cross-sectional view of another thin film transistor according to an embodiment of the present invention, referring to fig. 15, the active layer 40 further includes a channel region 403, and the source electrode 401 and the drain electrode 402 are respectively located on two sides of the channel region 403 along a direction perpendicular to a thickness direction of the thin film transistor; the active layer 40 further includes a lightly doped region 404 between the source electrode 401 and the channel region 403, and between the drain electrode 402 and the channel region 403; the lightly doped region 404 has a size equal to the shortest distance between the same side edges of the first gate electrode 510 and the second gate electrode 520 in a direction perpendicular to the thickness direction of the thin film transistor.
Specifically, the vertical projection of the first gate 510 on the substrate 10 falls within the vertical projection of the second gate 520 on the substrate 10; alternatively, the boundary of the vertical projection of the first gate 510 on the substrate 10 and the boundary of the vertical projection of the second gate 520 on the substrate 10 have a distance in any direction of the surface of the substrate 10. That is, the length of the second gate electrode 520 is greater than the length of the first gate electrode 510 in a direction perpendicular to the thickness direction of the thin film transistor. When ions are implanted into the active layer 40 by using the second gate electrode 520 as a mask, due to the shielding effect of the second gate electrode 520, the portion of the active layer 40 covered by the vertical projection of the second gate electrode 520 on the substrate 10 is not implanted with ions, the portion maintains a semiconductor state as the channel region 403 of the active layer 40, and the regions not shielded by the second gate electrode 520 form conductor regions (i.e., the source electrode 401 and the drain electrode 402). A lightly doped region 404 (shown as two dotted lines in fig. 15) is further included between the conductor region and the semiconductor region, wherein the lightly doped region 404 may be formed by natural diffusion, annealing or aging, etc. to make part of ions migrate, and the resistance of the lightly doped region 404 is between the conductor region and the semiconductor region, which can improve the off-state leakage current of the thin film transistor. And partial ions are migrated through processes of natural diffusion, annealing or aging and the like, so that the source and drain electrodes and the lightly doped region 404 can be formed simultaneously, the process steps can be reduced, and the production cost can be reduced.
Of course, in other embodiments, the vertical projection of the first gate electrode 510 on the substrate 10 may completely overlap with the vertical projection of the second gate electrode 520 on the substrate 10, that is, the first gate electrode 510 and the second gate electrode 520 have equal size in the direction perpendicular to the thickness direction of the thin film transistor. For a specific process flow, reference may be made to the related description of the first gate 510 and the second gate 520 in the above embodiments, and details are not repeated herein.
In the present embodiment, the first gate 510 is an undercut structure, and the first gate 510 with the undercut structure can be obtained by controlling the etching time; the thickness of the first metal layer 51 is smaller than that of the second metal layer 52, and this is set to prevent metal etching residue from occurring when the first metal layer 51 is etched. Since the etching solution has the characteristic of isotropy, when the first metal layer 51 is etched, the length (width) and thickness of the etched first metal layer 51 are the same in the direction perpendicular to the thickness direction of the thin film transistor, but since the upper surface of the first metal layer 51 is in contact with the second gate 520 and the selection ratio of the etching solution to the first metal layer 51 is higher than that to the second metal layer 52, the etching speed of the upper surface of the first metal layer 51 is lower than that of the lower surface thereof, so as to form the first gate 510 with an undercut structure. Along the thickness direction of being perpendicular to thin film transistor, there is the length difference between the one side that first grid 510 and gate insulation layer 30 contacted and the one side that contacts with second grid 520, because the isotropy of etching liquid for this length difference is positive correlation with the thickness of first metal level 51, consequently reduces the thickness of first metal level 51, is favorable to reducing the length difference between the upper and lower surface of first grid 510, and then is favorable to reducing the undercut structure, makes and is difficult for there being the metal etching to remain in undercut structure department.
The embodiment of the invention provides a thin film transistor, wherein a substrate and an active layer are arranged in the thin film transistor, the active layer comprises a source electrode and a drain electrode, a gate insulating layer is further arranged on one side, far away from the substrate, of the active layer, and the gate insulating layer comprises a first gate electrode and a second gate electrode which are arranged in a stacked mode, far away from the substrate, and materials of the first gate electrode and the second gate electrode are different. Because the materials of the first grid and the second grid are different, the first grid and the second grid can be formed by adopting different etching methods in different etching steps. When the first gate and the second gate are prepared, the first metal layer for preparing the first gate may be used as a barrier layer, the second metal layer for preparing the second gate is etched by a dry etching method to form the second gate, and then the first metal layer is etched by a wet etching method to form the first gate. Compared with a dry etching method, the wet etching method has small damage to the gate insulating layer below the first gate, and is beneficial to ensuring the uniformity of the surface of the gate insulating layer, so that when ions are injected into the active layer through the gate insulating layer to form a source electrode and a drain electrode, the uniformity of the injected ions can be improved, the conductor of the active layer is more uniform, and the uniformity of the electrical property of the thin film transistor is further beneficial to improving.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for manufacturing a thin film transistor includes:
providing a substrate, and sequentially forming an active layer and a gate insulating layer on the substrate, wherein the gate insulating layer is positioned on one side of the active layer, which is far away from the substrate, and the gate insulating layer covers the active layer;
sequentially forming a first metal layer and a second metal layer on one side, far away from the substrate, of the gate insulating layer, wherein the first metal layer and the second metal layer are made of different materials;
etching the second metal layer by a dry etching method to form a second grid and expose the first metal layer;
etching the first metal layer by adopting a wet etching method to form a first grid; wherein a vertical projection of the first gate on the substrate falls within a vertical projection of the second gate on the substrate;
and implanting ions into the active layer to obtain a source electrode and a drain electrode.
2. The method of claim 1, wherein the etching the second metal layer by a dry etching method to form a second gate and expose the first metal layer comprises:
forming a light resistance layer on one side of the second metal layer far away from the substrate, and exposing the light resistance layer;
etching the second metal layer by using the exposed photoresist layer as a mask to form the second grid and expose the first metal layer;
wherein the etching selectivity of the etching gas to the second metal layer is greater than the etching selectivity to the first metal layer.
3. The method for manufacturing the thin film transistor according to claim 1, wherein the etching the first metal layer by a wet etching method to form the first gate electrode comprises:
and etching the first metal layer by using etching liquid to form the first grid electrode with an undercut structure, wherein the selection ratio of the etching liquid to the first metal layer is higher than that of the etching liquid to the second metal layer.
4. The method for manufacturing a thin film transistor according to claim 1, further comprising, after implanting ions into the active layer to obtain a source electrode and a drain electrode:
and obtaining the lightly doped region through diffusion, annealing or aging processes.
5. The method of manufacturing a thin film transistor according to claim 4, further comprising, after obtaining the lightly doped region by a diffusion, annealing or aging process:
forming an interlayer dielectric layer on one side of the second grid electrode, which is far away from the substrate;
etching the interlayer dielectric layer to form a first through hole and a second through hole; wherein the first via exposes the source and the second via exposes the drain;
and filling the first through hole and the second through hole with a conductive material to form the source electrode and the drain electrode.
6. A thin film transistor, comprising:
a substrate;
an active layer on one side of the substrate, the active layer including a source electrode and a drain electrode;
the gate insulating layer is positioned on one side, far away from the substrate, of the active layer, and covers the active layer;
the first grid is positioned on one side, far away from the substrate, of the grid insulating layer;
the second grid is positioned on one side of the first grid, which is far away from the substrate;
a source electrode connected to a source electrode of the active layer and a drain electrode connected to a drain electrode of the active layer;
wherein the materials of the first gate and the second gate are different, and the vertical projection of the first gate on the substrate falls into the vertical projection of the second gate on the substrate.
7. The thin film transistor according to claim 6, wherein a boundary of a vertical projection of the first gate electrode on the substrate and a boundary of a vertical projection of the second gate electrode on the substrate are spaced apart in any direction of the surface of the substrate.
8. The thin film transistor according to claim 6, wherein the active layer comprises a channel region, and the source electrode and the drain electrode are respectively located on both sides of the channel region in a direction perpendicular to a thickness direction of the thin film transistor; the active layer further comprises a lightly doped region between the source electrode and the channel region and between the drain electrode and the channel region;
and the size of the lightly doped region is equal to the shortest distance between the same side edges of the first grid and the second grid along the direction vertical to the thickness direction of the thin film transistor.
9. The thin film transistor of claim 8, wherein the lightly doped region has a size in a range of 2 to 3 μm.
10. The thin film transistor according to claim 6, wherein a thickness of the first gate electrode is smaller than a thickness of the second gate electrode.
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