CN113223475A - GOA circuit, display panel and display device - Google Patents
GOA circuit, display panel and display device Download PDFInfo
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- CN113223475A CN113223475A CN202110514101.0A CN202110514101A CN113223475A CN 113223475 A CN113223475 A CN 113223475A CN 202110514101 A CN202110514101 A CN 202110514101A CN 113223475 A CN113223475 A CN 113223475A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2380/00—Specific applications
- G09G2380/02—Flexible displays
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The embodiment of the invention discloses a GOA circuit, a display panel and a display device, wherein the GOA circuit comprises: cascaded multi-stage sub-circuits, an nth stage sub-circuit of the multi-stage sub-circuits comprising: the device comprises a scanning control module, a pull-down module and a bootstrap module; the output end of the scanning module is electrically connected with one input end of the pull-down module through a first node; a bootstrap module, the bootstrap module comprising: a bootstrap capacitor and a seventh transistor; one end of the bootstrap capacitor is electrically connected with the nth-stage gate drive signal, the other end of the bootstrap capacitor is electrically connected with the first node, the input end of the seventh transistor is electrically connected with the first node, the control end of the seventh transistor is electrically connected with the first voltage end, and the output end of the seventh transistor is electrically connected with the second node; by redesigning the circuit structure of the bootstrap module, the problems of voltage reduction, abnormal display and the like caused by electric leakage are solved.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a GOA circuit, a display panel, and a display device.
Background
The Gate Driver On Array, referred to as GOA, is a technology for manufacturing a Gate line scan driving circuit On an Array substrate by using the existing thin film transistor liquid crystal display Array manufacturing process to realize a driving mode of scanning a Gate line by line.
The TP (Touch Panel) interrupt means that a GOA circuit including an ITP (In-Cell Touch Panel) function needs to implement display scanning and Touch scanning functions during a display period. In the conventional In-Cell touch screen technology, after a plurality of rows of pixels In an AA (Active Area, display Area) Area are scanned, the display scanning is stopped, a part of touch (touch) electrodes In the AA Area are scanned, then the display scanning and the touch scanning are alternated, and the process is repeated for multiple times (the times are determined according to specific products), so that the display of a frame of picture and the scanning of full-screen touch electrodes are completed.
The bootstrap circuit is a circuit that increases a voltage by superimposing a discharge voltage of a capacitor with a power supply voltage using an electronic component such as a bootstrap boost diode and a bootstrap boost capacitor. The existing bootstrap circuit is easy to generate electric leakage due to the connection mode, the structural design and other reasons, so that the voltage is reduced, and the problem of abnormal display is caused.
Therefore, in the existing GOA circuit technology, there are also problems that the bootstrap circuit design is not reasonable, the leakage is easy to occur, and the normal display is affected, and improvement is urgently needed.
Disclosure of Invention
The invention relates to a GOA circuit, a display panel and a display device, which are used for solving the problems that a bootstrap circuit is unreasonable in design, leakage is easy to generate, and normal display is influenced in the prior art.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a GOA circuit, which comprises: a cascaded multi-stage sub-circuit, an nth stage sub-circuit of the multi-stage sub-circuit comprising:
the device comprises a scanning control module, a pull-down module and a bootstrap module;
the output end of the scanning module is electrically connected with one input end of the pull-down module through a first node;
a bootstrapping module, the bootstrapping module comprising: a bootstrap capacitor and a seventh transistor;
one end of the bootstrap capacitor is electrically connected to the nth-stage gate driving signal, the other end of the bootstrap capacitor is electrically connected to the first node, an input end of the seventh transistor is electrically connected to the first node, a control end of the seventh transistor is electrically connected to the first voltage end, and an output end of the seventh transistor is electrically connected to the second node.
In some embodiments, the nth stage sub-circuit further comprises: closing the module;
the shutdown module includes an eleventh transistor;
a control end of the eleventh transistor is electrically connected to the turn-off control signal, an input end of the eleventh transistor is electrically connected to the nth-stage gate driving signal, and an output end of the eleventh transistor is electrically connected to the second voltage end.
In some embodiments of the present invention, the,
the nth stage sub-circuit further comprises: the pull-down control module is connected with the output module;
the output end of the scanning control module is electrically connected with one end of the bootstrap module, and the output end of the scanning control module is electrically connected with one end of the pull-down control module;
the other end of the bootstrap module is electrically connected with the output module;
the other end of the pull-down control module is electrically connected with one end of the pull-down module;
one end of the output module is electrically connected with the other end of the pull-down module;
the input end of the closing module is electrically connected with the output end of the output module, and the output end of the closing module is electrically connected with the output end of the pull-down module.
In some embodiments, the scan control module comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor;
the control end of the first transistor is electrically connected with the N-2 th level grid driving signal; the input end of the first transistor is electrically connected with the forward scanning control signal; the output end of the first transistor is electrically connected with the first node;
the control end of the second transistor is electrically connected with the (N +2) th-level grid driving signal; the input end of the second transistor is electrically connected with the reverse scanning control signal; the output end of the second transistor is electrically connected with the first node;
the control end of the third transistor is electrically connected with the forward scanning control signal; the input end of the third transistor is electrically connected with the (N +2) th-level clock signal; the output end of the third transistor is electrically connected with the control end of the eighth transistor;
the control end of the fourth transistor is electrically connected with the reverse scanning control signal; the input end of the fourth transistor is electrically connected with the N-2 level clock signal; and the output end of the fourth transistor is electrically connected with the control end of the eighth transistor.
In some embodiments, the output module comprises: a ninth transistor;
the control end of the ninth transistor is electrically connected with the second node; the input end of the ninth transistor is electrically connected with the Nth-stage clock signal; the output end of the ninth transistor is electrically connected with the Nth-stage grid driving signal.
In some embodiments, the pull-down control module comprises: a fifth transistor and an eighth transistor;
the control end of the eighth transistor is electrically connected with the output end of the third transistor; the input end of the eighth transistor is electrically connected with the first voltage end; the output end of the eighth transistor is electrically connected with the input end of the fifth transistor;
the control end of the fifth transistor is electrically connected with the first node; the input end of the fifth transistor is electrically connected with the output end of the eighth transistor; the output end of the fifth transistor is electrically connected with the second voltage end.
In some embodiments, the pull-down module comprises: a sixth transistor, a tenth transistor, and a second capacitor;
the control end of the sixth transistor is electrically connected with the input end of the fifth transistor; an input end of the sixth transistor is electrically connected with the first node; the output end of the sixth transistor is electrically connected with the second voltage end;
a control end of the tenth transistor is electrically connected with an input end of the fifth transistor; an input end of the tenth transistor is electrically connected with the nth-stage gate driving signal; an output end of the tenth transistor is electrically connected with the second voltage end;
the first end of the second capacitor is electrically connected with the input end of the fifth transistor; a second terminal of the second capacitor is connected to the second voltage terminal.
In some embodiments, the GOA circuit is a single stage driver circuit or the GOA circuit is a dual stage driver circuit.
The application also provides a display panel, which comprises the GOA circuit.
The application also provides a display device, which comprises the GOA circuit.
Compared with the prior art, the GOA circuit, the display panel and the display device provided by the invention have the beneficial effects that:
the invention provides a GOA circuit, which comprises: a cascaded multi-stage sub-circuit, an Nth stage sub-circuit of the multi-stage sub-circuit comprising: the device comprises a scanning control module, a pull-down module and a bootstrap module; the output end of the scanning module is electrically connected with one input end of the pull-down module through a first node; a bootstrapping module, the bootstrapping module comprising: a bootstrap capacitor and a seventh transistor; one end of the bootstrap capacitor is electrically connected to the nth-stage gate driving signal, the other end of the bootstrap capacitor is electrically connected to the first node, an input end of the seventh transistor is electrically connected to the first node, a control end of the seventh transistor is electrically connected to the first voltage end, and an output end of the seventh transistor is electrically connected to the second node; by redesigning the circuit structure of the bootstrap module, the problems of voltage reduction, abnormal display and the like caused by electric leakage are solved.
Drawings
Fig. 1 is a schematic view of a first structure of a display panel according to an embodiment of the present invention.
Fig. 2 is a schematic view of a second structure of the display panel according to the embodiment of the invention.
Fig. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention.
Fig. 5 is a timing diagram illustrating operation of a GOA circuit according to an embodiment of the present invention.
Fig. 6 is a flowchart illustrating a driving method of a GOA circuit according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
The invention provides a GOA circuit, a display panel and a display device, and particularly refers to fig. 1 to 6.
The existing bootstrap circuit is easy to generate electric leakage due to the reasons of electric connection mode, structural design and the like, so that the voltage is reduced, and the problem of abnormal display is caused. For example, the existing bootstrap circuit generally includes two cases, one case is that a bootstrap capacitor is disposed between an input module and a voltage regulator tube of the bootstrap module, so that one end of the bootstrap capacitor is connected to an input end of the voltage regulator tube, and the other end of the bootstrap capacitor is connected to a second voltage end VGL, and the design mode of the bootstrap capacitor can reduce leakage current generated by threshold voltage drift of the voltage regulator tube, and increase voltage of the voltage regulator tube; in another case, one end of the bootstrap capacitor is electrically connected to the output end of the voltage regulator tube, and the other end of the bootstrap capacitor is electrically connected to the output signal of the GOA, in the same way as the above electrical connection, the bootstrap capacitor can enhance the power storage capability at the output end of the voltage regulator tube, and reduce the voltage reduction during touch scanning leakage, and meanwhile, when the clock signal of the output transistor corresponding to the current stage is turned on, the bootstrap capacitor serves as a bootstrap device to enhance the bootstrap capability at the output end of the voltage regulator tube. In the two driving circuit designs, assuming that a touch scanning time period is entered after the nth-level pixel data display scanning is finished, touch scanning is started, when the nth-level GOA is output to a high level, the levels at the input end of the voltage regulator tube and the output end of the voltage regulator tube in the (n + 1) th-level GOA unit Gn +1 are also pulled high, however, during the touch scanning, the bootstrap capacitor electrically connected with one end of the first-level voltage regulator tube leaks electricity through the input end and the output end connected with the bootstrap capacitor, so that the voltage is reduced, after the touch scanning is finished, when the clock signal corresponding to the level outputs a high level, because the voltage at the output end of the voltage regulator tube (namely the control end of the output transistor) is insufficient, the starting voltage of the transistor of the upper level is insufficient, the output end of the voltage regulator tube cannot be bootstrapped to a high potential, and the voltage Vgs of the grid electrode in the voltage regulator, at this moment, the voltage regulator tube does not work, the output end of the voltage regulator tube leaks electricity to the input end of the voltage regulator tube, the voltage at the output end of the voltage regulator tube is not bootstrapped to a high potential, finally, the output voltage of the previous stage of the GOA unit is lower, and even pixel transistors in a corresponding row cannot be started, so that abnormal display is caused. Therefore, the present invention provides a GOA circuit, a driving method thereof, a display panel, and a display device to solve the above problems.
The display panel comprises a display area and a non-display area, and the display panel comprises a pixel driving circuit positioned in the display area and a GOA circuit positioned in the non-display area;
the GOA circuit is electrically connected to a second voltage terminal VGL, and the second voltage terminal VGL is used to turn off a driving transistor in the pixel driving circuit, which is electrically connected to an output terminal gate (n) of the GOA circuit, and an output transistor NT9 in the GOA circuit, so as to suppress threshold voltage drift of the driving transistor in the pixel driving circuit, and improve reliability of the driving transistor and fault tolerance of the display panel.
In an embodiment, the GOA circuit in the non-display area of the display panel is a single-stage driving circuit, refer to fig. 1; in another embodiment, the GOA circuit in the non-display area of the display panel is a dual-stage driving circuit, see fig. 2.
Specifically, referring to fig. 1, a first structural diagram of a display panel according to an embodiment of the present invention is shown. In this structure, the GOA circuit in the non-display area of the display panel is a single-stage driving circuit; that is, the GOA circuit is disposed at the left side of the display panel and the GOA circuit is provided to the display panel from the left side, and similarly, the GOA circuit may be disposed at the right side of the display panel to provide the GOA circuit to the display panel.
Fig. 2 is a schematic view of a second structure of the display panel according to the embodiment of the present invention. In this structure, the GOA circuits in the non-display region in the display panel are dual-stage driving circuits, that is, the gate driving circuits are simultaneously disposed on two sides of the display panel, and the GOA circuits are respectively provided to the display panel from the left and right sides.
Specifically, referring to fig. 3 to fig. 5, fig. 3 is a schematic diagram of a GOA circuit according to an embodiment of the present invention. Fig. 4 is a schematic structural diagram of a GOA circuit according to an embodiment of the present invention. Fig. 5 is a timing diagram illustrating operation of a GOA circuit according to an embodiment of the present invention.
The invention provides a GOA circuit, which comprises: a cascaded multi-stage sub-circuit, an Nth stage sub-circuit of the multi-stage sub-circuit comprising:
the device comprises a scanning control module, a pull-down module and a bootstrap module;
the output end of the scanning module is electrically connected with one input end of the pull-down module through a first node;
a bootstrap module 400, said bootstrap module 400 comprising a bootstrap capacitor C1 and a seventh transistor NT 7;
one end of the bootstrap capacitor C1 is electrically connected to the nth level gate driving signal, the other end of the bootstrap capacitor C1 is electrically connected to the first node q (N), an input end of the seventh transistor NT7 is electrically connected to the first node q (N), a control end of the seventh transistor NT7 is electrically connected to the first voltage terminal VGH, and an output end of the seventh transistor NT7 is electrically connected to the second node qa (N).
Specifically, the GOA circuit includes: a cascaded multi-stage sub-circuit, an nth stage sub-circuit of the multi-stage sub-circuit comprising:
a scan control module 100, configured to implement forward scanning or reverse scanning according to the scan control signal;
the pull-down control module 200 is electrically connected with the scan control module 100, and the pull-down control module 200 is configured to control a working state of the pull-down module according to the scan control module 100;
the output module 500 is electrically connected to the bootstrap module 400 and the pull-down module 300, the output module 500 is connected to the nth-stage clock signal ck (N), and the output module 500 is configured to output an nth-stage gate driving signal;
the pull-down module 300 is electrically connected to the pull-down control module 200 and the bootstrap module 400, and the pull-down module 300 is connected to a second voltage terminal VGL; the pull-down module 300 is configured to turn off the output transistor in the output module 500 by using the second voltage terminal VGL in a reset phase, and access the nth-stage gate driving signal by using the second voltage terminal VGL to pull down the nth-stage gate driving signal of the output module 500, so as to turn off a driving transistor in a pixel driving circuit;
a bootstrap module 400 electrically connected to the scan control module 100, the output module 500, the second end voltage VGH, and the nth-level gate driving signal, and configured to boost voltages at two ends of the bootstrap module according to the nth-level gate driving signal and the first capacitor;
the shutdown module 600 is electrically connected to the nth level gate driving signal gate (N) and the second voltage terminal VGL, and configured to shutdown the nth level gate driving signal gate (N) during a touch scan period and keep a potential of the pixel driving circuit unchanged.
In the reset stage S40, the output terminal gate (n) of the output module 500 is connected to the second voltage terminal VGL by using the pull-down module 300, and the output terminal gate (n) of the output module 500 is pulled down, so that the gate voltage of the driving transistor in the pixel driving circuit in the display area is adjusted, thereby avoiding the problem of threshold voltage drift caused by long-term bias of the driving transistor in the pixel driving circuit in the display area, and improving the reliability of the driving transistor; the influence on the GOA circuit is avoided while the threshold voltage drift of the driving transistor is restrained.
The second voltage end VGL can be modulated by the central control board, and the voltage value of the second voltage end VGL can be determined by a reliability experiment, so that a proper voltage value for turning off the driving transistor is obtained.
The plurality of transistors in the pixel driving circuit in the display area are field effect transistors; further, a plurality of transistors in the pixel driving circuit in the display area are thin film transistors; furthermore, a plurality of transistors in the pixel driving circuit in the display area are oxide thin film transistors.
In some embodiments, the nth stage sub-circuit further comprises: a shutdown module 600;
the shutdown module 600 includes an eleventh transistor NT 11;
a control terminal of the eleventh transistor NT11 is electrically connected to the turn-off control signal, an input terminal of the eleventh transistor NT11 is electrically connected to the nth stage gate driving signal, and an output terminal of the eleventh transistor NT11 is electrically connected to the second voltage terminal.
In some embodiments, the nth stage sub-circuit further comprises: an output module 500 and a pull-down control module 200;
a first output terminal of the scan control module 100 is electrically connected to one end of the bootstrap module 400, and a second output terminal of the scan control module 100 is electrically connected to one end of the pull-down control module 200;
the other end of the bootstrap module 400 is electrically connected to the output module 500;
the other end of the pull-down control module 200 is electrically connected to one end of the pull-down module 300;
one end of the output module 500 is electrically connected to the other end of the pull-down module 300;
the input end of the shutdown module 600 is electrically connected to the output end of the output module 500, and the output end of the shutdown module 600 is electrically connected to the output end of the pull-down module 300.
In some embodiments, the scan control module 100 includes: a first transistor NT1, a second transistor NT2, a third transistor NT3, and a fourth transistor NT 4;
the control end of the first transistor NT1 is electrically connected to the nth-2 stage Gate driving signal Gate (N-2); an input end of the first transistor NT1 is electrically connected to the forward scan control signal U2D; the output end of the first transistor NT1 and the bootstrap module 400 are electrically connected to the first node q (n);
the control end of the second transistor NT2 is electrically connected to the (N +2) th stage Gate driving signal Gate (N + 2); an input terminal of the second transistor NT2 is electrically connected to the inverse scan control signal D2U; the output terminal of the second transistor NT2 and the pull-down control module 200 are electrically connected to the first node q (n);
a control end of the third transistor NT3 is electrically connected to the forward scan control signal U2D; an input end of the third transistor NT3 is electrically connected to the (N +2) th stage clock signal CK (N + 2); the output terminal of the third transistor NT3 and the pull-down control module 200 are electrically connected to the control terminal of the eighth transistor;
a control terminal of the fourth transistor NT4 is electrically connected to the reverse scan control signal D2U; an input end of the fourth transistor NT4 is electrically connected to the N-2 th stage clock signal CK (N-2); the output terminal of the fourth transistor NT4 and the pull-down control module 200 are electrically connected to the control terminal of the eighth transistor.
In some embodiments, the output module 500 includes: a ninth transistor NT 9;
the control end of the ninth transistor NT9 and the bootstrap module 400 are electrically connected to the second node qa (n); an input terminal of the ninth transistor NT9 is electrically connected to the nth stage clock signal ck (N); an output end of the ninth transistor NT9 is electrically connected to the nth stage gate driving signal gate (N).
In some embodiments, the pull-down control module 200 includes: a fifth transistor NT5 and an eighth transistor NT 8;
a control end of the eighth transistor NT8 is electrically connected to an output end of the third transistor NT 3; an input end of the eighth transistor NT8 is electrically connected to the first voltage terminal VGH; the output terminal of the eighth transistor NT8 and the pull-down module 300 are electrically connected to the input terminal of the fifth transistor NT 5;
the control terminal of the fifth transistor NT5 and the output terminal of the first transistor NT1 are electrically connected to the first node q (n); an input terminal of the fifth transistor NT5 is electrically connected to an output terminal of the eighth transistor NT 8; an output end of the fifth transistor NT5 is electrically connected to the second voltage terminal VGL.
In some embodiments, the pull-down module 300 includes: a sixth transistor NT6, a tenth transistor NT10, and a second capacitor C2;
the control terminal of the sixth transistor NT6 and the pull-down control module 200 are electrically connected to the input terminal of the fifth transistor; an input terminal of the sixth transistor NT6 and the bootstrap module 400 are electrically connected to the first node q (n); an output end of the sixth transistor NT6 is electrically connected to the second voltage terminal VGL;
a control terminal of the tenth transistor NT10 is electrically connected to an input terminal of the fifth transistor NT 5; an input end of the tenth transistor NT10 is electrically connected to the nth-stage gate driving signal gate (N); an output end of the tenth transistor NT10 is electrically connected to the second voltage terminal VGL;
a first end of the second capacitor C2 is electrically connected to the input end of the fifth transistor NT 5; a second end of the second capacitor C2 is electrically connected to the second voltage terminal VGL.
The present application further provides a driving method of a GOA circuit, configured to drive the GOA driving circuit in the display panel, where the GOA circuit includes: a cascaded multi-stage sub-circuit, an Nth stage sub-circuit of the multi-stage sub-circuit comprising: the system comprises a bootstrap module 400, a shutdown module 600, a scan control module 100, an output module 500, a pull-down control module 200 and a pull-down module 300; the bootstrap module 400 includes: a bootstrap capacitor C1, wherein one end of the bootstrap capacitor C1 is electrically connected to the nth stage gate driving signal, and the other end of the bootstrap capacitor C1 is electrically connected to the first node; the driving method of the GOA circuit comprises the following steps:
the bootstrap module receives an Nth-stage gate drive signal;
the bootstrap capacitor charges, and the voltage of the first node rises accordingly.
Specifically, at S10, after the bootstrap module 400 receives the first driving signal outputted by the scan control module 100 and the first voltage end is turned on, the first node q (N) becomes high, the first capacitor C1 starts to charge and the output module 500 is turned on, so that the output end of the output module 500 writes the nth stage clock signal ck (N);
s20, after the pull-down control module 200 receives the second driving signal output by the scan control module 100, the pull-down control module 200 controls the pull-down module 300 to operate, and the bootstrap module 400 turns to a low potential;
s30, after the shutdown module 600 receives the shutdown control signal, the shutdown module 600 is turned on, and the nth-stage gate driving signal changes to a low potential;
s40, after the bootstrap module 400 receives the low-potential signal outputted by the nth stage gate driving signal, the first capacitor C1 discharges to maintain the voltage of the first node q (N);
s50, when the nth gate driving signal outputs a high level signal, and the bootstrap module 400 receives the high level signal output by the nth gate driving signal, the first capacitor C1 starts to charge, and the voltage of the first node q (N) increases accordingly.
Referring to fig. 4, in the bootstrap module 400, an electrical connection point between the bootstrap capacitor C1 and the seventh transistor NT7 is a point q (n), an electrical connection point between the seventh transistor NT7 and the output module 500 is a point qa (n), and a change of the bootstrap voltage of the bootstrap capacitor C1 can be obtained by detecting potentials of the point q (n) and the point qa (n).
The touch scanning may occur after any one clock signal period is finished, and the touch scanning is started assuming that a touch scanning time period is entered after the nth row of pixel data is displayed.
When the GOA output of the nth row is high, the Q (N +2) point and the Qa (N +2) level in the Gate (N +2) of the GOA unit of the nth +2 stage are pulled high, and also during the touch scan period, the Q (N +2) point in the Gate (N +2) stage leaks through the input terminal and the output terminal of the transistor connected thereto, so that the voltage is reduced.
After the touch scanning is finished, when the nth level clock signal ck (N) outputs a high level, the voltage of the point Q (N +2) is bootstrapped to a high level higher than VGH by the bootstrap capacitor C1, which not only can compensate for a voltage drop caused by the leakage, but also avoid the leakage to the point Q (N +2) when the point Qa (N +2) is bootstrapped, and even reversely charge the point Qa (N +2), thereby improving the bootstrap capability of the ninth transistor NT9, and at the same time, the point Qa is bootstrapped to a high level by the parasitic capacitor of the ninth transistor NT9 in the output module 500, and finally, the Gate (N +2) of the GOA unit can be completely output.
The application also provides a display panel, which comprises the GOA circuit.
The application also provides a display device, which comprises the GOA circuit.
The display device can be a liquid crystal display device, a flexible display device and the like; furthermore, the GOA circuit is suitable for a high-resolution display device. Further, the flexible display device includes a light emitting device; furthermore, the light emitting device includes an organic light emitting diode, a sub-millimeter light emitting diode and a micro light emitting diode.
Specifically, the display device may be a mobile display device or a non-mobile display device, including a mobile phone, a tablet computer, a desktop computer, a bracelet, a learning machine, and the like.
In the display device, the GOA circuit is adopted to drive the driving transistor in the pixel driving circuit, so that the driving transistor can be prevented from being in a bias state for a long time, the threshold voltage drift of the driving transistor is improved, and the reliability of a plurality of transistors in the display area is improved. In addition, the second voltage end VGL can be adjusted according to actual requirements, so that the bias voltages of a plurality of transistors in the display area can be adjusted, and the fault tolerance of the display device is improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing describes in detail a GOA circuit, a display panel and a display device provided in an embodiment of the present invention, and a specific example is applied in the present disclosure to explain the principle and the implementation of the present invention, and the description of the foregoing embodiment is only used to help understanding the technical solution and the core idea of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A gate driver (GOA) circuit, comprising: a cascaded multi-stage sub-circuit, an Nth stage sub-circuit of the multi-stage sub-circuit comprising:
the device comprises a scanning control module, a pull-down module and a bootstrap module;
the output end of the scanning module is electrically connected with one input end of the pull-down module through a first node;
a bootstrapping module, the bootstrapping module comprising: a bootstrap capacitor and a seventh transistor;
one end of the bootstrap capacitor is electrically connected to the nth-stage gate driving signal, the other end of the bootstrap capacitor is electrically connected to the first node, an input end of the seventh transistor is electrically connected to the first node, a control end of the seventh transistor is electrically connected to the first voltage end, and an output end of the seventh transistor is electrically connected to the second node.
2. The GOA circuit of claim 1, wherein the Nth stage sub-circuit further comprises: closing the module;
the shutdown module includes an eleventh transistor;
a control end of the eleventh transistor is electrically connected to the turn-off control signal, an input end of the eleventh transistor is electrically connected to the nth-stage gate driving signal, and an output end of the eleventh transistor is electrically connected to the second voltage end.
3. The GOA circuit of claim 2, wherein the Nth stage sub-circuit further comprises: the pull-down control module is connected with the output module;
the output end of the scanning control module is electrically connected with one end of the bootstrap module, and the output end of the scanning control module is electrically connected with one end of the pull-down control module;
the other end of the bootstrap module is electrically connected with the output module;
the other end of the pull-down control module is electrically connected with one end of the pull-down module;
one end of the output module is electrically connected with the other end of the pull-down module;
the input end of the closing module is electrically connected with the output end of the output module, and the output end of the closing module is electrically connected with the output end of the pull-down module.
4. The GOA circuit of claim 3, wherein the scan control module comprises: a first transistor, a second transistor, a third transistor, and a fourth transistor;
the control end of the first transistor is electrically connected with the N-2 th level grid driving signal; the input end of the first transistor is electrically connected with the forward scanning control signal; the output end of the first transistor is electrically connected with the first node;
the control end of the second transistor is electrically connected with the (N +2) th-level grid driving signal; the input end of the second transistor is electrically connected with the reverse scanning control signal; the output end of the second transistor is electrically connected with the first node;
the control end of the third transistor is electrically connected with the forward scanning control signal; the input end of the third transistor is electrically connected with the (N +2) th-level clock signal; the output end of the third transistor is electrically connected with the control end of the eighth transistor;
the control end of the fourth transistor is electrically connected with the reverse scanning control signal; the input end of the fourth transistor is electrically connected with the N-2 level clock signal; and the output end of the fourth transistor is electrically connected with the control end of the eighth transistor.
5. The GOA circuit of claim 3, wherein the output module comprises: a ninth transistor;
the control end of the ninth transistor is electrically connected with the second node; the input end of the ninth transistor is electrically connected with the Nth-stage clock signal; the output end of the ninth transistor is electrically connected with the Nth-stage grid driving signal.
6. The GOA circuit of claim 4, wherein the pull-down control module comprises: a fifth transistor and an eighth transistor;
the control end of the eighth transistor is electrically connected with the output end of the third transistor; the input end of the eighth transistor is electrically connected with the first voltage end; the output end of the eighth transistor is electrically connected with the input end of the fifth transistor;
the control end of the fifth transistor is electrically connected with the first node; the input end of the fifth transistor is electrically connected with the output end of the eighth transistor; the output end of the fifth transistor is electrically connected with the second voltage end.
7. The GOA circuit of claim 6, wherein the pull-down module comprises: a sixth transistor, a tenth transistor, and a second capacitor;
the control end of the sixth transistor is electrically connected with the input end of the fifth transistor; an input end of the sixth transistor is electrically connected with the first node; the output end of the sixth transistor is electrically connected with the second voltage end;
a control end of the tenth transistor is electrically connected with an input end of the fifth transistor; an input end of the tenth transistor is electrically connected with the nth-stage gate driving signal; an output end of the tenth transistor is electrically connected with the second voltage end;
the first end of the second capacitor is electrically connected with the input end of the fifth transistor; a second terminal of the second capacitor is connected to the second voltage terminal.
8. The GOA circuit of claim 1, wherein the GOA circuit is a single stage driver circuit or the GOA circuit is a dual stage driver circuit.
9. A display panel comprising a GOA circuit according to any one of claims 1 to 8.
10. A display device, characterized in that it comprises a GOA circuit according to any one of claims 1 to 8.
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| US9659540B1 (en) * | 2015-07-20 | 2017-05-23 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA circuit of reducing power consumption |
| CN108010498A (en) * | 2017-11-28 | 2018-05-08 | 武汉华星光电技术有限公司 | A kind of GOA circuits and liquid crystal panel, display device |
| CN108010495A (en) * | 2017-11-17 | 2018-05-08 | 武汉华星光电技术有限公司 | A kind of GOA circuits |
| KR20190063624A (en) * | 2017-11-30 | 2019-06-10 | 엘지디스플레이 주식회사 | Gate driving circuit and light emitting display apparatus comprising the same |
| CN111681625A (en) * | 2020-06-23 | 2020-09-18 | 武汉华星光电技术有限公司 | Drive circuit, display panel and display device |
| CN112102768A (en) * | 2020-10-15 | 2020-12-18 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9659540B1 (en) * | 2015-07-20 | 2017-05-23 | Shenzhen China Star Optoelectronics Technology Co., Ltd. | GOA circuit of reducing power consumption |
| CN108010495A (en) * | 2017-11-17 | 2018-05-08 | 武汉华星光电技术有限公司 | A kind of GOA circuits |
| CN108010498A (en) * | 2017-11-28 | 2018-05-08 | 武汉华星光电技术有限公司 | A kind of GOA circuits and liquid crystal panel, display device |
| KR20190063624A (en) * | 2017-11-30 | 2019-06-10 | 엘지디스플레이 주식회사 | Gate driving circuit and light emitting display apparatus comprising the same |
| CN111681625A (en) * | 2020-06-23 | 2020-09-18 | 武汉华星光电技术有限公司 | Drive circuit, display panel and display device |
| CN112102768A (en) * | 2020-10-15 | 2020-12-18 | 武汉华星光电技术有限公司 | GOA circuit and display panel |
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| CN113223475B (en) | 2022-09-09 |
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