CN113220610B

CN113220610B - Communication system and communication method and device of SPI interface

Info

Publication number: CN113220610B
Application number: CN202010071523.0A
Authority: CN
Inventors: 夏佳欣
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-01-21
Filing date: 2020-01-21
Publication date: 2024-04-09
Anticipated expiration: 2040-01-21
Also published as: CN113220610A

Abstract

The application provides a communication system and a communication method and device of an SPI interface. The communication system includes: a master device and at least one slave device. The master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three general purpose GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device. For any channel, configuring the level state of a GPIO interface in the channel based on a transmitted transaction by any one of the master device and the slave device; and based on the level state of the GPIO interface in the channel, data can be transmitted in two directions through the SPI interface in the channel. Thus, high-speed transmission of non-timed and/or non-fixed length data between the master device and the slave device is realized.

Description

Communication system and communication method and device of SPI interface

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a communications method and apparatus for a communications system and an SPI interface.

Background

The serial peripheral interface (serial peripheral interface, SPI) is typically composed of four wires, clock (SCK), master data out (master out slave in, MOSI), master data in (master in slave out, MISO) and Chip Select (CS), and can enable communication between the master (master) and slave (slave).

FIG. 1 shows a schematic diagram of the connection of an SPI interface between a master device and a slave device. As shown in fig. 1, the SCK line of the master device is connected to the SCK line of the slave device, and is used for the master device to transmit a clock signal to the slave device, so that the data can complete the data transmission based on the clock signal. The MOSI line of the master device is connected to the MOSI line of the slave device, wherein the MOSI line is used to implement a function that the master device transmits data and the slave device receives data, so that the master device can transmit (write) data to the slave device. The MISO line of the master device is connected to the MISO line of the slave device, wherein the MISO line is used to implement a function of transmitting data from the slave device and receiving data by the master device so that the slave device can transmit (write) data to the master device. The CS line of the master device is connected to the CS line of the slave device for the master device to send a chip select signal to the slave device to gate the slave device.

Advantages of the SPI interface include: 1. and the hardware design of four wires of the SPI interface is corresponding to the software of the SPI interface, so that the communication rate of the SPI interface is high. 2. Based on the connection relation shown in fig. 1, the master device and the slave device can send data simultaneously, so that full duplex communication of the SPI interface can be realized.

Drawbacks of the SPI interface include: 1. the slave device needs to receive the clock signal from the master device first to be able to send data to the master device, resulting in inflexible communication process. 2. When the clock signal exists, even if the master device does not send (write) data to the slave device, the slave device can still read the 'garbage data', so that an additional data frame structure needs to be set in the clock signal for elimination, and the clock signal has additional overhead, thereby wasting the data processing capacity of the master device. 3. The SPI interface has no underlying flow control mechanism, nor underlying determination (reply) mechanism.

Based on the advantages and disadvantages of the SPI interface, the SPI interface can only be applied in the field of data transmission with fixed duration or fixed quantity, such as a data interface of a liquid crystal display (Liquid Crystal Display, LCD), a read-write interface of a storage device or a drive interface of an analog-to-digital converter (A/D) and a digital-to-analog converter (D/A), and the like, and the SPI interface has the defects of being not wide enough in application.

Therefore, how to implement data non-timing and/or non-fixed length SPI interface communication between a master device and a slave device is in need of solution.

Disclosure of Invention

The application provides a communication system and a communication method and a device of an SPI interface, so that non-timing and/or non-fixed-length data transmission between a master device and a slave device is realized through the SPI interface, bidirectional and high-speed communication of data is ensured, and the communication performance of the system is improved.

In a first aspect, the present application provides a communication system comprising: a master device and at least one slave device;

the master device and any slave device are provided with at least one channel, each channel comprises a Serial Peripheral Interface (SPI) interface and at least three general purpose input/output (GPIO) interfaces associated with the SPI interface, and each GPIO interface is set into an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device;

for any channel, the master device and any one device in the slave devices configure the level state of the GPIO interface in the channel based on the transmitted transaction; and based on the level state of the GPIO interface in the channel, data can be transmitted in two directions through the SPI interface in the channel.

According to the communication system provided by the first aspect, for any channel, the level state of the GPIO interface in the channel can be configured by the master device and any one of the slave devices based on the transmitted transaction, and based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the transaction corresponding to the level state of the GPIO interface in the channel between the master device and the slave device can be synchronized, so that unnecessary clock signals are avoided being wasted, communication resources such as clock signals are identified or the boundary of the clock signals are judged, communication resources are ensured to be provided in a proper time period, the communication resources are reasonably used, the waste of the communication resources is reduced, the communication requirement of small resource consumption between the master device and the slave device is met, and data can be transmitted in two directions through the SPI interface in the channel.

In one possible design, when each GPIO interface is high in the initial level state of the GPIO interfaces in the channel, the master device or the slave device configures the level state of the GPIO interfaces in the channel by pulling low the high level of at least one GPIO interface based on the transmitted transaction. In this way, the characteristics of better processing capacity of the master device and higher real-time performance of the slave device are combined, and the response speed is improved, so that the master device and the slave device can quickly acquire the level state of the GPIO interface in the current channel, the communication time is saved, and the high-speed transmission of data is facilitated.

In one possible design, the master device configures a level state of the GPIO interface in the channel to be a first state based on a data transmission transaction, where the first state is used to indicate that the master device requests to send data to the slave device; when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device meets a receiving condition, configuring the level state of the GPIO interface in the channel as a second state, wherein the second state is used for notifying the master device that the slave device meets the receiving condition; and when the first state is switched to the second state, the master device sends data to the slave device through the SPI interface in the channel. In this way, the master device can determine that the slave device meets the receiving condition, and can send data to the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and the data transmission transaction is completed.

In one possible design, when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device does not meet the receiving condition, the level state of the GPIO interface in the channel is configured to be a third state, where the third state is used to notify the master device that the slave device does not meet the receiving condition; and when the first state is switched to the third state, the master device determines that the slave device refuses to receive data. In so doing, the master device may determine that the slave device refuses to receive data, ensuring that the master device reliably and efficiently transfers data to the slave device, completing the flow control mechanism transaction, so as to provide the slave device with the right to refuse to receive data.

In one possible design, the master device configures a level state of the GPIO interface in the channel to be a fourth state based on a response mechanism transaction, where the fourth state is used to indicate that the master device inquires the slave device that the data received by the slave device is accurate; when the slave device switches from the initial level state to the fourth state, configuring the level state of the GPIO interface in the channel to be a fifth state based on a response mechanism transaction, wherein the fifth state is used for indicating that the data received by the slave device from the master device is accurate; and when the fourth state is switched to the fifth state, the master device determines that the data received by the slave device from the master device is accurate. In so doing, the master device may determine that the data received by the slave device from the master device is accurate, and does not need to resend the data to the slave device again, completing the reply mechanism transaction.

In one possible design, the master device retransmits data to the slave device through the SPI interface in the channel based on a data retransmission transaction when the fourth state is not switched to the fifth state for a first preset period of time. In so doing, accuracy of data received by the slave device from the master device is ensured, and the data retransmission transaction is completed.

In one possible design, the master device configures a level state of the GPIO interface in the channel to be a sixth state based on a polling mechanism transaction, where the sixth state is used to indicate that the master device inquires whether the slave device has data to send to the master device; when the initial level state of the GPIO interface in the channel of the slave device is switched to the sixth state, if the slave device has data to be sent to the master device, configuring the level state of the GPIO interface in the channel to be a seventh state, wherein the seventh state is used for informing the master device that the slave device has data to be sent; and when the sixth state is switched to the seventh state, the master device receives data from the slave device through the SPI interface in the channel. In this way, the master device can determine that the slave device has data to send, and can receive the data from the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and the polling mechanism transaction is completed.

In one possible design, when the slave device switches to the sixth state in the initial level state of the GPIO interface in the channel, if the slave device does not have data to send to the master device, the level state of the GPIO interface in the channel is configured to be an eighth state, where the eighth state is used to notify the master device that the slave device does not have data to send; and when the master device is switched to the eighth state from the sixth state, the slave device is determined that no data needs to be sent. In so doing, the master device may determine that the slave device has no data to send to the master device, saving unnecessary communication resources, and completing the polling mechanism transaction.

In one possible design, the master device configures a level state of the GPIO interface in the channel to be a ninth state based on a reply mechanism transaction, where the ninth state is used to indicate that data received by the master device from the slave device is accurate; and when the initial level state of the GPIO interface in the channel is switched to the ninth state, the slave device determines that the data received by the master device from the slave device is accurate. In this way, the slave device can determine that the data received by the master device from the slave device is accurate, and the data does not need to be resent to the master device again, so that the response mechanism transaction is completed.

In one possible design, the slave device retransmits data to the master device through the SPI interface in the channel based on a data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state for a second preset period of time. In so doing, the accuracy of the data received by the master device from the slave device is ensured, and the data retransmission transaction is completed.

In one possible design, when the master device or the slave device completes a transmitted transaction or detects that an internal logic is wrong or detects that a GPIO interface in the channel is wrong in a transmitted transaction, configuring the level state of the GPIO interface in the channel to be a tenth state, where the tenth state is used for indicating the master device and/or the slave device to reset the level state of the GPIO interface in the channel; and the master device or the slave device configures the level state of the GPIO interface in the channel to be the initial level state based on the tenth state. In this way, the master device or the slave device can reset the level state of the GPIO interface in the channel when the transmitted transaction is completed, can reset the level state of the GPIO interface in the channel when the internal logic of the master device or the slave device is wrong, can reset the level state of the GPIO interface in the channel when the wrong level state of the GPIO interface in the channel is detected, not only solves the problem that the transmitted transaction cannot be normally completed due to the confusion of the internal logic of the master device or the slave device, but also is beneficial to timely knowing that the internal logic of the master device or the slave device is wrong, and is convenient for prompting an operator to check and replace the master device or the slave device, and also solves the problem that the transmitted transaction cannot be successfully performed due to the fact that the master device or the slave device cannot recognize the wrong level state of the GPIO interface in the channel, thereby being beneficial to error correction of the level state of the GPIO interface in the channel by the master device or the slave device, preventing the master device or the slave device from being dead-down, and facilitating the first device to realize the next transmitted transaction.

In a second aspect, the present application provides a communication method of an SPI interface, where the communication method of the SPI interface is applied to a communication system, the communication system including: a master device and at least one slave device; the master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device.

For any channel, when the first device is any one device of the master device and the slave device, the method includes: the first device configures the level state of the GPIO interface in the channel based on the transmitted transaction; the first device can bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

The communication method of the SPI interface provided by the second aspect is applied to a communication system, and the communication system comprises a master device and at least one slave device, wherein the master device and any slave device are provided with at least one channel, each channel comprises one SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode. According to the method, for any channel, the level state of the GPIO interface in the channel can be configured based on the transmission transaction of any one of the master device and the slave device, and based on the connection relationship of the GPIO interface in the channel between the master device and the slave device, the transaction corresponding to the level state of the GPIO interface in the channel between the master device and the slave device can be synchronized, so that unnecessary clock signals are avoided being wasted, clock signals are identified or communication resources such as boundaries of the clock signals are judged, communication resources are required to be provided in a proper time period, the communication resources are reasonably used, the waste of the communication resources is reduced, the communication requirements of small resource consumption between the master device and the slave device are met, data can be transmitted in a bidirectional mode through the SPI interface in the channel, the method is not only suitable for transmitting timing and/or fixed-length data, but also suitable for transmitting non-timing and/or non-fixed-length data, the reliability of the system is guaranteed, and the reliability of the system is improved.

In one possible design, when each GPIO interface is high in an initial level state of the GPIO interfaces in the channel, the first device configures the level state of the GPIO interfaces in the channel based on the transmitted transaction, including: the first device configures a level state of the GPIO interface in the channel by pulling low a high level of at least one GPIO interface based on the transmitted transaction. In this way, the characteristics of better processing capacity of the master device and higher real-time performance of the slave device are combined, and the response speed is improved, so that the master device and the slave device can quickly acquire the level state of the GPIO interface in the current channel, the communication time is saved, and the high-speed transmission of data is facilitated.

In one possible design, the first device configures a level state of the GPIO interface in the channel based on the transmitted transaction, including: the master device configures the level state of the GPIO interface in the channel to be a first state based on a data transmission transaction, wherein the first state is used for indicating that the master device requests to send data to the slave device; when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device meets a receiving condition, configuring the level state of the GPIO interface in the channel as a second state, wherein the second state is used for notifying the master device that the slave device meets the receiving condition; the first device may bi-directionally transmit data through the SPI interface in the channel based on a level state of the GPIO interface in the channel, including: and when the first state is switched to the second state, the master device sends data to the slave device through the SPI interface in the channel. In this way, the master device can determine that the slave device meets the receiving condition, and can send data to the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and the data transmission transaction is completed.

In one possible design, the method further comprises: when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device does not meet the receiving condition, configuring the level state of the GPIO interface in the channel to be a third state based on a flow control mechanism transaction, wherein the third state is used for notifying the master device that the slave device does not meet the receiving condition; and when the first state is switched to the third state, the master device determines that the slave device refuses to receive data. In so doing, the master device may determine that the slave device refuses to receive data, ensuring that the master device reliably and efficiently transfers data to the slave device, completing the flow control mechanism transaction, so as to provide the slave device with the right to refuse to receive data.

In one possible design, the method further comprises: the master device configures the level state of the GPIO interface in the channel to be a fourth state based on a response mechanism transaction, wherein the fourth state is used for indicating that the master device inquires the slave device to inform the master device that the received data of the slave device are accurate; when the slave device switches from the initial level state to the fourth state, configuring the level state of the GPIO interface in the channel to be a fifth state based on a response mechanism transaction, wherein the fifth state is used for indicating that the data received by the slave device from the master device is accurate; and when the fourth state is switched to the fifth state, the master device determines that the data received by the slave device from the master device is accurate. In so doing, the master device may determine that the data received by the slave device from the master device is accurate, and does not need to resend the data to the slave device again, completing the reply mechanism transaction.

In one possible design, the method further comprises: and when the fourth state is not switched to the fifth state after the first preset time period passes, the master equipment resends data to the slave equipment through the SPI interface in the channel based on the data resending transaction. In so doing, accuracy of data received by the slave device from the master device is ensured, and the data retransmission transaction is completed.

In one possible design, the first device configures a level state of the GPIO interface in the channel based on the transmitted transaction, including: the master device configures the level state of the GPIO interface in the channel to be a sixth state based on a polling mechanism transaction, wherein the sixth state is used for indicating that the master device inquires whether the slave device has data to be sent to the master device; when the initial level state of the GPIO interface in the channel of the slave device is switched to the sixth state, if the slave device has data to be sent to the master device, configuring the level state of the GPIO interface in the channel to be a seventh state, wherein the seventh state is used for informing the master device that the slave device has data to be sent; the first device may bi-directionally transmit data through the SPI interface in the channel based on a level state of the GPIO interface in the channel, including: and when the sixth state is switched to the seventh state, the master device receives data from the slave device through the SPI interface in the channel. In this way, the master device can determine that the slave device has data to send, and can receive the data from the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and the polling mechanism transaction is completed.

In one possible design, the method further comprises: when the slave device switches to the sixth state in the initial level state of the GPIO interface in the channel, if the slave device does not have data to send to the master device, configuring the level state of the GPIO interface in the channel to be an eighth state, where the eighth state is used for notifying the master device that the slave device does not have data to send; and when the master device is switched to the eighth state from the sixth state, the slave device is determined that no data needs to be sent. In so doing, the master device may determine that the slave device has no data to send to the master device, saving unnecessary communication resources, and completing the polling mechanism transaction.

In one possible design, the method further comprises: the master device configures the level state of the GPIO interface in the channel to be a ninth state based on the response mechanism transaction, wherein the ninth state is used for indicating that the data received by the master device from the slave device is accurate; and when the initial level state of the GPIO interface in the channel is switched to the ninth state, the slave device determines that the data received by the master device from the slave device is accurate. In this way, the slave device can determine that the data received by the master device from the slave device is accurate, and the data does not need to be resent to the master device again, so that the response mechanism transaction is completed.

In one possible design, the method further comprises: and the slave device retransmits data to the master device through the SPI interface in the channel based on a data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state after the second preset time length. In so doing, the accuracy of the data received by the master device from the slave device is ensured, and the data retransmission transaction is completed.

In one possible design, the method further comprises: when the first device completes a transmitted transaction or detects that an internal logic is wrong or detects that a level state of a GPIO interface in the channel is wrong in the transmitted transaction, configuring the level state of the GPIO interface in the channel to be a tenth state, wherein the tenth state is used for indicating the master device and/or the slave device to reset the level state of the GPIO interface in the channel; the first device configures a level state of the GPIO interface in the channel to be the initial level state based on the tenth state. By doing so, the level state of the GPIO interface in the channel is reset, so that the first device can conveniently realize the next transmitted transaction.

The advantages of the second aspect and the network device provided in the foregoing second aspect and the possible designs of the second aspect may be referred to the advantages brought by the foregoing first aspect and the possible implementations of the first aspect, which are not described herein again.

In a third aspect, the present application provides a communication apparatus of an SPI interface, which is generally referred to as a first device, and is configured to implement operations corresponding to the first device in each possible implementation manner of the second aspect and the second aspect, where the first device is any one of a master device and the slave device in a communication system, and the communication system may include the master device and at least one slave device. The master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device.

The communication device of the SPI interface of the present application may include: a configuration module and a transmission module.

The configuration module is used for configuring the level state of the GPIO interface in any channel based on the transmitted transaction;

and the transmission module is used for the first equipment to bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

In one possible design, the configuration module is configured to configure the level state of the GPIO interfaces in the channel by pulling low the high level of at least one GPIO interface based on the transmitted transaction when each GPIO interface in the initial level state of the GPIO interfaces in the channel is high.

In one possible design, the configuration module is configured to configure, based on a data transmission transaction, a level state of a GPIO interface in the channel to be a first state when the communication device of the SPI interface is a master device, where the first state is used to indicate that the master device requests to send data to the slave device; when the communication device of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the first state, if the slave device meets a receiving condition, configuring the level state of the GPIO interface in the channel to be a second state, wherein the second state is used for notifying the master device that the slave device meets the receiving condition;

And the transmission module is used for transmitting data to the slave equipment through the SPI interface in the channel when the communication device of the SPI interface is the master equipment and the first state is switched to the second state.

In one possible design, the configuration module is further configured to, when the communication device of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the first state, configure, based on a flow control mechanism transaction, the level state of the GPIO interface in the channel to be a third state, where the third state is used to notify the master device that the slave device does not meet the receiving condition, if the slave device does not meet the receiving condition; and when the communication device of the SPI interface is a master device and the first state is switched to the third state, determining that the slave device refuses to receive data.

In one possible design, the configuration module is further configured to, when the communication device of the SPI interface is a master device, configure, based on a response mechanism transaction, a level state of the GPIO interface in the channel to be a fourth state, where the fourth state is used to indicate that the master device inquires about the slave device that the data received by the slave device is accurate to the master device; when the communication device of the SPI interface is a slave device and the initial level state is switched to the fourth state, configuring the level state of the GPIO interface in the channel to be a fifth state based on a response mechanism transaction, wherein the fifth state is used for indicating that the data received by the slave device from the master device is accurate; and when the communication device of the SPI interface is a master device and the fourth state is switched to the fifth state, determining that the data received by the slave device from the master device is accurate.

In some embodiments, the transmission module is further configured to, when the communication device of the SPI interface is a master device, retransmit data to the slave device through the SPI interface in the channel based on a data retransmission transaction when the fourth state is not switched to the fifth state after a first preset period of time.

In one possible design, the configuration module is configured to, when the communication device of the SPI interface is a master device, configure, based on a polling mechanism transaction, a level state of the GPIO interface in the channel to be a sixth state, where the sixth state is used to indicate that the master device inquires whether the slave device has data to send to the master device; when the communication device of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the sixth state, if the slave device has data to be sent to the master device, configuring the level state of the GPIO interface in the channel to be a seventh state, wherein the seventh state is used for notifying the master device that the slave device has data to be sent;

and the transmission module is used for receiving data from the slave device through the SPI interface in the channel when the communication device of the SPI interface is a master device and the sixth state is switched to the seventh state.

In one possible design, the configuration module is further configured to, when the communication device of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the sixth state, configure the level state of the GPIO interface in the channel to be an eighth state if the slave device has no data to send to the master device, where the eighth state is used to notify the master device that the slave device has no data to send; and when the communication device of the SPI interface is a master device and the sixth state is switched to the eighth state, determining that the slave device has no data to send.

In some embodiments, the configuration module is further configured to, when the communication device of the SPI interface is a master device, configure, based on a response mechanism transaction, a level state of the GPIO interface in the channel to be a ninth state, where the ninth state is used to indicate that data received by the master device from the slave device is accurate; and when the communication device of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the ninth state, determining that the data received by the master device from the slave device is accurate.

In one possible design, the transmission module is further configured to, when the communication device of the SPI interface is a slave device, retransmit data to the master device through the SPI interface in the channel based on a data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state after a second preset period of time.

In one possible design, the configuration module is further configured to configure the level state of the GPIO interface in the channel to be a tenth state when the transmitted transaction is completed or an internal logic error is detected or an error level state of the GPIO interface in the channel is detected in the transmitted transaction, where the tenth state is used to instruct the master device and/or the slave device to reset the level state of the GPIO interface in the channel; and based on the tenth state, configuring the level state of the GPIO interface in the channel to be the initial level state.

The advantages of the third aspect and the network device provided in each possible design of the third aspect may be referred to the advantages brought by each possible implementation of the second aspect and the second aspect, which are not described herein.

In a fourth aspect, the present application provides a communication device comprising: a memory and a processor;

the memory is used for storing program instructions;

the processor is configured to invoke program instructions in the memory to perform the communication method of the SPI interface in the second aspect and any possible designs of the second aspect.

In a fifth aspect, the present application provides a readable storage medium having stored therein execution instructions which, when executed by at least one processor of a communication device, perform the communication method of the SPI interface in any of the second aspect and the possible designs of the second aspect.

In a sixth aspect, the present application provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the communication device may read the execution instructions from the readable storage medium, the execution of the execution instructions by the at least one processor causing the communication device to implement the communication method of the SPI interface in the second aspect and any one of the possible designs of the second aspect.

In a seventh aspect, the present application provides a chip, where the chip is connected to a memory, or the chip has a memory integrated thereon, and when a software program stored in the memory is executed, the communication method of the SPI interface in any one of the second aspect and the second aspect possible design is implemented.

Drawings

FIG. 1 is a schematic diagram of a connection of an SPI interface between a master device and a slave device;

fig. 2 is a schematic structural diagram of a communication system according to an embodiment of the present application;

fig. 3 is a schematic connection diagram of one GPIO interface in a master device and a corresponding GPIO interface in a slave device according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating a communication method of an SPI interface according to one embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a vehicle network system according to an embodiment of the present disclosure;

FIG. 6 is a schematic illustration of a scenario in which two-way communication between a master device and a slave device in the on-board TBOX of FIG. 5 is performed;

fig. 7 is a schematic state diagram of three GPIO interfaces according to an embodiment of the present application;

FIG. 8 is a schematic diagram of states of three GPIO interfaces and one SPI interface in FIG. 7;

FIG. 9 is a schematic diagram showing the states of three GPIO interfaces and one SPI interface in FIG. 7;

FIG. 10 is a schematic diagram showing states of three GPIO interfaces in FIG. 7;

FIG. 11 is a schematic diagram showing states of three GPIO interfaces and one SPI interface in FIG. 7;

FIG. 12 is a schematic diagram showing the states of three GPIO interfaces and one SPI interface in FIG. 7;

FIG. 13 is a schematic diagram showing states of three GPIO interfaces in FIG. 7;

fig. 14 is a schematic structural diagram of a communication device with an SPI interface according to an embodiment of the present disclosure;

Fig. 15 is a schematic hardware structure of a communication device according to an embodiment of the present application.

Detailed Description

The application provides a communication system, a communication method, a device, communication equipment and a computer storage medium of an SPI interface, wherein the level state can be determined based on an open-drain mode of the GPIO interface, so that data can be transmitted at a high speed in a non-timing and/or non-fixed length mode through the SPI interface between a master device and a slave device, the resource consumption can be reduced, the bidirectional communication of the SPI interface between the master device and the slave device can be realized, meanwhile, the communication process is flexible and convenient, the practicability of the SPI interface can be improved, and the communication system is suitable for application scenes with low requirements on various resource consumption and high requirements on transmission rate.

The following describes in detail, through specific embodiments, a specific structure of the communication system of the present application and a specific implementation procedure of the communication method of the SPI interface of the present application.

Fig. 2 is a schematic structural diagram of a communication system according to an embodiment of the present application. As shown in fig. 2, the communication system of the present application may include: a master device and at least one slave device to implement respective functions by the master device and at least one slave device functions.

The specific implementation of the communication system is not limited in this application, and may be a communication terminal such as a wireless access point (wireless access point, AP), an optical network device (optical network terminal, ONT), and a router. And the host device may be referred to as a host or a host chip. The master device is typically a relatively powerful device. The main equipment can run a multi-task operating system, can process complex services, has strong data computing capability, and often has poor real-time performance. The slave device is usually a device with better real-time performance. The slave device may be referred to as a slave or a secondary chip. The slave device can run a real-time operating system, so that the processing capacity is poor, but the real-time performance is often good. And the interrupt request of hardware in the real-time operating system is usually more than the terminal request of hardware in the multi-task operating system, so the master device often corresponds to one or the other slave device. The number of master devices and slave devices is not limited in this application. For ease of illustration, fig. 2 illustrates one master device and one slave device, and the SPI interface uses four lines, SCK line, MOSI line, MISO line, and CS line, as in the conventional art. The MOSI line and the MISO line may be high-level logic (i.e., high-level) or low-level logic (i.e., low-level) for transmitting the clock signal, which is not limited in this application.

In the application, the first device is any one of a master device and any one of slave devices, the first device is provided with one or more channels, each channel can comprise an SPI interface and three or more GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode.

That is, each channel may separate a control channel from a data channel, wherein the control channel is formed by at least three GPIO interfaces and the data channel is formed by one SPI interface, such that the correlation between one SPI interface and at least three GPIO interfaces in each channel is achieved.

It will be appreciated by those skilled in the art that to achieve both input and output functions, each GPIO interface is typically set in a leaky mode with a pull-up resistor connected to each GPIO interface so that the GPIO interface is capable of bi-directionally inputting and outputting high level logic and low level logic. In addition, the level states represented by the at least three GPIO interfaces may include at least 2 ³ The first device can conveniently use at least 8 level states by using the number of the SPI interfaces between the master device and the slave devices to realize bidirectional communication.

For convenience of explanation, on the basis of the embodiment shown in fig. 2, a specific implementation process of connecting one GPIO interface in the master device with a corresponding GPIO interface in the slave device is illustrated with reference to fig. 3.

Fig. 3 shows a schematic connection diagram of one GPIO interface in a master device and a corresponding one in a slave device. As shown in fig. 3, the write register in the master device may write the level of the GPIO interface to the GPIO interface, the read register in the master device may read the level of the GPIO interface from the GPIO interface, the write register in the slave device may write the level of the GPIO interface to the GPIO interface, and the read register in the slave device may read the level of the GPIO interface from the GPIO interface, and the specific logic truth table is shown in table 1.

TABLE 1

In summary, the level of the GPIO interface read from the read register in the master device depends on the content of the write register in the master device and the content of the write memory in the slave device, i.e. when the write register in the master device writes high level logic to the GPIO interface and the write register in the slave device writes high level logic to the GPIO interface, the level of the GPIO interface read from the read register in the master device is high.

And the level read from the read register in the slave device to the GPIO interface depends on the contents of the write register in the master device and the contents of the write memory in the slave device, i.e. when the write register in the master device writes high level logic to the GPIO interface and the write register in the slave device writes high level logic to the GPIO interface, the level read from the read register in the slave device to the GPIO interface is high.

The read register and the write register corresponding to the SPI interface and the GPIO interface are driven by an internal software program of the first device. The internal software program is stored on a code Memory of the first device, such as a charged erasable programmable read-only Memory (electrically erasable programmable read only Memory, EEPROM) or FLASH Memory (FLASH Memory). A corresponding communication driver exists between the master device and the slave device, and the communication driver is used for transmitting data and level states upwards and controlling read registers and write registers of the SPI interface and the GPIO interface downwards, so that software and hardware support is provided for realizing bidirectional communication between the master device and the slave device.

The pull-up resistor in fig. 3 may be included in the master device or the slave device, or may be provided to the master device and the slave device through the communication system, which is not limited in this application. In addition, the level conversion circuit is used for realizing level conversion, so that the master device or the slave device can receive the level suitable for the master device or the slave device. The level conversion circuit can be contained in a communication system or not, and is specifically set according to actual requirements. For convenience of explanation, fig. 3 illustrates an example in which the level shift circuit is included in the communication system and the pull-up resistor is not included in the master device or the slave device.

The bidirectional communication between the master device and the slave device mentioned in the present application may be understood as the first device having the capability to send and/or receive data. The specific representation may include: unidirectional data transmission can be realized between the master device and the slave device, 1, the master device sends data to the slave device; 2. the slave device transmits data to the master device. The two-way data transmission can be realized between the master device and the slave device, 1, when the master device is transmitting data to the slave device, the slave device can start transmitting data to the master device; 2. the master device may begin transmitting data to the slave device while the slave device is transmitting data to the master device.

Wherein the number of channels in the master device may be the same as or different from the number of channels in the slave device. The number of SPI interfaces in the master device may be the same as or different from the number of SPI interfaces in the slave device. The number of GPIO interfaces in the master device may be the same as or different from the number of GPIO interfaces in the slave device. The number of GPIO interfaces in each channel in the first device may be the same or different. The present application is not limited to the above. The parameter configuration such as clock frequency, clock polarity or clock phase of the SPI interface is not limited.

In the application, in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any slave device, so that the master device and the slave device can realize data transmission and/or reception through the SPI interface, and the GPIO interfaces of the master device and the GPIO interfaces of the slave device are electrically connected, namely at least three GPIO interfaces in the master device are respectively and correspondingly electrically connected with at least three GPIO interfaces in the slave device one by one, so that the master device and the slave device can acquire the level state of the GPIO interfaces. That is, the master device may not have any other GPIO interface except the GPIO interface connected to the GPIO interface in any slave device, or may have a GPIO interface not connected to any slave device, which is not limited in this application. For ease of illustration, one channel is illustrated in fig. 2.

Next, with reference to fig. 2, a specific implementation procedure of the communication method of the SPI interface provided in the present application will be described with respect to any channel by using the first device as an execution body.

Fig. 4 is a flow chart of a communication method of an SPI interface provided in an embodiment of the present application, and as shown in fig. 4, the communication method of an SPI interface provided in the present application may include:

S101, the first device configures the level state of the GPIO interface in the channel based on the transmitted transaction.

In the present application, the first device may determine a transaction that the first device needs to transmit currently, where the transaction may be understood as a specific function implemented by interaction between the master device and the slave device through multiple execution steps, such as a data transmission transaction (including a data receiving transaction and a data sending transaction), a data temporary sending transaction, a data temporary receiving transaction, a data retransmission transaction, a flow control mechanism transaction (i.e. a transaction that refuses to receive data), a response mechanism transaction (i.e. a transaction that requests and responds to post-send data), or a polling mechanism transaction (i.e. a transaction that inquires whether the data is sent and received after the data is sent), and so on.

Since one level state usually corresponds to one execution step, and in order to realize bidirectional communication between the master device and the slave device, the first device may implement one or more transactions, and at least two or more execution steps exist in any one transaction, in this application, the master device and the slave device may negotiate in advance which level state of the GPIO interface in any one channel may indicate which transaction or which execution step in which transaction, or a switching process of the level state of the GPIO interface in any one channel may indicate which transaction or which execution step in which transaction, which application is not limited in this application.

The first device may store the level state of the GPIO interface in any channel in real time, or store the level state of the GPIO interface before and after switching in any channel, so that the first device may grasp the situation corresponding to the currently transmitted transaction in real time. The specific transaction or the execution step of the transaction corresponding to each level state can be set according to the actual situation or the experience value, and the specific corresponding relation is not limited.

In the application, for any channel, the first device may configure the level state of the GPIO interface in the channel based on the transaction that needs to be transmitted currently, so that the master device and the slave device corresponding to the channel may acquire the level state of the GPIO interface in the channel. In so doing, transactions transferred between the master and slave devices are synchronized so that the master device need not waste unnecessary clock signals to enable communication with the slave devices.

S102, the first device can bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

In the application, when the level state of the GPIO interface in the channel is configured, based on the connection relationship of the GPIO interface between the master device and the slave device in the channel, the first device can determine the transaction corresponding to the level state of the GPIO interface in the channel, so that the master device and the slave device make preparation for data transmission, and the process of bidirectionally transmitting data at high speed is realized through the SPI interface in the channel.

When the master device configures the level state of the GPIO interface in any channel, based on the connection relationship between the GPIO interfaces in the channel and the slave device, not only the master device may determine the level state of the GPIO interface in the channel, but also the slave device may determine the level state of the GPIO interface in the channel. When the slave device configures the level state of the GPIO interface in any channel, based on the connection relationship between the GPIO interface in the channel and the master device, not only the slave device can determine the level state of the GPIO interface in the channel, but also the master device can determine the level state of the GPIO interface in the channel.

Compared with the SPI interface, when a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface is adopted to realize communication between a master device and a slave device, the UART interface supports full duplex communication, but the biggest disadvantage of the UART interface is that the communication rate is low, usually up to 4Mbps, which is far less than the maximum communication rate of the SPI interface. Moreover, the UART interface is synchronized by the start bit and the stop bit, so that the communication effect is affected by unstable or inaccurate communication frequency, and the above problem becomes more obvious along with the continuous increase of the communication rate.

Compared with an SPI interface, when the communication between the master device and the slave device is realized by adopting the I2C interface, the I2C interface has the defect of low communication rate, is suitable for low-speed transmission of data, and does not support full duplex communication.

Compared with the prior art that data transmission is realized by only adopting an SPI interface, in the method, the level state of the GPIO interface in any channel is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the transaction required to be transmitted between the master device and the slave device is synchronized, unnecessary resource consumption such as clock signal consumption, clock signal identification or clock signal boundary judgment between the master device and the slave device is reduced, a great deal of expenditure of communication resources is saved, small communication requirements of the resource consumption between the master device and the slave device are met, bidirectional high-speed communication of data between the master device and the slave device can be realized through the SPI interface, the method is suitable for transmitting timing and/or fixed-length data, is suitable for transmitting non-timing and/or non-fixed-length data, ensures the data transmission rate, improves the communication performance of the system, and is suitable for transmitting non-timing and/non-fixed-length data. The specific implementation form of the data is not limited in this application.

In a specific embodiment, taking an internet of vehicles system as an example, when the communication system is a vehicle TBOX (telematics BOX), a specific implementation process of performing bidirectional communication by the master device and the slave device is illustrated with reference to fig. 5 and 6. For ease of illustration, fig. 5 and 6 are illustrated as examples.

As shown in fig. 5, the internet of vehicles system includes: the vehicle-mounted TBOX, a content service provider (Telematics Service Provider, TSP) server, a vehicle and terminal equipment, wherein the vehicle-mounted TBOX is in communication connection with the TSP server, such as a network adopting a fourth generation mobile communication technology (the 4th generation mobile communication technology,4G), a fifth generation mobile communication technology (the 5th generation mobile communication technology,5G) and the like, so as to realize the function of the internet of vehicles. At the same time, the on-board TBOX may also access a controller area network (controller area network, CAN network) on the vehicle to obtain data about the vehicle and to control one or more electronic control units (electronic control unit, ECU) on the vehicle. The TSP server may also be communicatively coupled to the terminal device to receive instructions related to the vehicle owner and to transmit data related to the vehicle owner. The terminal device may include, but is not limited to, a wearable device, a tablet computer, a laptop computer, a mobile phone, etc.

Based on the internet of vehicles system shown in fig. 5, with reference to fig. 6, taking a terminal device as an example of a mobile phone, a specific implementation process of realizing corresponding service by using two-way communication between a master device and a slave device in a vehicle-mounted TBOX by a vehicle owner and a vehicle is illustrated through a first scene and a second scene respectively.

Scene one: the vehicle owner initiates remote control of the vehicle, such as locking the vehicle door, through the mobile phone. An Application (APP) on a mobile phone is operated by a vehicle owner, the APP on the mobile phone is communicated with a TSP server, the TSP server issues an instruction to a vehicle-mounted TBOX, and the vehicle-mounted TBOX is received by a master device, forwarded to a slave device and sent to a specifically executed ECU by the slave device through a CAN network of a vehicle.

Scene II: the vehicle detects that the owner forgets the key, realizes triggering reminding, and reports to the owner. When the vehicle determines that the vehicle owner leaves the vehicle and does not take away the key, a corresponding event is generated on the CAN network of the vehicle, the event is collected by the slave equipment in the vehicle-mounted TBOX and then transmitted to the master equipment, the master equipment reports the event to the TSP server through the 4G network, and the TSP server informs the vehicle owner of the event, such as a short message of a mobile phone or an APP prompt mode.

In summary, in addition to the above two scenarios, a large amount of data collection, diagnosis or control functions are performed in the on-board TBOX, which causes busy communication between the master device and the slave device in the on-board TBOX. However, by adopting the SPI interface communication method between the master device and the slave device in the vehicle-mounted TBOX, the SPI interface can be utilized to realize high-speed data transmission, so that the problems are avoided, and the communication efficiency of the vehicle networking system is improved.

The communication method of the SPI interface is applied to a communication system, the communication system comprises a master device and at least one slave device, wherein the master device and any one slave device are provided with at least one channel, each channel comprises one SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode. According to the method, for any channel, the level state of the GPIO interface in the channel can be configured based on the transmitted transaction of any one of the master device and the slave device, and based on the connection relation of the GPIO interface in the channel between the master device and the slave device, the transaction corresponding to the level state of the GPIO interface in the channel between the master device and the slave device can be synchronized, so that unnecessary clock signals are avoided being wasted, clock signals are identified or communication resources such as boundaries of the clock signals are judged, communication resources are required to be provided in a proper time period, the communication resources are reasonably used, the waste of the communication resources is reduced, the communication requirements of small resource consumption between the master device and the slave device are met, data can be transmitted in two directions through the SPI interface in the channel, the method is suitable for transmitting timing and/or fixed-length data, meanwhile, the transmission rate and the reliability of the data are improved, and the performance of the system is guaranteed.

Those skilled in the art will appreciate that the speed at which the level of the GPIO interface is pulled down is faster than the speed at which the level of the GPIO interface is set high. Therefore, in this application, for any channel, in the open-drain mode of the GPIO interface, the first device may set the initial level of each GPIO interface in the channel to be high level logic in advance. Therefore, when the first device configures the level state of the GPIO interfaces in the channel, the high level logic of one or more GPIO interfaces can be pulled down to improve the response speed, so that the master device and the slave device can quickly acquire the current level state of the GPIO interfaces in the channel, the communication time is saved, and the high-speed transmission of data is facilitated.

In the application, bidirectional communication of the SPI interface can be realized between the master device and the slave device. In the following, a specific procedure for realizing bidirectional communication between a master device and a slave device in the present application will be described by way of example with reference to the first and second embodiments. For convenience of explanation, in this application, a specific embodiment of transmitting data from a master device to a slave device is referred to as a first embodiment, and a specific embodiment of transmitting data from a slave device to a master device is referred to as a second embodiment.

Example 1

In a first embodiment, when the master device has a need to send data to the slave device, for any channel, the master device may configure, based on a data transmission transaction, a level state of the GPIO interface in the channel to be a first state, where the first state is used to indicate that the master device requests to send data to the slave device. After the configuration of the first state is completed, the slave device can detect that the initial level state of the GPIO interface in the channel is switched to the first state based on the connection relation of the GPIO interface between the master device and the slave device in the channel.

In the present application, the slave device may not have the capability to receive data due to various reasons such as insufficient storage capacity, and may have the capability to receive data. According to the actual situation of the data receiving capability of the slave device, the slave device can inform the master device whether the slave device meets the receiving condition or not, namely, whether the slave device can receive data or not, based on the level state of the GPIO interface in the channel.

In one aspect, when the slave device meets the receiving condition, the slave device may configure the level state of the GPIO interface in the channel to be a second state, where the second state is used to notify the master device that the slave device meets the receiving condition. After the second state is configured, the master device may detect that the first state is switched to the second state based on a connection relationship of the GPIO interface between the master device and the slave device in the channel. Therefore, the master device can determine that the slave device meets the receiving condition, and can send data to the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and data transmission transaction is completed.

Since the level states of the GPIO interfaces in any one of the channels may be the same for the plurality of transactions, in order to distinguish the data transmission transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to be a tenth state after the data transmission transaction is completed, that is, after the data transmission is finished, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

The foregoing implementation process may be implemented by the master device and/or the slave device, which is not limited in this application.

In addition, when the first device detects that the internal logic is wrong, the level state of the GPIO interface in the channel can be configured to be a tenth state, and the level state of the GPIO interface in the channel is reset to be an initial level state, so that the problem that data transmission transaction cannot be completed normally due to the fact that the internal logic of the first device is disordered is solved, the first device is favorable for knowing that the internal logic of the first device is wrong in time, and an operator is conveniently prompted to check and replace the first device.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device can configure the level state of the GPIO interface in the channel to be a tenth state and reset the level state of the GPIO interface in the channel to be an initial level state, so as to solve the problem that the data transmission transaction cannot be smoothly performed due to the fact that the first device cannot recognize the error level state of the GPIO interface in the channel, and facilitate the first device to correct the level state of the GPIO interface in the channel, and prevent the first device from being dead.

On the other hand, when the slave device does not meet the receiving condition, the slave device may configure the level state of the GPIO interface in the channel to be a third state based on the flow control mechanism transaction, where the third state is used to notify the master device that the slave device does not meet the receiving condition. After the third state is configured, the master device may detect that the first state is switched to the third state based on the connection relationship of the GPIO interface between the master device and the slave device in the channel. Thus, the master device can determine that the slave device refuses to receive the data, ensure that the master device reliably and effectively transmits the data to the slave device, and complete the flow control mechanism transaction so as to provide the slave device with the right to refuse to receive the data.

Since the level states of the GPIO interfaces in any one of the channels that may be used by the plurality of transactions are the same, in order to distinguish the flow control mechanism transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to be a tenth state after the flow control mechanism transaction is completed, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

In addition, when the first device detects that the internal logic is wrong, the level state of the GPIO interface in the channel can be configured to be a tenth state, and the level state of the GPIO interface in the channel is reset to be an initial level state, so that the problem that the transaction of the flow control mechanism cannot be completed normally due to the disorder of the internal logic of the first device is solved, the first device can be informed of the fact that the internal logic of the first device is wrong in time, and an operator can be conveniently prompted to check and replace the first device.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device can configure the level state of the GPIO interface in the channel to be a tenth state and reset the level state of the GPIO interface in the channel to be an initial level state, so that the problem that the flow control mechanism transaction cannot be smoothly performed due to the fact that the first device cannot recognize the error level state of the GPIO interface in the channel is solved, error correction is performed on the level state of the GPIO interface in the channel by the first device, and the phenomenon that the first device is dead is prevented.

In addition, those skilled in the art will appreciate that the processing power of the master device is greater than that of the slave device. Compared with the master device, the slave device has stronger real-time performance. Thus, to facilitate knowing whether the data received by the slave from the master is accurate, a reply mechanism transaction is typically initiated by the master to the slave to inform the master of whether the data received by the slave is accurate.

In the application, the master device may configure the level state of the GPIO interface in the channel to be a fourth state based on the response mechanism transaction, where the fourth state is used to indicate that the master device inquires the slave device to notify the master device that the data received by the slave device is accurate. After the fourth state is configured, the slave device can detect that the initial level state is switched to the fourth state based on the connection relation of the GPIO interface between the master device and the slave device in the channel.

In this application, the slave device may or may not receive accurate data from the master device due to various subjective and objective factors. Based on the actual situation that whether the data received by the slave device is correct or not, the slave device can inform the master device whether the data received by the slave device is correct or not, namely, the transmission situation of the data, based on the level state of the GPIO interface in the channel.

In one aspect, when the data received from the master device by the slave device is accurate, the level state of the GPIO interface in the channel may be configured to be a fifth state based on the response mechanism transaction, where the fifth state is used to indicate that the data received from the master device by the slave device is accurate. Therefore, after the configuration of the fifth state is completed, the master device can detect that the fourth state is switched to the fifth state based on the connection relation of the GPIO interface between the master device and the slave device in the channel. Therefore, the master device can determine that the data received by the slave device from the master device is accurate, and the slave device does not need to be resent the data, so that the response mechanism transaction is completed.

Since the level states of the GPIO interfaces in any one of the channels that may be used by the multiple transactions are the same, in order to distinguish the reply mechanism transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to a tenth state after the reply mechanism transaction is completed, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

In addition, when the first device detects that the internal logic is wrong, the level state of the GPIO interface in the channel can be configured to be a tenth state, and the level state of the GPIO interface in the channel is reset to be an initial level state, so that the problem that the response mechanism transaction cannot be completed normally due to the fact that the internal logic of the first device is disordered is solved, the first device is favorable for knowing that the internal logic of the first device is wrong in time, and an operator is conveniently prompted to check and replace the first device.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device can configure the level state of the GPIO interface in the channel to be a tenth state and reset the level state of the GPIO interface in the channel to be an initial level state, so as to solve the problem that the response mechanism transaction cannot be smoothly performed due to the fact that the first device cannot recognize the error level state of the GPIO interface in the channel, and facilitate the first device to correct the level state of the GPIO interface in the channel, and prevent the first device from being dead.

On the other hand, when the data received from the master device is inaccurate, the slave device does not configure the level state of the GPIO interface in the channel to be the fifth state based on the response mechanism transaction. Therefore, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the master device cannot detect that the fourth state is not switched to the fifth state, that is, the fourth state is not detected to be switched to the fifth state, or the fourth state is detected to be switched to a state other than the fifth state. After the first preset duration, when the fourth state is detected not to be switched to the fifth state, the master device can resend data to the slave device through the SPI interface in the channel based on the data resending transaction, so that accuracy of the data received by the slave device from the master device is ensured, and the data resending transaction is completed.

The first preset duration may be set according to practical experience, which is not limited in this application.

Since the level states of the GPIO interfaces in any one of the channels that may be used by the plurality of transactions are the same, in order to distinguish the data retransmission transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to be a tenth state after the data retransmission transaction is completed, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

In addition, when the first device detects that the internal logic is wrong, the level state of the GPIO interface in the channel can be configured to be a tenth state, and the level state of the GPIO interface in the channel is reset to be an initial level state, so that the problem that the data retransmission transaction cannot be completed normally due to the disorder of the internal logic of the first device is solved, the first device is favorable for knowing that the internal logic of the first device is wrong in time, and an operator is conveniently prompted to check and replace the first device.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device can configure the level state of the GPIO interface in the channel to be a tenth state and reset the level state of the GPIO interface in the channel to be an initial level state, so that the problem that the data retransmission transaction cannot be smoothly performed due to the fact that the first device cannot recognize the error level state of the GPIO interface in the channel is solved, the first device can timely acquire that the first device has an error in internal logic, and an operator can be conveniently prompted to check the first device.

In a specific embodiment, fig. 7 shows a state schematic diagram of three GPIO interfaces, and in conjunction with fig. 7, a specific implementation procedure of the master device and the slave device to complete the above-mentioned transmitted transaction in the first embodiment is illustrated. For convenience of explanation, in fig. 7, an example is shown in which one channel includes three GPIO interfaces, namely, a first GPIO interface, a second GPIO interface, and a third GPIO interface, and initial level states of the three GPIO interfaces are "111".

1. The level states of the three GPIO interfaces change as follows: "111-011-010-000-111"

Step 1, when the master device has a need to send data to the slave device, for any channel, the master device may pull low the high level logic of the first GPIO interface based on the data transmission transaction, and configure the first state to be "011", as shown in fig. 8.

Step 2, when the slave device detects that the initial level state "111" is switched to the first state "011", and the slave device meets the receiving condition, the slave device pulls down the high level logic of the third GPIO interface, and configures the second state to be "010", as shown in fig. 8.

And 3, when the master device detects that the first state '011' is switched to the second state '010', the master device sends data to the slave device through the MOSI line in the SPI interface in the channel, as shown in fig. 8, and the corresponding level of the MOSI line is high level logic at the moment, so that the master device sends a clock signal to the slave device, and the master device completes the process of transmitting the data to the slave device based on the clock signal.

And 4, after the data transmission is finished, the master device or the slave device pulls down the high level logic of the second GPIO interface to configure the tenth state as '000'. When the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 8.

2. The level states of the three GPIO interfaces are changed as follows: "111-011-001-000-111"

Step 1, when the master device has a need to send data to the slave device, for any channel, the master device may pull low the high level logic of the first GPIO interface based on the data transmission transaction, and configure the first state to be "011", as shown in fig. 9.

Step 2, when the slave device detects that the initial level state "111" is switched to the first state "011", and the slave device does not meet the receiving condition, the slave device pulls down the high level logic of the second GPIO interface, and configures the third state to "001", as shown in fig. 9.

Step 3, when the master device detects that the first state "011" is switched to the third state "001", it may determine that the slave device refuses to receive data, as shown in fig. 9, where the level corresponding to the MOSI line is a low level, so that the master device will not send a clock signal to the slave device.

And 4, the master device or the slave device pulls down the high-level logic of the third GPIO interface to configure the tenth state to be '000'. When the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 9.

3. Response mechanism transaction, the level state of the three GPIO interfaces changes as follows: "111-101-000-111"

Step 1, after the data transmission transaction is completed, the master device may pull the high level logic of the second GPIO interface low based on the response mechanism transaction, and configure the fourth state to be "101", as shown in fig. 10.

In step 21, when the slave device detects that the initial level state "111" is switched to the fourth state "101" and the data received from the master device is accurate, the high level logic of the first GPIO interface is pulled down, the high level logic of the third GPIO interface is pulled down, and the fifth state is configured to be "000", as shown in fig. 10.

Step 31, when the master device detects that the fourth state is switched to the fifth state of "000", the master device determines that the data received from the master device by the slave device is accurate, as shown in fig. 10.

Step 4, since the fifth state is the tenth state "000", when the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 10.

Step 32, when the master device does not detect that the fourth state is switched to the fifth state of "001" after the first preset time period, determining that the data received from the master device by the slave device is inaccurate, and continuing to execute the step 1 to realize the data repetition transaction.

Example two

In the second embodiment, those skilled in the art will understand that the processing capability of the master device is stronger than that of the slave device. Compared with the master device, the slave device has stronger real-time performance. Thus, to facilitate knowing whether a slave device has data to send to the master device, a polling mechanism transaction is typically initiated by the master device to the slave device in order to effect the slave device to send data to the master device.

In the application, when the master device inquires whether the slave device has a need to send data to the slave device, for any channel, the master device can configure the level state of the GPIO interface in the channel to be a sixth state based on the polling mechanism transaction, where the sixth state is used to indicate that the master device inquires whether the slave device has data to send to the master device. After the sixth state is configured, the slave device can detect that the initial level state of the GPIO interface in the channel is switched to the sixth state based on the connection relationship of the GPIO interface between the master device and the slave device in the channel.

In this application, the slave device may not currently have a data requirement to send to the master device, or may have a data requirement to send to the master device. According to the actual situation of the data transmission requirement of the slave device, the slave device can inform the master device whether the slave device currently has data to transmit to the master device or not based on the level state of the GPIO interface in the channel.

In one aspect, when the slave device has data to send to the master device, the slave device may configure the level state of the GPIO interface in the channel to be a seventh state, where the seventh state is used to notify the master device that the slave device has data to send. After the configuration of the seventh state is completed, the master device may detect that the sixth state is switched to the seventh state based on the connection relationship of the GPIO interface between the master device and the slave device in the channel. Therefore, the master device can determine that the slave device has data to send, and can receive the data from the slave device at high speed through the SPI interface in the channel, so that unnecessary communication resources are saved, and the polling mechanism transaction is completed.

Since the level states of the GPIO interfaces in any channel that may be used by the plurality of transactions are the same, in order to distinguish the polling mechanism transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to be a tenth state after the polling mechanism transaction is completed, i.e. after the data transmission is completed, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

In addition, when the first device detects that the internal logic is wrong, the level state of the GPIO interface in the channel can be configured to be a tenth state, and the level state of the GPIO interface in the channel is reset to be an initial level state, so that the problem that the polling mechanism transaction cannot be completed normally due to the fact that the internal logic of the first device is disordered is solved, the first device is favorable for knowing that the internal logic of the first device is wrong in time, and an operator is conveniently prompted to check and replace the first device.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device may configure the level state of the GPIO interface in the channel to be a tenth state, and reset the level state of the GPIO interface in the channel to be an initial level state, so as to solve the problem that the polling mechanism transaction cannot be smoothly performed due to the fact that the first device cannot identify the error level state of the GPIO interface in the channel, which is favorable for the first device to correct the level state of the GPIO interface in the channel, and prevent the first device from crashing.

On the other hand, when the slave device has no data to send to the master device, the slave device may configure the level state of the GPIO interface in the channel to be an eighth state, where the eighth state is used to notify the master device that the slave device has no data to send. After the eighth state configuration is completed, the master device may detect that the sixth state is switched to the eighth state based on the connection relationship of the GPIO interface between the master device and the slave device in the channel. Therefore, the master device can determine that the slave device does not need to send data to the master device, unnecessary communication resources are saved, and the polling mechanism transaction is completed.

Since the level states of the GPIO interfaces in any channel that may be used by the multiple transactions are the same, in order to distinguish the polling mechanism transaction from other transmitted transactions, the first device may configure the level state of the GPIO interface in the channel to be a tenth state after the polling mechanism transaction is completed, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device. After the tenth state is configured, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the first device can configure the level state of the GPIO interface in the channel to be an initial level state, so that the level state of the GPIO interface in the channel is reset, and the first device can conveniently realize the next transmission transaction.

In addition, in the present application, the data received from the master device may be accurate or inaccurate due to various subjective and objective factors. Based on the actual condition that whether the slave device receives the data accurately or not, the master device can inform the slave device whether the data received by the master device is accurate or not, namely the transmission condition of the data, based on the level state of the GPIO interface in the channel. To facilitate knowing whether the data received by the master from the slave is accurate, a reply mechanism transaction is initiated by the master to the slave to inform the slave whether the data received by the master is accurate.

In one aspect, when the data received by the master device is accurate, the master device may configure, based on the response mechanism transaction, the level state of the GPIO interface in the channel to be a ninth state, where the ninth state is used to indicate that the data received by the master device from the slave device is accurate. After the ninth state is configured, the slave device may detect that the initial level state is switched to the ninth state based on the connection relationship of the GPIO interface between the master device and the slave device in the channel. Therefore, the slave device can determine that the data received by the master device from the slave device is accurate, and the data does not need to be sent to the master device again, so that the response mechanism transaction is completed.

On the other hand, when the data received from the master device is inaccurate, the master device does not configure the level state of the GPIO interface in the channel to be the ninth state based on the response mechanism transaction. Therefore, based on the connection relation of the GPIO interface between the master device and the slave device in the channel, the slave device cannot detect that the initial level state is not switched to the ninth state, that is, detects that the initial level state is switched to the ninth state, or detects that the initial level state is switched to a state other than the ninth state. After the second preset duration, when the initial level state is detected not to be switched to the ninth state, the slave device can resend data to the master device through the SPI interface in the channel based on the data resending transaction, so that the accuracy of the data received by the master device from the slave device is ensured, and the data resending transaction is completed.

The second preset duration may be set according to practical experience, which is not limited in this application.

In addition, when the first device detects that the GPIO interface in the channel has an error level state in the data transmission transaction, the first device may configure the level state of the GPIO interface in the channel to be a tenth state, and reset the level state of the GPIO interface in the channel to be an initial level state, so as to solve the problem that the data retransmission transaction cannot be smoothly performed due to the fact that the first device cannot identify the error level state of the GPIO interface in the channel, which is favorable for the first device to correct the level state of the GPIO interface in the channel, and prevent the first device from a dead halt phenomenon.

In a specific embodiment, with continued reference to fig. 7, a specific implementation procedure in which the master device and the slave device complete the above-mentioned transmitted transaction in the second embodiment is illustrated.

1. The polling mechanism transaction 1, the change of the level states of the three GPIO interfaces is: "111-101-100-000-111"

Step 1, when the master device inquires whether the slave device has a need to send data to the slave device, the master device may pull low the logic of the high level of the second GPIO interface for any channel based on a data transmission transaction, and configure the sixth state to be "101", as shown in fig. 11.

Step 2, when the slave device detects that the initial level state "111" is switched to the sixth state "101" and the slave device has data to send, the slave device pulls down the high level logic of the third GPIO interface, and configures the seventh state to be "100", as shown in fig. 11.

Step 3, when the master device detects that the sixth state '101' is switched to the seventh state '100', the master device can receive data from the slave device through the MISO line in the SPI interface in the channel, as shown in fig. 11, and the level corresponding to the MISO line is high level logic, so that the master device sends a clock signal to the slave device, and the slave device completes a process of transmitting data to the master device based on the clock signal.

And 4, after the data transmission is finished, the master device or the slave device pulls down the high level logic of the first GPIO interface to configure the tenth state as '000'. When the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 11.

2. The polling mechanism transaction 2, the change of the level states of the three GPIO interfaces is: "111-101-001-000-111"

Step 1, when the master device inquires whether the slave device has a need to send data to the slave device, the master device may pull low the logic of the high level of the second GPIO interface for any channel based on a data transmission transaction, and configure the sixth state to be "101", as shown in fig. 12.

Step 2, when the slave device detects that the initial level state "111" is switched to the sixth state "101" and the slave device has no data to send, the slave device pulls down the high level logic of the first GPIO interface, and configures the eighth state to "001", as shown in fig. 12.

Step 3, when the master device detects that the sixth state "101" is switched to the eighth state "001", it may be determined that the slave device has no data to send to the master device, as shown in fig. 12, where the level corresponding to the MISO line is a low level, so that the master device will not send a clock signal to the slave device.

And 4, the master device or the slave device pulls down the high-level logic of the third GPIO interface to configure the tenth state to be '000'. When the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 12.

3. Response mechanism transaction, the level state of the three GPIO interfaces changes as follows: "111-110-000-111"

Step 1, after the polling mechanism transaction 1 is completed, the master device may pull low the high level logic of the third GPIO interface based on the response mechanism transaction, and configure the ninth state to be "110", as shown in fig. 13.

Step 21, when the slave device detects that the initial level state '111' is switched to the ninth state '110', it is determined that the data received by the master device from the slave device is accurate, as shown in fig. 13.

And 3, the slave device pulls down the high-level logic of the first GPIO interface, pulls down the high-level logic of the second GPIO interface, and configures the tenth state as '000'. When the master device and the slave device detect the tenth state "000", the low level logic of the first GPIO interface is set high, the low level logic of the second GPIO interface is set high, and the low level logic of the third GPIO interface is set high, so that the level states of the GPIO interfaces of the master device and the slave device in the channel are reset to the initial level state "111", as shown in fig. 13.

Step 22, when the primary device passes through the second preset time period and the initial level state 111 is not detected to be switched to the ninth state 110, determining that the data received by the primary device from the secondary device is inaccurate, and continuing to execute the step 1 to realize the data repetition transaction.

Illustratively, the present application also provides a communication system. As shown in fig. 2, the communication system of the present application may include: a master device and at least one slave device. The master device and any slave device are provided with at least one channel, each channel comprises a serial peripheral interface SPI interface and at least three general purpose input/output (GPIO) interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode. In each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device.

For any channel, any one of the master device and the slave device configures the level state of the GPIO interface in the channel based on the transmitted transaction, and can bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

In some embodiments, the master device or slave device configures the level state of the GPIO interfaces in the channel by pulling low the high level of at least one GPIO interface based on the transmitted transaction when each of the initial level states of the GPIO interfaces in the channel is high.

In some embodiments, the master device configures a level state of the GPIO interface in the channel to be a first state based on the data transfer transaction, the first state being indicative of the master device requesting to send data to the slave device; when the slave device switches to a first state in the initial level state of the GPIO interface in the channel, if the slave device meets the receiving condition, configuring the level state of the GPIO interface in the channel as a second state, wherein the second state is used for informing the master device that the slave device meets the receiving condition; when the master device switches from the first state to the second state, data is sent to the slave device through the SPI interface in the channel.

In some embodiments, when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device does not meet the receiving condition, configuring the level state of the GPIO interface in the channel to be a third state, where the third state is used to notify the master device that the slave device does not meet the receiving condition; when the master device switches from the first state to the third state, the slave device is determined to refuse to receive data.

In some embodiments, the master device configures a level state of the GPIO interface in the channel to be a fourth state based on the reply mechanism transaction, the fourth state being used to indicate that the master device inquires the slave device that the data received by the slave device is accurate; when the slave device is switched to a fourth state in the initial level state, based on the response mechanism transaction, configuring the level state of the GPIO interface in the channel to be a fifth state, wherein the fifth state is used for indicating that the data received by the slave device from the master device is accurate; when the master device switches from the fourth state to the fifth state, the data received from the master device by the slave device is determined to be accurate.

In some embodiments, the master device retransmits data to the slave device over the SPI interface in the channel based on the data retransmission transaction when the fourth state is not switched to the fifth state for a first predetermined period of time.

In some embodiments, the master device configures a level state of the GPIO interface in the channel to be a sixth state based on the polling mechanism transaction, the sixth state being used to indicate that the master device inquires whether the slave device has data to send to the master device; when the slave device switches from the initial level state of the GPIO interface in the channel to the sixth state, if the slave device has data to be sent to the master device, configuring the level state of the GPIO interface in the channel to be a seventh state, wherein the seventh state is used for informing the master device that the slave device has data to be sent; the master device receives data from the slave device over the SPI interface in the channel when the sixth state is switched to the seventh state.

In some embodiments, when the slave device switches from the initial level state of the GPIO interface in the channel to the sixth state, if the slave device does not have data to send to the master device, configuring the level state of the GPIO interface in the channel to be the eighth state, where the eighth state is used to notify the master device that the slave device does not have data to send; when the master device switches from the sixth state to the eighth state, it is determined that the slave device has no data to transmit.

In some embodiments, the master device configures a level state of the GPIO interface in the channel to be a ninth state based on the reply mechanism transaction, the ninth state being used to indicate that the data received by the master device from the slave device is accurate; and when the slave device is switched to the ninth state in the initial level state of the GPIO interface in the channel, determining that the data received by the master device from the slave device is accurate.

In some embodiments, the slave device retransmits the data to the master device through the SPI interface in the channel based on the data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state for a second predetermined period of time.

In some embodiments, when the master device or the slave device completes the transmitted transaction or detects that an internal logic is wrong or detects that the GPIO interface in the channel is wrong in the transmitted transaction, configuring the level state of the GPIO interface in the channel to be a tenth state, where the tenth state is used for indicating the level state of the GPIO interface in the reset channel of the master device and/or the slave device; the master device or the slave device configures the level state of the GPIO interface in the channel to be an initial level state based on the tenth state.

The specific structure of the communication system provided in the present application may be described in the embodiments shown in fig. 2 to 3, and the communication process between the master device and the slave device may be described in the embodiments shown in fig. 4 to 13, which are not repeated here.

The application also provides a communication device with the SPI interface. Fig. 14 is a schematic structural diagram of a communication apparatus of an SPI interface provided in an embodiment of the present application, and as shown in fig. 14, a communication apparatus 100 of the SPI interface generally refers to a first device, which is any one of a master device and a slave device in a communication system, and the communication system may include the master device and at least one slave device, for implementing an operation corresponding to the first device in an embodiment of a communication method of any one of the SPI interfaces. The master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device.

As shown in fig. 14, the communication device 100 of the SPI interface of the present application may include: a configuration module 101 and a transmission module 102.

A configuration module 101, configured to configure, for any channel, a level state of a GPIO interface in the channel based on a transmitted transaction;

the transmission module 102 is configured to enable the first device to bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

In some embodiments, when each GPIO interface in the initial level state of the GPIO interfaces in the channel is high, the configuration module 101 is configured to configure the level state of the GPIO interfaces in the channel by pulling low the high level of at least one GPIO interface based on the transmitted transaction.

In some embodiments, the configuration module 101 is configured to configure, when the communication apparatus 100 of the SPI interface is a master device, a level state of the GPIO interface in the channel to be a first state based on a data transmission transaction, where the first state is used to indicate that the master device requests to send data to the slave device; when the communication device 100 of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the first state, if the slave device meets the receiving condition, configuring the level state of the GPIO interface in the channel to be a second state, where the second state is used for notifying the master device that the slave device meets the receiving condition;

And the transmission module 102 is configured to send data to the slave device through the SPI interface in the channel when the communication apparatus 100 with the SPI interface is the master device and the first state is switched to the second state.

In some embodiments, the configuration module 101 is further configured to, when the communication apparatus 100 of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the first state, configure, based on the flow control mechanism transaction, the level state of the GPIO interface in the channel to be a third state, where the third state is used to notify the master device that the slave device does not meet the receiving condition, if the slave device does not meet the receiving condition; when the communication apparatus 100 of the SPI interface is a master device and the first state is switched to the third state, it is determined that the slave device refuses to receive data.

In some embodiments, the configuration module 101 is further configured to, when the communication apparatus 100 of the SPI interface is a master device, configure a level state of the GPIO interface in the channel to be a fourth state based on a response mechanism transaction, where the fourth state is used to indicate that the master device inquires about the slave device that the data received by the slave device is accurate; when the communication device 100 of the SPI interface is a slave device and the initial level state is switched to the fourth state, configuring the level state of the GPIO interface in the channel to be a fifth state based on the response mechanism transaction, where the fifth state is used to indicate that the data received from the master device by the slave device is accurate; when the communication apparatus 100 of the SPI interface is a master device and the fourth state is switched to the fifth state, it is determined that the data received from the master device by the slave device is accurate.

In some embodiments, the transmission module 102 is further configured to, when the communication apparatus 100 of the SPI interface is a master device, retransmit data to the slave device through the SPI interface in the channel based on the data retransmission transaction after a first preset period of time passes when the fourth state is not switched to the fifth state.

In some embodiments, the configuration module 101 is configured to, when the communication apparatus 100 of the SPI interface is a master device, configure, based on a polling mechanism transaction, a level state of the GPIO interface in the channel to be a sixth state, where the sixth state is used to indicate that the master device inquires whether there is data from the slave device that needs to be sent to the master device; when the communication device 100 of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the sixth state, if the slave device has data to send to the master device, configuring the level state of the GPIO interface in the channel to be the seventh state, where the seventh state is used to notify the master device that the slave device has data to send;

the transmission module 101 is configured to receive data from the slave device through the SPI interface in the channel when the communication apparatus 100 of the SPI interface is the master device and the sixth state is switched to the seventh state.

In some embodiments, the configuration module 101 is further configured to, when the communication apparatus 100 of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the sixth state, configure the level state of the GPIO interface in the channel to be the eighth state if the slave device has no data to send to the master device, where the eighth state is used to notify the master device that the slave device has no data to send; when the communication apparatus 100 of the SPI interface is a master device and the sixth state is switched to the eighth state, it is determined that there is no data to be transmitted from the slave device.

In some embodiments, the configuration module 101 is further configured to, when the communication apparatus 100 of the SPI interface is a master device, configure, based on the response mechanism transaction, a level state of the GPIO interface in the channel to be a ninth state, where the ninth state is used to indicate that data received by the master device from the slave device is accurate; when the communication apparatus 100 of the SPI interface is a slave device and the initial level state of the GPIO interface in the channel is switched to the ninth state, it is determined that the data received by the master device from the slave device is accurate.

In some embodiments, the transmission module 101 is further configured to, when the communication apparatus 100 of the SPI interface is a slave device, retransmit data to the master device through the SPI interface in the channel based on the data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state after a second preset period of time.

In some embodiments, the configuration module 101 is further configured to configure the level state of the GPIO interface in the channel to be a tenth state when the transmitted transaction is completed or an internal logic error is detected or an error level state of the GPIO interface in the channel is detected in the transmitted transaction, where the tenth state is used to indicate the level state of the GPIO interface in the reset channel of the master device and/or the slave device; based on the tenth state, the level state of the GPIO interface in the configuration channel is an initial level state.

The communication device of the SPI interface in the embodiment of the present application may be used to execute the technical scheme in the communication method embodiment of the SPI interface, and its implementation principle and technical effects are similar, and will not be described herein again.

An exemplary electronic device is further provided in the present application, fig. 15 is a schematic hardware structure of a communication device provided in an embodiment of the present application, and as shown in fig. 15, the communication device 200 is configured to implement operations corresponding to a first device in any of the foregoing method embodiments through software and/or hardware, where the first device is any one of a master device and a slave device in a communication system, and the communication system may include the master device and at least one slave device. The master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device.

As shown in fig. 15, the communication device 200 of the present application may include: a memory 201 and a processor 202. The memory 201 and the processor 202 may be connected by a bus 203.

A memory 201 for storing program codes;

the processor 202 invokes program code that, when executed, is operable to perform the communication method of the SPI interface in any of the embodiments described above. Reference may be made in particular to the relevant description of the embodiments of the method described above.

Optionally, the present application further comprises a communication interface 204, which communication interface 204 may be connected to the processor 202 via the bus 203. Processor 202 may control communication interface 203 to implement the above-described functions of receiving and transmitting of communication device 200.

The communication device of the present application may be used to execute the technical scheme in the communication method embodiment of the SPI interface, and its implementation principle and technical effects are similar, and will not be described herein.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, e.g., the division of modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purposes of the embodiments of the present application.

In addition, each functional module in each embodiment of the present application may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The units formed by the modules can be realized in a form of hardware or a form of hardware and software functional units.

The integrated modules, which are implemented in the form of software functional modules, may be stored in a computer readable storage medium. The software functional module is stored in a storage medium, and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (english: processor) to perform some steps of the methods of the embodiments of the present application.

It is understood that the processor may be a central processing unit (central processing unit, CPU), but may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile memory NVM, such as at least one magnetic disk memory, and may also be a U-disk, a removable hard disk, a read-only memory, a magnetic disk or optical disk, etc.

The bus may be an industry standard architecture (industry standard architecture, ISA) bus, an external device interconnect (peripheral component, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc. For ease of illustration, the buses in the drawings of the present application are not limited to only one bus or one type of bus.

The application also provides a readable storage medium, wherein the readable storage medium stores execution instructions, and when at least one processor of the electronic device executes the execution instructions, the electronic device executes the communication method of the SPI interface in the method embodiment.

The application also provides a chip, the chip is connected with the memory, or the memory is integrated on the chip, and when a software program stored in the memory is executed, the communication method of the SPI interface in the embodiment of the method is realized.

The present application also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the electronic device may read the execution instructions from the readable storage medium, the execution instructions being executed by the at least one processor to cause the electronic device to implement the communication method of the SPI interface in the method embodiment described above.

Those of ordinary skill in the art will appreciate that: in the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.) means from one website, computer, server, or data center. Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc., that contain an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

Claims

1. A communication system, comprising: a master device and at least one slave device;

2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

when each GPIO interface in the initial level state of the GPIO interface in the channel is at a high level, the master device or the slave device configures the level state of the GPIO interface in the channel by pulling down the high level of at least one GPIO interface based on the transmitted transaction.

3. The system according to claim 1 or 2, wherein,

the master device configures the level state of the GPIO interface in the channel to be a first state based on a data transmission transaction, wherein the first state is used for indicating that the master device requests to send data to the slave device;

when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device meets a receiving condition, configuring the level state of the GPIO interface in the channel as a second state, wherein the second state is used for notifying the master device that the slave device meets the receiving condition;

and when the first state is switched to the second state, the master device sends data to the slave device through the SPI interface in the channel.

4. The system of claim 3, wherein the system further comprises a controller configured to control the controller,

when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device does not meet the receiving condition, configuring the level state of the GPIO interface in the channel to be a third state, where the third state is used for notifying the master device that the slave device does not meet the receiving condition;

And when the first state is switched to the third state, the master device determines that the slave device refuses to receive data.

5. The system of claim 3, wherein the system further comprises a controller configured to control the controller,

the master device configures the level state of the GPIO interface in the channel to be a fourth state based on a response mechanism transaction, wherein the fourth state is used for indicating that the master device inquires the slave device to inform the master device that the received data of the slave device are accurate;

when the slave device switches from the initial level state to the fourth state, configuring the level state of the GPIO interface in the channel to be a fifth state based on a response mechanism transaction, wherein the fifth state is used for indicating that the data received by the slave device from the master device is accurate;

and when the fourth state is switched to the fifth state, the master device determines that the data received by the slave device from the master device is accurate.

6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,

and when the fourth state is not switched to the fifth state after the first preset time period passes, the master equipment resends data to the slave equipment through the SPI interface in the channel based on the data resending transaction.

7. The system according to claim 1 or 2, wherein,

the master device configures the level state of the GPIO interface in the channel to be a sixth state based on a polling mechanism transaction, wherein the sixth state is used for indicating that the master device inquires whether the slave device has data to be sent to the master device;

when the initial level state of the GPIO interface in the channel of the slave device is switched to the sixth state, if the slave device has data to be sent to the master device, configuring the level state of the GPIO interface in the channel to be a seventh state, wherein the seventh state is used for informing the master device that the slave device has data to be sent;

and when the sixth state is switched to the seventh state, the master device receives data from the slave device through the SPI interface in the channel.

8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,

when the slave device switches to the sixth state in the initial level state of the GPIO interface in the channel, if the slave device does not have data to send to the master device, configuring the level state of the GPIO interface in the channel to be an eighth state, where the eighth state is used for notifying the master device that the slave device does not have data to send;

And when the master device is switched to the eighth state from the sixth state, the slave device is determined that no data needs to be sent.

9. The system of claim 7, wherein the system further comprises a controller configured to control the controller,

the master device configures the level state of the GPIO interface in the channel to be a ninth state based on the response mechanism transaction, wherein the ninth state is used for indicating that the data received by the master device from the slave device is accurate;

and when the initial level state of the GPIO interface in the channel is switched to the ninth state, the slave device determines that the data received by the master device from the slave device is accurate.

10. The system of claim 9, wherein the system further comprises a controller configured to control the controller,

and the slave device retransmits data to the master device through the SPI interface in the channel based on a data retransmission transaction when the initial level state of the GPIO interface in the channel is not switched to the ninth state after the second preset time length.

11. The system of any one of claims 2-10, wherein,

when the master device or the slave device completes a transmitted transaction or detects that an internal logic is wrong or detects that a GPIO interface in the channel is wrong in the transmitted transaction, configuring the level state of the GPIO interface in the channel to be a tenth state, wherein the tenth state is used for indicating the master device and/or the slave device to reset the level state of the GPIO interface in the channel;

And the master device or the slave device configures the level state of the GPIO interface in the channel to be the initial level state based on the tenth state.

12. A communication method of an SPI interface, applied to a communication system, the communication system comprising: a master device and at least one slave device; the master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device;

for any channel, when the first device is any one device of the master device and the slave device, the method includes:

the first device configures the level state of the GPIO interface in the channel based on the transmitted transaction;

the first device can bidirectionally transmit data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

13. The method of claim 12, wherein the first device configuring the level state of the GPIO interfaces in the channel based on the transmitted transaction when each GPIO interface is high in the initial level state of the GPIO interfaces in the channel comprises:

The first device configures a level state of the GPIO interface in the channel by pulling low a high level of at least one GPIO interface based on the transmitted transaction.

14. The method according to claim 12 or 13, wherein,

the first device configures a level state of a GPIO interface in the channel based on the transmitted transaction, including:

the first device may bi-directionally transmit data through the SPI interface in the channel based on a level state of the GPIO interface in the channel, including:

15. The method of claim 14, wherein the method further comprises:

when the slave device switches to the first state in the initial level state of the GPIO interface in the channel, if the slave device does not meet the receiving condition, configuring the level state of the GPIO interface in the channel to be a third state based on a flow control mechanism transaction, wherein the third state is used for notifying the master device that the slave device does not meet the receiving condition;

16. The method of claim 14, wherein the method further comprises:

17. The method of claim 16, wherein the method further comprises:

18. The method according to claim 12 or 13, wherein,

19. The method of claim 18, wherein the method further comprises:

20. The method of claim 18, wherein the method further comprises:

21. The method of claim 20, wherein the method further comprises:

22. The method according to any one of claims 13-21, further comprising:

when the first device completes a transmitted transaction or detects that an internal logic is wrong or detects that a level state of a GPIO interface in the channel is wrong in the transmitted transaction, configuring the level state of the GPIO interface in the channel to be a tenth state, wherein the tenth state is used for indicating the master device and/or the slave device to reset the level state of the GPIO interface in the channel;

the first device configures a level state of the GPIO interface in the channel to be the initial level state based on the tenth state.

23. A communication device of an SPI interface, for use with a first apparatus in a communication system, the communication system comprising: a master device and at least one slave device; the master device and any slave device are provided with at least one channel, each channel comprises an SPI interface and at least three GPIO interfaces associated with the SPI interface, and each GPIO interface is set to be in an open-drain mode; in each channel, the SPI interface of the master device is electrically connected with the SPI interface of any one slave device, and the GPIO interface of the master device is electrically connected with the GPIO interface of the slave device; the first device is any one of the master device and the slave device;

the device comprises:

and the transmission module is used for bidirectionally transmitting data through the SPI interface in the channel based on the level state of the GPIO interface in the channel.

24. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a method of communicating an SPI interface as claimed in any of claims 12 to 22.

25. A communication device, comprising:

a processor; and

a memory for storing executable instructions of the processor;

wherein the processor is configured to perform a communication method of an SPI interface of any of claims 12-22 via execution of the executable instructions.