CN113220602B - Data writing method of flash memory and flash memory - Google Patents
Data writing method of flash memory and flash memory Download PDFInfo
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- CN113220602B CN113220602B CN202110474501.3A CN202110474501A CN113220602B CN 113220602 B CN113220602 B CN 113220602B CN 202110474501 A CN202110474501 A CN 202110474501A CN 113220602 B CN113220602 B CN 113220602B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
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- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
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Abstract
The invention discloses a data writing method of a flash memory and the flash memory, wherein the flash memory comprises the following steps: a buffer register for buffering page data of a single page size; the page type to which the page data belongs is one of: lower page LP, middle page MP, upper page UP; one physical page includes: one LP, one MP and one UP; a data register, comprising: a sub data register storing page data of different page types; the flash memory array is used for storing page data written by the controller; the controller is respectively connected with the cache register and the data register, and is used for allowing the cache register to insert page data of the (n+1) th physical page and allowing page data of the (n+1) th physical page currently cached in the cache register to be moved from the cache register to a sub-data register which is idle corresponding to the page type of the page data of the (n+1) th physical page currently cached in the cache register in the process of writing the N physical page into the flash memory array by the data register; wherein N is a natural number.
Description
The present application is a divisional application of chinese patent application with application date 2018, 10-09, application number 201811173662.3, and the name of "a data writing method for flash memory and flash memory".
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a data writing method of a flash memory and a flash memory.
Background
In the NAND flash memory, there are a buffer register (Cache page buffer) and a Data register (Data page buffer), and Data writing is quickly stored in the buffer register and then moved to the Data register, and in the related art, in a one-time programming process of writing Data into a physical array of the flash memory, only one-time movement of page Data from the buffer register to the Data register can be realized, so that when the number of Data pages written into the physical array is more than one, it is necessary to wait for the movement of page Data from the buffer register to the Data register after the programming is completed, so that the efficiency of writing Data into the flash memory array is low and the programming has no continuity.
Disclosure of Invention
Therefore, the embodiment of the invention provides a data writing method of a flash memory and the flash memory, which can realize the movement of moving different types of page data from a cache register to a data register in a one-time programming process, thereby ensuring the programming continuity.
The technical scheme of the embodiment of the invention is realized as follows:
The embodiment of the invention provides a flash memory, which comprises the following components:
a buffer register for buffering page data of a single page size; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP; one physical page includes: one of said LP, one of said MPs, and one of said UP;
a data register, comprising: a sub data register storing page data of different page types;
a flash memory array for storing the page data written by the controller;
the controller is respectively connected with the cache register and the data register, and is used for allowing the cache register to insert page data of the (n+1) th physical page and allowing page data of the (n+1) th physical page currently cached in the cache register to be moved from the cache register to a sub-data register which is free corresponding to the page type of the page data of the (n+1) th physical page currently cached in the cache register in the programming process of writing the Nth physical page into the flash memory array by the data register; wherein N is a natural number.
In the above scheme, the controller is further configured to control writing page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register.
In the above scheme, the controller is further configured to, after storing page data with types of LP, MP and UP in the data register, perform code conversion on the page data stored in the data register to obtain corresponding state codes of different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
In the above scheme, before performing transcoding on the page data stored in the data register, the controller is further configured to control the page data in the buffer register to move to the data register, so that a page type of the page data stored in the data register includes the LP, the MP, and the UP.
In the above scheme, the controller is further configured to control the buffer register to release the buffer register after the page data in the buffer register is moved to the data register, so that the buffer register continues to store the next page data that is written according to the specific type ordering.
In the above scheme, the controller is further configured to sequentially and circularly check the state codes of the different state bits from high-order bits to low-order bits after performing code conversion on the page data stored in the data register, and determine whether to move the page data in the buffer register to the data register according to a check result.
In the above scheme, different state identification bits correspond to different sub-data registers;
and the controller is also used for controlling the page data in the buffer register to move to the sub-data register corresponding to the state identification bit passing the verification when the state code corresponding to the state identification bit in the different state bits passes the verification.
In the above scheme, the controller is further configured to control to perform a next sequential loop check of the status code when the status code corresponding to the status identification bit passes the check, and the page data stored in the buffer register is empty, and control the page data stored in the buffer register to move to a sub-data register corresponding to the status identification bit, where the check passes the data, when determining that the page data is stored in the buffer register.
In the above scheme, the different status bits further include a status flag bit for indicating that writing of page data is completed;
and the controller is also used for controlling the process of writing the physical page into the flash memory array to be ended when the status identification bit for indicating the completion of writing the page data passes the verification.
In the above scheme, the buffer register is further configured to buffer reference page data of a single page size that is written according to a specific type ordering, where the reference page data is used to indicate execution of first programming;
The data register is further used for caching the reference page data of different page types which are moved from the cache register;
the controller is further configured to, when the first programming starts, move the reference page data in the cache register to the data register, so that page data with types of LP, MP and UP are stored in the data register, and write the page data stored in the data register into the flash memory array.
The embodiment of the invention also provides a data writing method of the flash memory, which comprises the following steps:
writing page data of an Nth physical page stored in a data register into the flash memory array; wherein N is a natural number; the data register comprises a sub-data register for storing page data of different page types; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP; one physical page includes: one of said LP, one of said MPs, and one of said UP;
in the process that the data register writes the Nth physical page into the flash memory array, a buffer register is allowed to insert page data of the (n+1) th physical page, and page data of the (n+1) th physical page currently buffered in the buffer register is allowed to be moved from the buffer register to a sub-data register which is free corresponding to the page type of the page data of the (n+1) th physical page currently buffered in the buffer register.
In the above scheme, after the page data of the LP, the MP and the UP are stored in the data register, the page data stored in the data register is written into the flash memory array.
In the above scheme, after the page data with the types of LP, MP and UP are stored in the data register, the page data stored in the data register is subjected to code conversion to obtain corresponding state codes with different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
In the above scheme, before the page data stored in the data register is transcoded, the page data in the buffer register is controlled to be moved to the data register, so that the page type of the page data stored in the data register includes the LP, the MP and the UP.
In the above scheme, after the page data in the buffer memory register moves to the data register, the buffer memory register is released, so that the buffer memory register continues to store the next page data written according to the specific type ordering.
In the above scheme, after the page data stored in the data register is coded and converted, the state coding cycles of the different state bits are sequentially checked from the high order bit to the low order bit, and whether the page data in the cache register is moved to the data register is judged according to the checking result.
In the above scheme, different state identification bits correspond to different sub-data registers;
correspondingly, the step of judging whether to move the page data in the cache register to the data register according to the checking result comprises the following steps:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification.
In the above scheme, when the state code check corresponding to the state identification bit passes and the page data stored in the buffer register is empty, the next sequential loop check of the state code is controlled to be executed, and when the page data is determined to be stored in the buffer register, the page data stored in the buffer register is controlled to move to the sub-data register corresponding to the state identification bit, where the state identification bit passes the check of the data.
In the above scheme, the different status bits further include a status flag bit for indicating that writing of page data is completed;
correspondingly, the method further comprises the steps of:
and when the status identification bit for indicating that the writing of the page data is completed passes the verification, controlling to finish the process of writing the physical page into the flash memory array.
In the above scheme, when the first programming starts, moving the reference page data stored in the cache register to the data register, so that the page data with the types of LP, MP and UP are stored in the data register, and writing the page data stored in the data register into the flash memory array;
wherein the reference page data is used to indicate the execution of the first programming.
The data writing method of the flash memory provided by the embodiment of the invention has the following technical effects: in the one-time programming process of the flash memory, page data of LP, MP and UP are moved from a buffer register to a data register, and finally written into the flash memory array for the last time, so that the writing of a plurality of page data in the one-time programming process is realized, the data writing efficiency is improved, the time for inserting two pages of data after one-time programming in the related art is relatively reduced, and the continuity among a plurality of programming processes is ensured.
Drawings
FIG. 1 is a schematic diagram of a related art flash memory for data writing;
FIG. 2 is a schematic diagram of a flash memory according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating data writing of a flash memory according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a flow chart of writing data into a flash memory according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a state encoding table before encoding conversion of a flash memory according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a state encoding table after transcoding of a flash memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a flow chart of writing data into a flash memory according to an embodiment of the present invention;
FIG. 8 is a diagram of a state encoding table after transcoding of a flash memory according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a flow chart of writing data into a flash memory according to an embodiment of the present invention;
FIG. 10 is a diagram of a state encoding table after transcoding of a flash memory according to an embodiment of the present invention;
fig. 11 is a schematic diagram of a flow of writing data into a flash memory according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the examples provided herein are for the purpose of illustration only and are not intended to limit the invention. In addition, the embodiments provided below are some of the embodiments for carrying out the present invention, but not all of the embodiments for carrying out the present invention, and the technical solutions described in the embodiments of the present invention may be implemented in any combination without conflict.
It should be noted that, in the embodiments of the present invention, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a method or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such method or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other related elements (e.g., a step in a method or a unit in an apparatus, e.g., a unit may be a part of a circuit, a part of a processor, a part of a program or software, etc.) in a method or apparatus comprising the element.
The related art flash memory data writing schematic diagram is shown in fig. 1, wherein the NAND includes a buffer register, a data register, a flash memory array, and a controller, and the internal memory array of the NAND is accessed by taking a page as a basic unit. The writing time is the programming time and takes pages as basic units. To increase the speed of programming, the chip has a buffer register to which data is first stored and then written, and programming begins once the data is stored in the data register. After the data register is loaded and programming begins, the buffer register becomes empty and the next data can continue to be loaded, so that the internal programming and loading of data proceed in parallel, the buffer register being 1 page of data and the data register being 3 pages of data. There are three types of write data in NAND, LP, MP, UP, which are user-defined and the order is also user-defined, here user-defined as the write order of low, medium, and high page data.
In fig. 1, data page0 is first moved into a data register, page1 is stored in a buffer register, page2 is started to be tPROG, page2 is moved into the data register, so that page0, page1 and page2 are written into a flash memory array at one time, page3 is put into the buffer register, namely a first physical page is completed, a second physical page is started after the first physical page, when programming is executed, a low data type page3 is allowed to be moved into the data register from the buffer register, the programming is waited for to finish, page4 and page5 are moved from the buffer register to the data register, three pages of data are written into the flash memory register at one time, page3, page4 and page5 are all written into the flash memory register, page6 is put into the buffer register to complete the second physical page, and it can be seen that the time of page3 moved into the flash memory array is hidden in the programming, and the writing time of page4 and page5 is exposed, and the programming is waited for to finish. For example: the NV-DDR interface data writing speed is 200MB/s, so that the time of page4 and page5 moving into a data register keeps 80us for the time of the third physical page, page3 is low data, page4 and page5 are respectively data and high data, discontinuity is caused between two programming tPROGs, the third physical page starts after the second physical page is completed, and the like. Note that in the related art, in each programming, the inserted page data can only be low data, and both medium data and high data are rewritten after each programming, delaying the next programming.
The flash memory provided by the embodiment of the invention is explained next. Referring to fig. 2, a flash memory according to an embodiment of the present invention includes: a cache register 11, a data register 12, a flash array 13 and a controller 10. The buffer register is 1 page of data, and the data register is 3 pages of data. The controller 10 controls the data of the buffer memory 11 to move to the data register 12, and when the data of the low, medium and high pages are all moved in the data register 12, the data of the three pages are written into the flash memory array 13 from the data register 12 at one time.
According to the invention, low data, medium data and high data can not be shifted into the data register at one time in each programming, and finally are written into the flash memory array, as shown in fig. 3, a data writing schematic diagram of the flash memory provided by the embodiment of the invention is that firstly, the data register is shifted into the data page0, the page1 is stored in the cache register, the tPROG is started, the page2 is shifted into the data register, so that three pages of data of the page0, the page1 and the page2 are all in the data register, the flash memory array is written into the flash memory array at the last time, the page3 and the page4 are placed into the data register when the write data enter the flash memory array, a first physical page is completed, a second physical page starts after the first physical page, the page5 is shifted into the data register, at the moment, the page3 is stored in the data register, the page4 and the page5 are stored in the data register, the three pages are shifted into the data register after the three pages are in the state, the three pages of the page2 are written into the flash memory array after the three pages are written into the data register, the page4 is shifted into the three physical page5, the page4 is written into the three physical pages after the page4, the page4 is written into the three physical page5, and the page4 is written into the three physical page4 is written into the data register, and the three physical page is written into the three physical page5, and the page5 is written into the three physical page5, and the page is written into the data page. Note that in the embodiment of the present invention, in each programming, the inserted page data is low data, medium data and high data in sequence, and after three types of page data are written in one-time programming, the writing of the three page data is hidden in the programming process, so that the efficiency of writing the flash memory data is improved.
In one embodiment, a flash memory includes:
a buffer register for buffering page data of a single page size; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP;
the controller is used for controlling page data of the LP, the MP and the UP to be moved from the cache register to a data register respectively in a one-time programming process;
and writing page data stored by the data register into a flash memory array after the page data of the LP, the MP, and the UP are stored by the data register;
the data register is used for caching the page data of different page types moved from the cache register;
the flash memory array is used for storing the page data written by the controller.
Correspondingly, the controller is further configured to, after storing page data with types of LP, MP and UP in the data register, perform transcoding on the page data stored in the data register to obtain corresponding state codes with different status bits, and control the page data in the buffer register to move to the data register before transcoding, so that the page type of the page data stored in the data register includes the LP, MP and UP. Wherein the page data shifted into the data register is 16384 x 8 bits composed of 0 and 1 According to the embodiment, each page corresponds to 16384×8 physical units, and each physical unit receives three bits from LP/MP/UP. Since 1 bit of each page has two possible states of 0 and 1, one physical unit has 8 possible states (2 3 =8). And the three pages of data of the low, medium and high types are coded and converted to obtain a state coding table, wherein the different state bits comprise state identification bits used for indicating that the page data moves from the cache register to the data register. Specifically, 8 states correspond to 8 state bits, consisting of LV0, LV1, LV2 through LV 7.
In the above scheme, the controller is further configured to control the buffer register to release the buffer register after the page data in the buffer register is moved to the data register, so that the buffer register continues to store the next page data that is written according to the specific type ordering. Such as: before writing three pages of data of different types into the flash memory array, the three pages of data firstly move into the data register according to the sequence of the low-level page data, the low-level data move into the data register from the cache register, after the cache register is released, the data are stored in the cache register according to the sequence, and so on. In one embodiment, the size of the buffer register 11 is one data page, and the size of the data register 12 is three data pages. If the user requires low, medium and high order writing, the data is moved from one page of the cache register to a specific sub data register of the corresponding data register, after all three pages of data are moved into the corresponding sub data register, the three pages of data in the sub data register are encoded, and then the flash memory array is written according to the low, medium and high order, and after all the three pages of data are written, programming is completed.
In the above scheme, the controller is further configured to sequentially check the state coding cycles of the different state bits from high-order bits to low-order bits after performing code conversion on the page data stored in the data register, and determine whether to move the page data in the buffer register to the data register according to a check result.
In the above scheme, the data register includes a plurality of sub data registers for storing page data of different page types, and different state identification bits correspond to different sub data registers;
the controller is further configured to control page data in the cache register to be moved to a sub-data register corresponding to the status identification bit passing the check when the status code corresponding to the status identification bit in the different status bits passes the check in the process of checking the status codes of the different status bits from the high bit to the low bit.
The encoded state table obtained by encoding three pages of data stored in the data register is fixed, the above description is that 8 states correspond to 8 states bits, each state bit is composed of LV0, LV1, LV2 to LV7, 3 bits are respectively from LP/MP/UP, after being encoded and converted, the data of LV1 is encoded from 110 to 000, wherein 110 is respectively from UP/MP/LP in sequence, the state encoding sequences of other states bits are UP/MP/LP in the same way, the data of LV2 is encoded from 100 to 100, the data of LV3 is encoded from 000 to 010, and so on, the data of LV5 is encoded from 011 to 110, the data of LV6 is encoded from 001 to 101, and the data of LV7 is encoded from 101 to 011. After the encoding, when LV5 is over, the data of the status bits LV0 to LV5 stored in the three sub data registers are written, when LV7 is over, the data representing LV0 to LV6 is written, so that the judgment is started from the high level to the low level, that is, LV7, if LV7 is over, all the status bit data are written, the page data in the buffer register are not moved to the data register, programming is completed, if LV7 is not over, the judgment is continued for LV6, if LV6 is not over, LV5 is judged again, when LV5 is over, the low data to be written in the next programming is moved from the buffer register to the data register, the judgment is performed again for LV7, when LV6 is over, the middle data to be written in the next programming is moved from the buffer register to the data register, the judgment is performed again, when LV7 is over, the programming is finished, when the high data to be written in the next programming is already in the buffer register, and the data register is moved when waiting for the next programming.
And the controller is also used for controlling the execution of the next cyclic check when the state code corresponding to the state identification bit passes the check and the page data stored in the buffer register is empty, and controlling the page data stored in the buffer register to move to the sub-data register corresponding to the state identification bit of the data passing the check when the page data is determined to be stored in the buffer register. Such as: when LV5 passes, the low data to be written in the next programming should be shifted into the data register from the buffer memory register, but the low data is not yet available, namely, when the page data stored in the buffer memory register is empty, the loop judgment is continued, and when LV5 passes the next judgment, the buffer memory register has the low data, and the low data is shifted into the sub data register corresponding to the flag bit LV5 for identifying the low data.
The different status bits also comprise status identification bits for indicating that the writing of page data is completed;
and the controller is also used for controlling the programming to be ended when the state identification bit for indicating the completion of the writing of the page data passes the verification.
The buffer register is further used for buffering reference page data of a single page size which is written in according to a specific type sequence, and the reference page data is used for indicating the execution of first programming; the reference page data is as in page0, page1 and page2 in fig. 3.
The data register is further used for caching the reference page data of different page types which are moved from the cache register;
the controller is further configured to, when the first programming starts, move the reference page data in the cache register to the data register, so that page data with types of LP, MP and UP are stored in the data register, and write the page data stored in the data register into the flash memory array.
In one embodiment, a flash memory includes:
a buffer register for buffering page data of a single page size; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP;
the controller is used for controlling page data of the LP, the MP and the UP to be moved from the cache register to a data register respectively in a one-time programming process;
and writing page data stored by the data register into a flash memory array after the page data of the LP, the MP, and the UP are stored by the data register;
the data register is used for caching the page data of different page types moved from the cache register;
The flash memory array is used for storing the page data written by the controller.
In this embodiment, three different types of page data are shifted into the data register by one-time programming, one time programming corresponds to one tPROG, page0, page1 in fig. 3, after page2 is put into the buffer register, programming starts, fig. 4 is a flow chart of shifting three different types of page data into the data register by one-time programming, and then writing into the flash memory array:
step 1: the controller controls page data to move from the buffer register to the data register, and the buffer register is free after being released; for example, page0, page1 is in the data register, page2 is in the buffer register, after programming is started, page2 in the buffer register is shifted into the data register, and the buffer register is idle.
Step 2: and after the buffer register is released, the three pages of low, medium and high data in the data register are coded and converted.
The code conversion has two parts, the first part codes page data, which is to code user data into data which is convenient for chip designer to operate and design, the data register can store three pages of different types of data, wherein, the page data shifted into the data register is 16384 x 8 bits of data composed of 0 and 1, and specifically, each page corresponds to 16384 x 8 physical units, each physical unit receives three bits, and the three bits come from LP/MP/UP respectively. Since 1 bit of each page has two possible states of 0 and 1, one physical unit has 8 possible states (2 3 =8). Low, medium and high classThe three-page data of the type are coded to obtain a state coding table, wherein 8 state bits in the state coding table consist of LV0, LV1, LV2 to LV 7. Fig. 5 is a state encoding table of a user not encoded in the data register, fig. 6 is a state encoding table of encoded in the data register, it can be seen that corresponding sub data registers in the data register sequentially store low, middle and high data pages, data sub register 3 stores low data, data sub register 2 stores middle data, data sub register 1 stores high data, each state bit before the encoding is composed of 3 bits, 3 bits come from LP/MP/UP respectively, after the encoding conversion, data of LV1 is encoded from 110 to 000, 110 comes from UP/MP/LP respectively in sequence, and the state encoding sequence of other state bits is UP/MP/LP respectively, data of LV2 is encoded from 100 to 100, data of LV3 is encoded from 000 to 010, and so on, the state encoding after the encoding conversion is fixed, as shown in fig. 6, data of LV5 is encoded from 001 to 101, data of LV6 is encoded from 101 to 011. The coded LV5 is 110,0 in the data sub-register 3, and is indicated by a circle, and the bit is a state identification bit which is included in the state bit LV5 and used for indicating that the low data page moves from the cache register to the data register; 0 in LV6 is in data sub-register 2, which is said status bit LV6 comprising a status identification bit for indicating that the middle data page is moved from the cache register to the data register; similarly, 0 in data sub-register 1 in LV 7. The status flag bits indicating that page data is moved from the cache register to the data register after encoding all become 0. The second part is preprocessing, namely setting processing for environmental scripts and the like;
Step 3: after code conversion, the controller controls three pages of data of the data register to be written into the flash memory array at one time, and the state coding cycle of different state bits is sequentially carried out multi-type page data buffer downloading detection from high to low along with state coding change after writing.
Wherein the step 3 further comprises 3 steps:
step 301: as shown in fig. 7, when data is written into the flash memory array, the status code will change, firstly, the status flag bit of LV7 in the data sub-register 1 is judged, and if it is 1, the status flag bit of LV6 in the data sub-register 2 and the status flag bit of LV5 in the data page register 1 will not be judged any more, and the data in the buffer register cannot be instructed to be moved into the data register; if the status flag bit in LV7 is 0, the status flag bit in LV6 is continuously judged, if it is 1, it indicates that the data to be written in the next programming stored in the buffer register is shifted into the data sub-register 2, if it is 0, the status flag bit in LV5 is continuously judged, if it is 0, the loop judgment is continuously carried out, if it is 1, it indicates that the low data to be written in the next programming stored in the buffer register is shifted into the data sub-register 3, because the data writing sequence is low, medium and high, the sequence of shifting into the data register from the buffer is also low, medium and high, therefore, the status flag bit in LV5 is first 1, then the status flag bit in LV6 is 1 again, and finally the status flag bit in LV7 is 1, and programming is completed. When special conditions exist and the status flag bit in the LV5 is 0 or the status flag bit of the LV5 is 1, the buffer register has no low data, and then the loop sequential verification is continued;
As shown in fig. 8, when the status flag bit in LV5 is 1, it means that all the data of LV0 to LV5 in the three sub-data registers are written, after all the data of LV0 to LV5 are changed to 1, and the status flag bit in LV5 is 1, both the status bits LV6 and LV7 are 1 in the data page register 3, and all the data sub-registers 3 are 1, so that the data page register 3 is not needed any more, the low data to be written in the cache register in the next programming can be moved into the data sub-registers 3, and at this time, the status flag bits in LV6 and LV7 are 0, and then the data to be written in the cache register in the next programming cannot be moved into the data sub-registers 2;
step 302: as shown in fig. 9, if it is judged that the low data has been shifted into the data sub-register 3, and then the loop sequentially checks, if the status flag bit in LV6 becomes 1, as shown in fig. 10, LV6 passes, that is, all the data of LV0 to LV6 in the three sub-data registers are written in, after the status flag bits in LV0 to LV6 are all 1, LV7 is 1 in the data page register 2 and all the data sub-registers 2 are 1, so that the data page register 2 is not needed any more, and the data to be written in the cache register for the next programming can be shifted into the data sub-register 2, and at this time, the status flag bit in LV7 is 0; if the state identification bit in LV6 is 0, continuing to circularly judge; when the state flag bit of the LV5 is 1, but the low data is not yet, and the cycle judgment is continued, after the state flag bit of the LV6 is 1, the low data is only started, the low data is allowed to be inserted into the data register 3, whether the data is present or not is judged, and if the data is present, the medium data is inserted into the data register 2; if LV6 does not pass or low data or medium data is not transmitted at the moment, continuing to carry out cyclic and sequential verification; there is another special case that when the status flag of LV5 and LV6 is 1 and neither the low data nor the medium data is available, the low data and the data to be written in the next programming are placed in the corresponding positions of the data register before the status flag of LV7 is not 1, the high data is still placed in the buffer register, and the next programming is waited to be placed in the data sub-register 1 again.
Step 303: as shown in fig. 11, after the status flag bits of LV5 and LV6 are all 1, and after the low data and the medium data to be written in the next programming have been moved into the data sub-register 3 and the data sub-register 2, if the status flag bit of LV7 is 1, the high data to be written in the next programming is already in the buffer register, and the data register 1 is put after the next programming is started.
Based on the above-mentioned flash memory provided by the embodiment of the present invention, the embodiment of the present invention further provides a data writing method of the flash memory, including:
in the one-time programming process, low-middle page data which need to be written in next programming are moved from a cache register to a data register, and high data are stored in the cache; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP; after the data register stores page data of the LP, the MP and the UP, writing the page data stored by the data register into a flash memory array;
after page data with the types of LP, MP and UP are stored in the data register, the page data stored in the data register is subjected to code conversion to obtain corresponding state codes of different state bits; wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register. And encoding three pages of data of different types shifted into the data register, and performing encoding conversion on the three pages of data of low, medium and high types to obtain a state encoding table, wherein 8 state bits in the state encoding table consist of LV0, LV1, LV2 and LV 7. Fig. 5 is a state encoding table of a user not encoded in the data register, fig. 6 is a state encoding table of the data register after encoded conversion, it can be seen that corresponding sub data registers in the data register store three pages of data of low, medium and high in order, data sub register 3 stores low data, data sub register 2 stores medium data, data sub register 1 stores high data, each state bit before encoded conversion is composed of 3 bits, 3 bits come from LP/MP/UP, respectively, after encoded conversion, the state encoding table after encoded conversion is fixed, as shown in fig. 6, data of LV5 is encoded from 011 to 110, data of LV6 is encoded from 001 to 101, and data of LV7 is encoded from 101 to 011. The coded LV5 is 110,0 in the data sub-register 3, and is indicated by a circle, and the bit is a state identification bit which is included in the state bit LV5 and used for indicating that the low data page moves from the cache register to the data register; 0 in LV6 is in data sub-register 2, which is said status bit LV6 comprising a status identification bit for indicating that the middle data page is moved from the cache register to the data register; similarly, 0 in data sub-register 1 in LV 7. The status flag bits indicating that page data is moved from the cache register to the data register after encoding all become 0.
Before the page data stored in the data register is coded, the page data in the buffer register is controlled to move to the data register, so that the page type of the page data stored in the data register comprises the LP, the MP and the UP. After the page data in the cache register is moved to the data register, the cache register is released so that the cache register continues to store the next page data written according to the particular type of ordering.
After the page data stored in the data register are coded and converted, the state coding cycles of the different state bits are checked sequentially from high order bits to low order bits, and whether the page data in the cache register are moved to the data register is judged according to the checking result. The data register comprises a plurality of sub-data registers for storing page data of different page types, and different state identification bits correspond to different sub-data registers; correspondingly, the step of judging whether to move the page data in the cache register to the data register according to the checking result comprises the following steps:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification. When data is written into the flash memory array, the state code is changed, the state identification bit of LV7 in the data sub-register 1 is judged firstly, and if the state identification bit is 1, the state identification bit of LV6 in the data sub-register 2 and the state identification bit of LV5 in the data page register 1 are not judged any more, and the data in the cache register cannot be indicated to be moved into the data register; if the status flag bit in LV7 is 0, the status flag bit in LV6 is continuously judged, if it is 1, the status flag bit indicating that the data to be written in the next programming stored in the cache register is shifted into the data sub-register 2, if it is 0, the status flag bit in LV5 is continuously judged, if it is 1, the status flag bit indicating that the low data to be written in the next programming stored in the cache register is shifted into the data sub-register 3, because the data writing sequence is low, the sequence of shifting into the data register from the cache is also low, therefore, the status flag bit of LV5 is first 1, then the status flag bit in LV6 is again 1, the data to be written in the next programming stored in the data sub-register 2 is indicated, and finally the status flag bit of LV7 is 1, the high data to be written in the next programming is shifted into the data sub-register 3, and the high data to be written in the next programming in the cache register is waited for the next data sub-register 1 after programming.
And when the state code corresponding to the state identification bit passes the verification, and the page data stored in the cache register is empty, controlling to execute the next cycle of verification, and when the page data is determined to be stored in the cache register, controlling the page data stored in the cache register to move to a sub-data register corresponding to the state identification bit of the data passing the verification. When the state flag bit of the LV5 is 1, but the low data is not yet, and the cycle judgment is continued, after the state flag bit of the LV6 is 1, the low data is only started, the low data is allowed to be inserted into the data register 3, whether the data is present or not is judged, and if the data is present, the medium data is inserted into the data register 2; if LV6 does not pass or low data or medium data is not transmitted at the moment, continuing to carry out cyclic and sequential verification;
and when the state identification bit for indicating the completion of page data writing passes the verification, controlling to end the programming. I.e., the states in LV5, LV6 and LV7 are all identified as 1, programming ends.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (20)
1. A flash memory, comprising:
a buffer register for buffering page data of a single page size; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP; one physical page includes: one of said LP, one of said MPs, and one of said UP;
a data register, comprising: a sub data register storing page data of different page types;
a flash memory array for storing the page data written by the controller;
the controller is respectively connected with the cache register and the data register, and is used for allowing the cache register to insert page data of the (n+1) th physical page and allowing page data of the (n+1) th physical page currently cached in the cache register to be moved from the cache register to an idle sub-data register corresponding to the page type of the page data of the (n+1) th physical page currently cached in the cache register in the process that the data register writes the Nth physical page into the flash memory array; wherein N is a natural number.
2. The flash memory device of claim 1, wherein,
the controller is further configured to control writing page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register.
3. The flash memory device of claim 1, wherein,
the controller is further configured to, after storing page data with types of LP, MP and UP in the data register, perform code conversion on the page data stored in the data register to obtain corresponding state codes of different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
4. The flash memory device of claim 3, wherein,
the controller is further configured to control page data in the buffer register to be moved to the data register before performing transcoding on the page data stored in the data register, so that a page type of the page data stored in the data register includes the LP, the MP, and the UP.
5. The flash memory device of claim 4, wherein,
and the controller is also used for controlling the buffer register to release the buffer register after the page data in the buffer register is moved to the data register, so that the buffer register continues to store the next page data which is written according to the specific type ordering.
6. The flash memory device of claim 3, wherein,
and the controller is also used for sequentially and circularly checking the state codes of the different state bits from high order to low order after the page data stored in the data register are subjected to code conversion, and judging whether to move the page data in the cache register to the data register according to a checking result.
7. The flash memory of claim 6 wherein different ones of said status identification bits correspond to different ones of said sub-data registers;
and the controller is also used for controlling the page data in the buffer register to move to the sub-data register corresponding to the state identification bit passing the verification when the state code corresponding to the state identification bit in the different state bits passes the verification.
8. The flash memory device of claim 7, wherein,
and the controller is further used for controlling to execute the next sequential cyclic check of the state code when the state code check corresponding to the state identification bit passes and the page data stored in the cache register is empty, and controlling the page data stored in the cache register to move to the sub-data register corresponding to the state identification bit of the data which passes the check when the page data is determined to be stored in the cache register.
9. The flash memory of claim 6 wherein said different status bits further comprise status identification bits for indicating that page data writing is complete;
and the controller is also used for controlling the process of writing the physical page into the flash memory array to be ended when the status identification bit for indicating the completion of writing the page data passes the verification.
10. The flash memory device of any one of claims 1 to 9, wherein,
the buffer register is further used for buffering reference page data of a single page size which is written in according to a specific type sequence, and the reference page data is used for indicating the execution of first programming;
the data register is further used for caching the reference page data of different page types which are moved from the cache register;
the controller is further configured to, when the first programming starts, move the reference page data in the cache register to the data register, so that page data with types of LP, MP and UP are stored in the data register, and write the page data stored in the data register into the flash memory array.
11. A method for writing data to a flash memory, the method comprising:
Writing page data of an Nth physical page stored in a data register into the flash memory array; wherein N is a natural number; the data register comprises a sub-data register for storing page data of different page types; the page data belongs to one of the following page types: lower page LP, middle page MP, upper page UP; one physical page includes: one of said LP, one of said MPs, and one of said UP;
in the process that the data register writes the Nth physical page into the flash memory array, a buffer register is allowed to insert page data of the (n+1) th physical page, and page data of the (n+1) th physical page currently buffered in the buffer register is allowed to be moved from the buffer register to a sub-data register which is free corresponding to the page type of the page data of the (n+1) th physical page currently buffered in the buffer register.
12. The data writing method of claim 11, wherein the method further comprises:
after the data register stores page data of the LP, the MP, and the UP, the page data stored by the data register is written into the flash memory array.
13. The data writing method of claim 11, wherein the method further comprises:
After page data with the types of LP, MP and UP are stored in the data register, the page data stored in the data register is subjected to code conversion to obtain corresponding state codes of different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
14. The data writing method of claim 13, wherein the method further comprises:
before the page data stored in the data register is coded, the page data in the buffer register is controlled to move to the data register, so that the page type of the page data stored in the data register comprises the LP, the MP and the UP.
15. The data writing method of claim 14, wherein the method further comprises:
after the page data in the cache register is moved to the data register, the cache register is released so that the cache register continues to store the next page data written according to the particular type of ordering.
16. The data writing method of claim 13, wherein the method further comprises:
After the page data stored in the data register are coded and converted, the state coding cycles of the different state bits are checked sequentially from high order bits to low order bits, and whether the page data in the cache register are moved to the data register is judged according to the checking result.
17. The data writing method of claim 16, wherein different ones of the status identification bits correspond to different ones of the sub-data registers;
correspondingly, the step of judging whether to move the page data in the cache register to the data register according to the checking result comprises the following steps:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification.
18. The data writing method of claim 17, wherein the method further comprises:
when the state code corresponding to the state identification bit passes the verification, and the page data stored in the buffer register is empty, controlling to execute the next sequential loop verification of the state code, and when the page data is stored in the buffer register, controlling the page data stored in the buffer register to move to the sub-data register corresponding to the state identification bit of the data passing the verification.
19. The data writing method of claim 16, wherein the different status bits further comprise status identification bits for indicating that writing of page data is completed;
correspondingly, the method further comprises the steps of:
and when the status identification bit for indicating that the writing of the page data is completed passes the verification, controlling to finish the process of writing the physical page into the flash memory array.
20. The data writing method according to any one of claims 11 to 19, wherein the method further comprises:
when the first programming starts, moving the reference page data stored in the cache register to the data register, so that page data with the types of LP, MP and UP are stored in the data register, and writing the page data stored in the data register into the flash memory array;
wherein the reference page data is used to indicate the execution of the first programming.
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