CN113220602A - Data writing method of flash memory and flash memory - Google Patents

Data writing method of flash memory and flash memory Download PDF

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Publication number
CN113220602A
CN113220602A CN202110474501.3A CN202110474501A CN113220602A CN 113220602 A CN113220602 A CN 113220602A CN 202110474501 A CN202110474501 A CN 202110474501A CN 113220602 A CN113220602 A CN 113220602A
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data
page
register
flash memory
page data
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CN113220602B (en
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万维俊
李跃平
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention discloses a data writing method of a flash memory and a flash memory, wherein the flash memory comprises the following steps: a cache register for caching page data of a single page size; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; one physical page includes: one LP, one MP, and one UP; a data register, comprising: a sub data register storing page data of different page types; the flash memory array is used for storing page data written by the controller; the controller is respectively connected with the cache register and the data register and is used for allowing the cache register to insert page data of the (N +1) th physical page and allowing the page data of the (N +1) th physical page cached in the cache register to be moved from the cache register to a vacant sub data register corresponding to the page type of the page data of the (N +1) th physical page cached in the cache register in the process that the data register writes the Nth physical page into the flash memory array; wherein N is a natural number.

Description

Data writing method of flash memory and flash memory
The application is a divisional application of Chinese patent application with application date of 2018, 10 and 09, application number of 201811173662.3, and invention name of 'a data writing method of flash memory and flash memory'.
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a data writing method for a flash memory and a flash memory.
Background
In the related art, in a one-time programming process of writing Data into a physical array of the flash memory, only one-time movement of page Data from the Cache register to the Data register can be realized, so that when the number of Data pages programmed into the physical array is more than one, the page Data needs to be separately moved from the Cache register to the Data register after the programming is finished, the efficiency of writing the Data into the flash memory array is low, and the programming is not continuous.
Disclosure of Invention
In view of this, embodiments of the present invention provide a data writing method for a flash memory and a flash memory, which can move different types of page data from a cache register to a data register in a one-time programming process, thereby ensuring continuity of programming.
The technical scheme of the embodiment of the invention is realized as follows:
an embodiment of the present invention provides a flash memory, including:
a cache register for caching page data of a single page size; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; one physical page includes: one said LP, one said MP, and one said UP;
a data register, comprising: a sub data register storing page data of different page types;
the flash memory array is used for storing the page data written by the controller;
the controller is respectively connected with the cache register and the data register, and is configured to allow the cache register to insert page data of an (N +1) th physical page and allow page data of an (N +1) th physical page currently cached in the cache register to be moved from the cache register to a sub data register which is free corresponding to a page type of the page data of the (N +1) th physical page currently cached by the cache register in a programming process of writing the nth physical page into the flash memory array by the data register; wherein N is a natural number.
In the above solution, the controller is further configured to control writing of the page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register.
In the foregoing solution, the controller is further configured to perform code conversion on the page data stored in the data register after the page data of the types LP, MP, and UP are stored in the data register, so as to obtain corresponding state codes with different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
In the foregoing solution, the controller is further configured to control the page data in the cache register to move to the data register before performing code conversion on the page data stored in the data register, so that the page type of the page data stored in the data register includes the LP, the MP, and the UP.
In the foregoing scheme, the controller is further configured to release the cache register after the page data in the cache register is moved to the data register, so that the cache register continues to store the next page data written according to the specific type sequence.
In the above scheme, the controller is further configured to perform, after code conversion is performed on the page data stored in the data register, sequential cyclic check on the state codes of the different state bits from a high bit to a low bit, and determine whether to move the page data in the cache register to the data register according to a check result.
In the above scheme, different status flag bits correspond to different sub-data registers;
the controller is further configured to control the page data in the cache register to move to the sub-data register corresponding to the status flag bit that passes the check when the status code corresponding to the status flag bit in the different status bits passes the check.
In the foregoing scheme, the controller is further configured to control to execute sequential cyclic checking of a next state code when the state code corresponding to the state identification bit passes the check and the page data stored in the cache register is empty, and control the page data stored in the cache register to move to the sub-data register corresponding to the state identification bit where the check of the data passes when it is determined that the page data is stored in the cache register.
In the above scheme, the different status bits further include a status flag bit for indicating that the writing of the page data is completed;
the controller is further configured to control to end the process of writing the physical page into the flash memory array when the status flag indicating that the page data write is completed passes verification.
In the above scheme, the cache register is further configured to cache reference page data of a single page size written according to a specific type of sorting, where the reference page data is used to indicate execution of first programming;
the data register is further used for caching the reference page data of different page types moved from the cache register;
the controller is further configured to move the reference page data in the cache register to the data register when the first programming starts, so that the data register stores page data of the types LP, MP, and UP, respectively, and write the page data stored in the data register into the flash memory array.
The embodiment of the invention also provides a data writing method of the flash memory, which comprises the following steps:
writing page data of the Nth physical page stored by the data register into the flash memory array; wherein N is a natural number; the data register comprises a subdata register for storing page data of different page types; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; one physical page includes: one said LP, one said MP, and one said UP;
in the process that the data register writes the nth physical page into the flash memory array, allowing the cache register to insert the page data of the (N +1) th physical page, and allowing the page data of the (N +1) th physical page currently cached in the cache register to be moved from the cache register to a sub data register which is free corresponding to the page type of the page data of the (N +1) th physical page currently cached by the cache register.
In the above-described scheme, after the page data of the LP, the MP, and the UP are stored in the data register, the page data stored in the data register is written into the flash memory array.
In the above scheme, after the page data of the types LP, MP and UP are stored in the data register, the page data stored in the data register is subjected to code conversion to obtain corresponding state codes of different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
In the above scheme, before performing code conversion on the page data stored in the data register, the page data in the cache register is controlled to move to the data register, so that the page type of the page data stored in the data register includes the LP, the MP, and the UP.
In the above scheme, after the page data in the cache register is moved to the data register, the cache register is released, so that the cache register continues to store the next page data written according to the specific type sequence.
In the above scheme, after the page data stored in the data register is subjected to code conversion, the state coding cycles of the different state bits are sequentially verified from the high bit to the low bit, and whether the page data in the cache register is moved to the data register is determined according to a verification result.
In the above scheme, different status flag bits correspond to different sub-data registers;
correspondingly, the determining whether to move the page data in the cache register to the data register according to the check result includes:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification.
In the above scheme, when the status code corresponding to the status flag passes the check and the page data stored in the cache register is empty, the next sequential cyclic check of the status code is controlled to be executed, and when it is determined that the page data is stored in the cache register, the page data stored in the cache register is controlled to move to the sub-data register corresponding to the status flag that the check of the data passes.
In the above scheme, the different status bits further include a status flag bit for indicating that the writing of the page data is completed;
correspondingly, the method further comprises the following steps:
and when the status flag bit for indicating the completion of the writing of the page data passes the verification, controlling to end the process of writing the physical page into the flash memory array.
In the above scheme, when the first programming starts, the reference page data stored in the cache register is moved to the data register, so that the page data of the types LP, MP, and UP are stored in the data register, and the page data stored in the data register is written into the flash memory array;
wherein the reference page data is used to indicate execution of first programming.
The data writing method of the flash memory and the flash memory provided by the embodiment of the invention have the following technical effects: in the programming process, the flash memory moves page data of LP, MP and UP from the cache register to the data register, and writes the page data into the flash memory array for the last time, so that the writing of a plurality of page data in the programming process is realized, the data writing efficiency is improved, the time for inserting two pages of data after the programming in the related technology is relatively reduced, and the continuity among a plurality of programming processes is ensured.
Drawings
FIG. 1 is a diagram illustrating data writing of a flash memory provided in the related art;
FIG. 2 is a schematic diagram of a flash memory according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating data writing of a flash memory according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating data writing of a flash memory according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a state code table of a flash memory according to an embodiment of the present invention before code conversion;
FIG. 6 is a diagram illustrating a state code table after code conversion of a flash memory according to an embodiment of the present invention;
FIG. 7 is a flow chart illustrating data writing of a flash memory according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating a state code table after code conversion of a flash memory according to an embodiment of the present invention;
FIG. 9 is a flow chart illustrating data writing of a flash memory according to an embodiment of the present invention;
FIG. 10 is a diagram illustrating a state code table after code conversion of a flash memory according to an embodiment of the present invention;
fig. 11 is a schematic flow chart illustrating data writing of the flash memory according to the embodiment of the invention.
Detailed Description
The present invention will be described in further detail below with reference to the accompanying drawings and examples. It should be understood that the examples provided herein are merely illustrative of the present invention and are not intended to limit the present invention. In addition, the following embodiments are provided as partial embodiments for implementing the present invention, not all embodiments for implementing the present invention, and the technical solutions described in the embodiments of the present invention may be implemented in any combination without conflict.
It should be noted that, in the embodiments of the present invention, the terms "comprises", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion, so that a method or apparatus including a series of elements includes not only the explicitly recited elements but also other elements not explicitly listed or inherent to the method or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other related elements in a method or apparatus including the element (e.g., steps in a method or elements in an apparatus, such as units that may be part of a circuit, part of a processor, part of a program or software, etc.).
A data write schematic diagram of a related art flash memory is shown in fig. 1, where a NAND includes a cache register, a data register, a flash memory array, and a controller, and an internal memory array of the NAND is accessed in a page unit. When writing, namely programming, the page is also taken as a basic unit. In order to increase the programming speed, the chip is provided with a buffer register, data are firstly stored in the buffer register and then written into the data register, and once the data are stored in the data register, the programming is started. After the data register is loaded and programming begins, the buffer register becomes empty and the next data can be loaded, so that the internal programming and data loading are performed in parallel, the buffer register size is 1 page of data, and the data register size is 3 pages of data. There are three types of write data in NAND, LP, MP, UP, which are user-defined, and the sequence is also user-defined, where user-defined is the write sequence of low, medium, and high page data.
As shown in fig. 1, data page0 and page1 are first moved into a data register, page2 is stored in a cache register, tPROG is started, page2 is moved into the data register, page0, page1 and page2 are written into a flash memory array at a time, page3 is placed into the cache register, that is, a first physical page is completed, a second physical page is started after the first physical page, during program execution, page3, which is a low data type page, is allowed to be moved into the data register from the cache, the program is waited for the end of the program, page4 and page5 are moved into the data register from the cache register, three pages of data, page3, page4 and page5, are all written into the flash memory register at a time, page6 is placed into the cache register, and the second physical page is completed, it can be seen that the time for page3 to be moved into the flash memory array is hidden in the program at a time, and the time for writing into page4 and page5 needs to be exposed, and the time for waiting for the end of the program. For example: when the NV-DDR interface data writing speed is 200MB/s, the time for shifting the page4 and the page5 into the data register delays the time for the third physical page by 80us, the page3 is low data, the page4 and the page5 are medium data and high data respectively, the two times of programming tPROG are not continuous, after the second physical page is completed, the third physical page starts, and the like. Note that, in the related art, the inserted page data can only be low data in each programming, and both the medium data and the high data are written after each programming, delaying the next programming.
Next, a description will be given of a flash memory provided in an embodiment of the present invention. Fig. 2 is a schematic diagram of a flash memory according to an embodiment of the present invention, and referring to fig. 2, the flash memory according to the embodiment of the present invention includes: a cache register 11, a data register 12, a flash memory array 13 and a controller 10. The cache register size is 1 page of data and the data register size is 3 pages of data. The controller 10 controls the page data of the cache register 11 to move to the data register 12, and after all the low, medium and high three pages of data in the data register 12 are moved in, the three pages of data are written into the flash memory array 13 from the data register 12 at one time.
In the related art, each programming cannot be performed by shifting three different types of page data of the data register at one time, the invention shifts low data, medium data and high data into the data register in one programming and finally writes into the flash memory array, as shown in fig. 3, which is a data writing schematic diagram of the flash memory provided by the embodiment of the invention, firstly, data page0, page1 are shifted into the data register, page2 is stored in the cache register, tPROG is started, page2 is shifted into the data register, so that three pages of data, page0, page1 and page2 are all in the data register, and finally, data is written into the flash memory array, page3 and page4 are put into the data register when data is written into the flash memory array, page5 is put into the cache register, a first physical page is completed, a second physical page starts after the first physical page, when the programming rotpg is performed, page data 5 in the data register is shifted into the data register, and at this time, page3 is included in the data register, page4 and page5, after status coding is performed on three pages of data, page3, page4 and page5 of page data are written into the flash memory array at one time, when data is written, page6, page7 are moved into the data register, page8 is stored in the cache register, the programming is finished, all three pages of data are written into the second physical page, it can be seen that the time for moving page3, page4 and page5 into the data register is hidden in the programming, after three pages of data are written, the programming writing window is closed, after the second physical page is finished, the third physical page is started, and the like, backward pushing is performed. Note that in the embodiment of the present invention, in each programming, the inserted page data is low data, medium data, and high data in sequence, and after three types of page data are written in one programming, the writing of the three page data is hidden in the programming process, so that the data writing efficiency of the flash memory is improved.
In one embodiment, a flash memory includes:
a cache register for caching page data of a single page size; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP;
a controller for controlling page data of page types respectively LP, MP and UP to move from the buffer register to a data register in a one-time programming process;
and a flash memory array for writing the page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register;
the data register is used for caching the page data of different page types moved from the cache register;
the flash memory array is used for storing the page data written by the controller.
Correspondingly, the controller is further configured to perform code conversion on the page data stored in the data register after the page data of the types LP, MP, and UP are stored in the data register, to obtain corresponding state codes of different state bits, and control the page data in the buffer register to move to the data register before the code conversion, so that the page types of the page data stored in the data register include the LP, MP, and UP. The page data shifted into the data register is 16384 × 8 bits of data composed of 0 and 1, and specifically, each page corresponds to 16384 × 8 physical units, and each physical unit receives three bits from LP/MP/UP. Since 1 bit of each page has two possible states, 0 and 1, there are 8 possible states (2) for a physical unit38). And encoding and converting the three low-medium type pages of data to obtain a state encoding table, wherein the different state bits comprise state identification bits for indicating that the page data is moved from the cache register to the data register. Specifically, the 8 states correspond to 8 state bits, consisting of LV0, LV1, LV2 through LV 7.
In the foregoing scheme, the controller is further configured to release the cache register after the page data in the cache register is moved to the data register, so that the cache register continues to store the next page data written according to the specific type sequence. Such as: before writing three pages of different types of data into the flash memory array, the three pages of data are firstly moved into the data register according to the sequence of page data of low, medium and high, the low data are moved into the data register from the cache register, after the cache register is released, the medium data are stored in the cache register according to the sequence, and so on. In one embodiment, the size of the cache register 11 is one data page, and the size of the data register 12 is three data pages. If the user requires the low, medium and high order writing, the data is moved from the buffer register to the specific subdata register of the corresponding data register page by page, after all three pages of data are moved into the corresponding subdata register, the three pages of data in the subdata register are encoded, and then the data is written into the flash memory array once according to the low, medium and high order, and after all the low, medium and high pages of data are written, the programming is completed.
In the foregoing solution, the controller is further configured to, after code conversion is performed on the page data stored in the data register, sequentially check the state code cycles of the different state bits from a high bit to a low bit, and determine whether to move the page data in the cache register to the data register according to a check result.
In the above solution, the data register of the controller includes a plurality of sub data registers for storing page data of different page types, and different status flag bits correspond to different sub data registers;
the controller is further configured to control the page data in the cache register to move to the sub-data register corresponding to the checked state identification bit when the state code corresponding to the state identification bit in the different state bits passes the check in the process of checking the state codes of the different state bits from the high bit to the low bit.
The encoding state table obtained by encoding the three pages of data stored in the data register is fixed, 8 states are corresponding to 8 state bits, the encoding state table is composed of LV0, LV1, LV2 to LV7, each state bit is composed of 3 bits, the 3 bits are respectively from LP/MP/UP, after encoding conversion, the data of LV1 is encoded into 000 from 110, wherein 110 is respectively from UP/MP/LP in sequence, the state encoding sequence of other state bits is UP/MP/LP in the same way, the data of LV2 is encoded into 100 from 100, the data of LV3 is encoded into 010 from 000, and so on, the data of LV5 is encoded into 110 from 011, the data of LV6 is encoded into 101 from 001, and the data of LV7 is encoded into 011 from 101. After encoding, LV5 is that the data of status bits LV0 to LV5 stored in the three sub-data registers are written in, LV7 is passed, which represents that the data of LV0 to LV6 are written in, so that the judgment is started from LV7 from high to low, if LV7 passes, all status bit data are written in, the page data in the buffer register is not moved to the data register, programming is completed, if LV7 does not pass, LV6 is continuously judged, if LV6 does not pass, LV5 is judged, at this time LV5 passes, the low data to be written in next programming is moved into the data register from the buffer register, the recirculation judgment LV7 is moved to LV6, at this time LV6 passes, the data to be written in next programming is moved into the data register from the buffer register, the recirculation judgment is made, at this time LV7 passes, the programming is finished, and the high data to be written in next programming is already in the buffer register, the data register is shifted in when waiting for the next programming.
The controller is further configured to control execution of next cyclic check when the status code corresponding to the status flag bit passes the check and the page data stored in the cache register is empty, and control the page data stored in the cache register to move to the sub-data register corresponding to the status flag bit where the check of the data passes when it is determined that the page data is stored in the cache register. Such as: when LV5 passes, the low data to be written in next programming should be shifted from the buffer register to the data register, but the low data is not available, that is, when the page data stored in the buffer register is empty, the loop judgment is continued, and when LV5 passes next judgment, the buffer register has the low data, the low data is shifted into the sub data register corresponding to the flag LV5 for identifying the low data.
The different status bits also comprise status identification bits used for indicating the completion of the writing of the page data;
and the controller is also used for controlling the programming to be ended when the status flag bit for indicating the completion of the writing of the page data passes the verification.
The cache register is further used for caching reference page data with a single page size written according to a specific type sequence, and the reference page data is used for indicating the execution of first programming; the reference page data is like pages 0, pages 1, and pages 2 in FIG. 3.
The data register is further used for caching the reference page data of different page types moved from the cache register;
the controller is further configured to move the reference page data in the cache register to the data register when the first programming starts, so that the data register stores page data of the types LP, MP, and UP, respectively, and write the page data stored in the data register into the flash memory array.
In one embodiment, a flash memory includes:
a cache register for caching page data of a single page size; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP;
a controller for controlling page data of page types respectively LP, MP and UP to move from the buffer register to a data register in a one-time programming process;
and a flash memory array for writing the page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register;
the data register is used for caching the page data of different page types moved from the cache register;
the flash memory array is used for storing the page data written by the controller.
In this embodiment, one-time programming may shift three different types of page data into the data register, where one-time programming corresponds to one tPROG, page0, page1 shifting into the data register, and after page2 is put into the cache register, the programming starts, and fig. 4 is a flowchart of one-time programming to shift three different types of page data into the data register and then write into the flash memory array:
step 1: the controller controls page data to move from the cache register to the data register, and the cache register is idle after being released; for example, page0, page1, at the data register, page2 at the cache register, after programming begins, moves page2 in the cache register into the data register, and the cache register is free.
Step 2: and after the cache register is released, performing code conversion on the three pages of low-medium data in the data register.
The code conversion has two parts of contents, the first part codes page data, the data of a user is coded into data which is convenient for a chip designer to operate and design, the data register can store three pages of data with different types, wherein the page data shifted into the data register is 16384 × 8 bits of data consisting of 0 and 1, the data is specifically stored in the flash memory array, each page also corresponds to 16384 × 8 physical units, and each physical unit receives three bits which come from LP/MP/UP respectively. Since 1 bit of each page has two possible states, 0 and 1, there are 8 possible states (2) for a physical unit38). The three pages of data of low and medium height type are coded and converted to obtain a state code table, wherein the state code table has 8 state bits, and the state bits are LV0, LV1, LV2 to LV 7. FIG. 5 is a status code table of user without code conversion in the data register, FIG. 6 is a status code table of code conversion stored in the data register, it can be seen that, the corresponding sub-data registers in the data register store three pages of data in low, medium and high order in sequence, the data sub-register 3 stores low data, the data sub-register 2 stores medium data, the data sub-register 1 stores high data, each status bit before code conversion is composed of 3 bits, 3 bits are respectively from LP/MP/UP, after code conversion, the data of LV1 is coded from 110 to 000, wherein 110 is respectively from UP/MP/LP in sequence, and similarly, the status code sequence of other status bits is UP/MP/LP, the data of LV2 is coded from 100 to 100, the data of LV3 is coded from 000 to 010, and so on, the status code table after code conversion is fixed, as shown by the data in FIG. 6, data for LV5 was encoded from 011 to 110, data for LV6 was encoded from 001 to 101, and data for LV7 was encoded from 101 to 011. The encoded LV5 is 110,0 is indicated by a circle in the data sub-register 3, and the bit is a state identification bit included in the state bit LV5 for indicating that the low data page is moved from the buffer register to the data register; LV6 with 0 in data subregister 2, bitThe status bit LV6 includes a status flag bit for indicating that the middle data page is moved from the cache register to the data register; similarly, 0 in LV7 in data sub-register 1. After encoding, all status flag bits indicating that the page data is moved from the cache register to the data register become 0. The second part is preprocessing, namely setting processing of environment scripts and the like;
and step 3: after code conversion, the controller controls the three pages of data of the data register to be written into the flash memory array once, and after the three pages of data are written, along with the change of the state codes, the state codes of different state bits are circularly and sequentially subjected to multi-type page data cache downloading detection from high bits to low bits.
Wherein step 3 comprises 3 steps:
step 301: as shown in fig. 7, when data is written into the flash memory array, the status code is changed, the status flag bit of LV7 in the data sub-register 1 of LV7 is first determined, and if it is 1, the status flag bit of LV6 in the data sub-register 2 and the status flag bit of LV5 in the data page register 1 are no longer determined, and it cannot indicate to move the data in the cache register into the data register; if the status flag bit in LV7 is 0, the status flag bit in LV6 is continuously determined, if 1, it indicates to shift the data to be written by the next programming stored in the buffer register into the data sub-register 2, if 0, the status flag bit in LV5 is continuously determined, if 0, the loop determination is continuously performed, if 1, it indicates to shift the low data to be written by the next programming stored in the buffer register into the data sub-register 3, because the data writing sequence is low, medium, high, the sequence of shifting from the buffer into the data register is also low, medium, high, so the status flag bit of LV5 is 1 first, then the status flag bit in LV6 is 1 again, and finally the status flag bit of LV7 is 1, and the programming is completed. When the status flag bit in LV5 is 0 or the status flag bit in LV5 is 1, no low data is in the cache register, and the cyclic sequential verification is continued;
as shown in fig. 8, when the status flag bit in LV5 is 1, it means that all the data in LV0 to LV5 in the three sub-data registers are written, all the data in LV0 to LV5 are 1, and after the status flag bit in LV5 is 1, both the two status bits LV6 and LV7 are 1 in the data page register 3, and all the data sub-registers 3 are 1, so that the data page register 3 is no longer needed, the low data to be written in the next programming in the buffer register can be shifted into the data sub-register 3, and at this time, the status flag bits in LV6 and LV7 are 0, the data to be written in the next programming in the buffer register cannot be shifted into the data sub-register 2;
step 302: as shown in fig. 9, it is determined that low data has been shifted into the data sub-register 3, and then cyclic sequential verification is performed, if the status flag bit in LV6 becomes 1, as shown in fig. 10, the LV6 passes through, which means that all the data of LV0 to LV6 in the three sub-data registers are written, all the data of LV0 to LV6 become 1, and after the status flag bit in LV6 is 1, the LV7 is 1 in the data page register 2, and all the data sub-registers 2 are 1, so that the data page register 2 is no longer needed, and the data to be written in by next programming in the cache register can be shifted into the data sub-register 2, and the status flag bit in LV7 is 0 at this time; if the state identification bit in the LV6 is 0, continuing to circularly judge; when the status flag bit of LV5 is 1, but low data is not available, and the loop determination is continued, after the status flag bit of LV6 is 1, the low data comes, the low data is allowed to be inserted into data register 3, and then it is determined whether there is medium data, if yes, the medium data is inserted into data register 2; if LV6 fails or does not have low data or medium data at this time, the cyclic sequential check is continued; there is another special case that when both the state flag bits of LV5 and LV6 are 1 and both the low data and the medium data are not received, before the state flag bit of LV7 is not 1, the low data and the medium data to be written in next programming are put into the corresponding positions of the data register, the high data are put into the buffer register as they are, and the data sub-register 1 is waited for the next programming.
Step 303: as shown in fig. 11, after the status flag bits of LV5 and LV6 are both determined to be 1, and both the low data and the middle data to be written in the next programming are already shifted into the data sub-register 3 and the data sub-register 2, if the status flag bit of LV7 is 1, the high data to be written in the next programming is already in the buffer register, and the high data to be written in the next programming is placed into the data register 1 after the next programming is started.
Based on the flash memory provided by the embodiment of the present invention, the embodiment of the present invention further provides a data writing method of the flash memory, including:
in the one-time programming process, the low and middle page data which needs to be written in the next programming is moved from the cache register to the data register, and the high data is stored in the cache; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; after the data register stores the page data of the LP, the MP and the UP, writing the page data stored by the data register into a flash memory array;
after page data with the types of LP, MP and UP are stored in the data register, performing code conversion on the page data stored in the data register to obtain corresponding state codes with different state bits; wherein the different status bits include a status identification bit for indicating that page data is moved from the cache register to the data register. Three pages of different types of data shifted into the data register are encoded, and the three pages of data of low, medium and high types are subjected to encoding conversion to obtain a state encoding table, wherein the state encoding table comprises 8 state bits, and the state bits comprise LV0, LV1, LV2 to LV 7. Fig. 5 is a state coding table of a user without code conversion in a data register, fig. 6 is a state coding table stored in a data register after code conversion, it can be seen that corresponding sub data registers in the data register sequentially store three pages of data of low, medium and high, data sub register 3 stores low data, data sub register 2 stores medium data, data sub register 1 stores high data, each state bit before code conversion is composed of 3 bits, 3 bits are respectively from LP/MP/UP, and after code conversion, the state coding table after code conversion is fixed, as shown in the data in fig. 6, data of LV5 is coded from 011 to 110, data of LV6 is coded from 001 to 101, and data of LV7 is coded from 101 to 011. The encoded LV5 is 110,0 is indicated by a circle in the data sub-register 3, and the bit is a state identification bit included in the state bit LV5 for indicating that the low data page is moved from the buffer register to the data register; 0 in LV6 is in data sub-register 2, and the bit is that status bits LV6 includes status flag bits for indicating that the medium data page is moved from the cache register to the data register; similarly, 0 in LV7 in data sub-register 1. After encoding, all status flag bits indicating that the page data is moved from the cache register to the data register become 0.
Before performing code conversion on the page data stored in the data register, controlling the page data in the cache register to move to the data register, so that the page type of the page data stored in the data register comprises the LP, the MP and the UP. And after the page data in the cache register is moved to the data register, releasing the cache register so that the cache register continues to store the next page data written according to the specific type sorting.
After the page data stored in the data register is subjected to coding conversion, the state coding cycles of the different state bits are sequentially checked from high bits to low bits, and whether the page data in the cache register is moved to the data register is judged according to a checking result. The data register comprises a plurality of subdata registers for storing page data of different page types, and different state identification bits correspond to different subdata registers; correspondingly, the determining whether to move the page data in the cache register to the data register according to the check result includes:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification. When data is written into the flash memory array, the state code is changed, the state identification bit of LV7 in the data sub-register 1 of LV7 is judged firstly, if the state identification bit is 1, the state flag bit of LV6 in the data sub-register 2 and the state flag bit of LV5 in the data page register 1 are not judged any more, and the data in the cache register cannot be indicated to be moved into the data register; if the status flag bit in LV7 is 0, the status flag bit in LV6 is continuously determined, if 1, it indicates that the data to be written by the next program stored in the cache register is shifted into the data sub-register 2, if 0, the status flag bit in LV5 is continuously determined, if 0, the loop determination is continuously performed, if the status flag bit in LV5 is 1, it indicates that the low data to be written by the next program stored in the cache register is shifted into the data sub-register 3, because the data writing sequence is low, high, the sequence of shifting from the cache into the data register is also low, high, and therefore, the status flag bit in LV5 is 1 first, then the status flag bit in LV6 is 1 again, it indicates that the data to be written by the next program stored in the cache register is shifted into the data sub-register 2, finally the status flag bit in LV7 is 1, the high data to be written by the next program is put into the cache register, the programming is finished and the high data in the buffer waits for the next program shift into the data sub-register 1.
And when the state code corresponding to the state identification bit passes the check and the page data stored in the cache register is empty, controlling to execute the next cyclic check, and when determining that the page data is stored in the cache register, controlling the page data stored in the cache register to move to the sub-data register corresponding to the state identification bit through which the check of the data passes. When the status flag bit of LV5 is 1, but low data is not available, and the loop determination is continued, after the status flag bit of LV6 is 1, the low data comes, the low data is allowed to be inserted into data register 3, and then it is determined whether there is medium data, if yes, the medium data is inserted into data register 2; if LV6 fails or does not have low data or medium data at this time, the cyclic sequential check is continued;
and when the status flag bit for indicating the completion of the writing of the page data passes verification, controlling to end the programming. I.e., all of the state flags in LV5, LV6, and LV7 are 1, the programming ends.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (20)

1. A flash memory, comprising:
a cache register for caching page data of a single page size; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; one physical page includes: one said LP, one said MP, and one said UP;
a data register, comprising: a sub data register storing page data of different page types;
the flash memory array is used for storing the page data written by the controller;
the controller is respectively connected with the cache register and the data register, and is configured to allow the cache register to insert page data of an (N +1) th physical page and allow page data of an (N +1) th physical page currently cached in the cache register to be moved from the cache register to a sub data register which is free corresponding to a page type of the page data of the (N +1) th physical page currently cached by the cache register in a process that the data register writes the nth physical page into the flash memory array; wherein N is a natural number.
2. The flash memory of claim 1,
the controller is further configured to control writing of the page data stored in the data register into the flash memory array after the page data of the LP, the MP, and the UP are stored in the data register.
3. The flash memory of claim 1,
the controller is further configured to perform code conversion on the page data stored in the data register after the page data of the types LP, MP, and UP are stored in the data register, so as to obtain corresponding state codes of different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
4. A flash memory device according to claim 3,
the controller is further configured to control the page data in the cache register to move to the data register before performing transcoding on the page data stored in the data register, so that the page type of the page data stored in the data register includes the LP, the MP, and the UP.
5. A flash memory device according to claim 4,
the controller is further configured to release the cache register after the page data in the cache register is moved to the data register, so that the cache register continues to store the next page data written according to the specific type sequence.
6. A flash memory device according to claim 3,
and the controller is further configured to perform sequential cyclic check on the state codes of the different state bits from a high bit to a low bit after performing code conversion on the page data stored in the data register, and determine whether to move the page data in the cache register to the data register according to a check result.
7. The flash memory of claim 6 wherein different of said status flag bits correspond to different sub-data registers;
the controller is further configured to control the page data in the cache register to move to the sub-data register corresponding to the status flag bit that passes the check when the status code corresponding to the status flag bit in the different status bits passes the check.
8. A flash memory device according to claim 7,
the controller is further configured to control to execute sequential cyclic check of a next state code when the state code corresponding to the state identification bit passes check and the page data stored in the cache register is empty, and control the page data stored in the cache register to move to the sub-data register corresponding to the state identification bit where the check of the data passes when it is determined that the page data is stored in the cache register.
9. The flash memory device of claim 6 wherein said different status bits further include a status identification bit for indicating completion of writing of page data;
the controller is further configured to control to end the process of writing the physical page into the flash memory array when the status flag indicating that the page data write is completed passes verification.
10. Flash memory device according to any one of claims 1 to 9,
the cache register is further used for caching reference page data with a single page size written according to a specific type sequence, and the reference page data is used for indicating the execution of first programming;
the data register is further used for caching the reference page data of different page types moved from the cache register;
the controller is further configured to move the reference page data in the cache register to the data register when the first programming starts, so that the data register stores page data of the types LP, MP, and UP, respectively, and write the page data stored in the data register into the flash memory array.
11. A method for writing data to a flash memory, the method comprising:
writing page data of the Nth physical page stored by the data register into the flash memory array; wherein N is a natural number; the data register comprises a subdata register for storing page data of different page types; the page type to which the page data belongs is one of: low page LP, middle page MP, high page UP; one physical page includes: one said LP, one said MP, and one said UP;
in the process that the data register writes the nth physical page into the flash memory array, allowing the cache register to insert the page data of the (N +1) th physical page, and allowing the page data of the (N +1) th physical page currently cached in the cache register to be moved from the cache register to a sub data register which is free corresponding to the page type of the page data of the (N +1) th physical page currently cached by the cache register.
12. The data writing method of claim 11, wherein the method further comprises:
after the data register stores the page data of the LP, the MP, and the UP, the page data stored by the data register is written to the flash memory array.
13. The data writing method of claim 11, wherein the method further comprises:
after page data with the types of LP, MP and UP are stored in the data register, performing code conversion on the page data stored in the data register to obtain corresponding state codes with different state bits;
wherein the different status bits include status identification bits for indicating that page data is moved from the cache register to the data register.
14. The data writing method of claim 13, wherein the method further comprises:
before performing code conversion on the page data stored in the data register, controlling the page data in the cache register to move to the data register, so that the page type of the page data stored in the data register comprises the LP, the MP and the UP.
15. The data writing method of claim 14, wherein the method further comprises:
and after the page data in the cache register is moved to the data register, releasing the cache register so that the cache register continues to store the next page data written according to the specific type sorting.
16. The data writing method of claim 13, wherein the method further comprises:
after the page data stored in the data register is subjected to coding conversion, the state coding cycles of the different state bits are sequentially checked from high bits to low bits, and whether the page data in the cache register is moved to the data register is judged according to a checking result.
17. The data writing method of claim 16, wherein different status flag bits correspond to different sub data registers;
correspondingly, the determining whether to move the page data in the cache register to the data register according to the check result includes:
and when the state code corresponding to the state identification bit in the different state bits passes the verification, controlling the page data in the cache register to move to the sub-data register corresponding to the state identification bit passing the verification.
18. The data writing method of claim 17, wherein the method further comprises:
and when the state code corresponding to the state identification bit passes the check and the page data stored in the cache register is empty, controlling to execute the next sequential cyclic check of the state code, and when determining that the page data is stored in the cache register, controlling the page data stored in the cache register to move to the sub-data register corresponding to the state identification bit through which the check of the data passes.
19. The data writing method according to claim 16, wherein the different status bits further include a status flag bit for indicating completion of writing of page data;
correspondingly, the method further comprises the following steps:
and when the status flag bit for indicating the completion of the writing of the page data passes the verification, controlling to end the process of writing the physical page into the flash memory array.
20. The data writing method according to any one of claims 11 to 19, further comprising:
when first programming is started, moving reference page data stored in the cache register to the data register, so that page data of the types LP, MP and UP are stored in the data register, and writing the page data stored in the data register into the flash memory array;
wherein the reference page data is used to indicate execution of first programming.
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