CN113206090A - CFET structure, preparation method thereof and semiconductor device applying CFET structure - Google Patents
CFET structure, preparation method thereof and semiconductor device applying CFET structure Download PDFInfo
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
The invention relates to a CFET structure, a preparation method thereof and a semiconductor device using the same, in particular to a method for preparing a substrate, wherein a base fin structure is formed on the substrate, a first stack part and a second stack part are formed on the base fin, and the second stack part is vertically stacked on the first stack part; the first stack portion has at least one I-type channel structure; the second stack part is provided with at least one II-type channel structure; the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part. Forming a first surrounding type grid structure which is arranged around the I-shaped channel structure; and forming a second surrounding type grid structure which is arranged around the II-type channel structure. Compared with the prior art, the invention has the beneficial technical effects that: according to the invention, Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet is realized by using a method of combining side wall masking and selective step etching, so that the purpose of simultaneously optimizing the crystal orientations of NMOS and PMOS channels is achieved, and the performance of NMOS and PMOS on a single wafer is simultaneously optimized.
Description
Technical Field
The invention relates to the technical field of semiconductor integration, in particular to a manufacturing method of a CFET structure and a semiconductor device.
Background
In a Complementary Field-Effect Transistor (CFET) device structure, an nFET and a pFET share a gate electrode as a signal input terminal and a drain electrode as a signal output terminal, and a source electrode is respectively grounded and powered. The method greatly saves the chip area, enhances the driving current of the device and improves the integration level of the chip device while keeping the electrical integrity of the vertical stack nanowire or nanosheet surrounding type grid field effect transistor. The n and p vertical stacks greatly reduce the area of a CMOS circuit and realize ultrahigh integration level. Area scaling brings power and performance advantages. For electrostatic control, a complementary Gate-All-Around (GAA) structure composed of n, p vertical stacks, NFETs and PFETs can use different crystal orientations and different channel materials to optimize NFET and PFET carrier mobility. Compared with the traditional transistor, the CFET has the complete function of a CMOS transistor, is close to an ideal sub-threshold swing amplitude, extremely low in leakage current, extremely low in noise, smaller in mobility deterioration and high in reliability, and the GAA can better control the gate, so that the performance is improved, and the leakage is reduced.
In the CFET structure manufactured by an epitaxial channel mode at present, a PMOS is usually arranged at the bottom layer, and an NMOS is arranged at the top layer, so that a stress scheme is conveniently applied to a bottom layer PMOS device to improve the performance of the PMOS device; because the top-layer device cannot apply stress or the benefit of the existing stress scheme is low, the top-layer NMOS device has poor performance and the balance between NMOS and PMOS is difficult to regulate; in the CFET structure manufactured by an epitaxial channel mode at present, the crystal faces of channels of an NMOS and a PMOS are the same crystal face, and the mobility of electrons and holes cannot be optimized simultaneously.
Disclosure of Invention
In order to overcome the technical problems, the invention discloses the following technical scheme:
a CFET structure, characterized by: the method comprises the following steps:
a substrate;
a first stack portion disposed on the substrate and having at least one I-type channel structure;
a second stack portion vertically stacked on the first stack portion, and having at least one type II channel structure;
a first surrounding gate structure disposed around the I-type channel structure;
a second surrounding gate structure disposed around the II-type channel structure;
the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part.
A method of making a CFET device, comprising: the method comprises the following steps:
providing a substrate, forming a base fin structure on the substrate,
forming a first stack portion and a second stack portion on the base fin, the second stack portion being vertically stacked on the first stack portion; the first stack portion has at least one I-type channel structure; the second stack part is provided with at least one II-type channel structure; the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part;
forming a first surrounding type grid structure which is arranged around the I-shaped channel structure;
and forming a second surrounding type grid structure which is arranged around the II-type channel structure.
Compared with the prior art, the invention has the beneficial technical effects that: according to the invention, Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet is realized by using a method of combining side wall masking and selective step etching, so that the purpose of simultaneously optimizing the crystal orientations of NMOS and PMOS channels is achieved, and the performance of NMOS and PMOS on a single wafer is simultaneously optimized. The device preparation process is compatible with the mainstream MOS device process. According to the invention, by the method of combining the side wall masking with the selective etching process, an additional photoetching process is not required to be introduced, and the flow is very simple; by the method of combining the side wall masking and the selective etching process, the formed top layer device and the bottom layer device have the channel self-alignment characteristic, and the control of the thickness and the width of a channel is greatly ensured; the formed Vertical Nano-sheet on Horizontal Nano-sheet structure can form channel structures with different crystal faces on the top layer and the bottom layer, can simultaneously optimize the mobility of electrons and holes, and achieves the effect of simultaneously optimizing NMOS and PMOS devices; the bottom layer Horizontal Nano-sheet can apply stress to the device by using a conventional source-drain epitaxial stress scheme, so that the performance of the device is improved; the driving capability and performance of the device can be adjusted by increasing the number of the nanosheets and adjusting the width of the nanosheets at the bottom layer; the top-layer Vertical Nano-sheet device can adjust the driving capability and performance of the top-layer device by adjusting the height of the Nano sheets and the number of the Nano sheets; under the condition of not increasing the area, the top-layer device can be provided with two nanosheets, the bottom-layer device is provided with one nanosheet, and in the structure of N on P, the performance of the top-layer NMOS device is greatly increased, so that NP balance is realized; the number of the nanosheets of the top-layer device can be regulated and controlled by adopting a conventional Fin Cut process.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings.
Fig. 1 is a schematic view of a fabrication substrate for a CFET device of the present invention.
FIG. 2 is a schematic view of the present invention forming a top mold.
FIG. 3 is a schematic diagram of forming an interfacial oxide layer according to the present invention
FIG. 4 is a schematic view of forming a sidewall spacer according to the present invention.
FIG. 5 is a schematic view of the present invention.
FIG. 6 is a schematic view of the present invention.
FIG. 7 is a schematic view of the present invention.
FIG. 8 is a schematic view of the present invention.
Fig. 9 is a schematic diagram of etching a superlattice stack in accordance with the invention.
Figure 10 is a schematic diagram of shallow trench isolation region formation in accordance with the present invention.
FIG. 11 is a schematic diagram of forming a dummy gate according to the present invention.
Fig. 12 is a schematic diagram of etching a superlattice stack to form a horizontal conduction channel in accordance with the invention.
FIG. 13 is a schematic diagram of the channel relief performed by the present invention.
Fig. 14 is a schematic diagram of a gate-all-around CFET device according to the present invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It is to be understood that such description is merely illustrative and not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.
Various structural schematics according to embodiments of the present invention are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present invention, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In the present embodiment, a method for fabricating a CFET device is provided. Referring to the drawings, which are schematic views of the manufacturing process of the CFET device of the present invention, the process of manufacturing the CFET device 100 includes:
providing a substrate 100;
the fabrication of a CFET device begins with a base 101, and a first step of epitaxial growth on the lowest substrate 101 of the base 100 forms a stack of multiple Si/SiGe superlattice structures, the substrate 101 being part of a semiconductor wafer suitable for forming one or more IC devices, for example a silicon (Si) substrate may be employed. The thickness of each layer in the superlattice structure directly determines the height of the nanosheet channels and the electrostatic properties. In one embodiment, the stack of the Si/SiGe superlattice structure is three periods. The thickness of the SiGe layer 102 is greater than the thickness of the Si layer 101' in the remaining superlattice structure period, except that the thickness of the Si sinker 101 in the bottommost period is greater than the thickness of the SiGe layer 102, wherein the Si layer materials in the Si/SiGe superlattice structure are all type I Si, as shown in fig. 1.
A type II Si layer 103 is then deposited on the top surface of the uppermost SiGe layer 102 of the stack of Si/SiGe superlattice structures, the thickness of the type II Si layer 103 being the largest in the substrate 100. Forming an interface oxide layer 104 on the upper surface of the type II Si layer 103, wherein the interface oxide layer 104 is SiO2Layer of silicon nitride (SiN) sequentially deposited on the interfacial oxide layer 104X) Layer 105 and amorphous silicon layer (a-Si)106, to the completion of the fabrication of substrate 100 for the fabrication of CFET devices. The deposition process may be thermal oxidation, chemical vapor deposition, sputtering, etc.
The amorphous silicon layer (a-Si)106 is patterned by photolithography, etching, etc. to form top molds 106', and in one embodiment, the amorphous silicon layer (a-Si)106 forms a long stripe pattern with equal intervals, and silicon nitride (SiN) is exposed between adjacent top molds 106X) The surface of layer 105, as shown in fig. 2.
Then the silicon nitride (SiN) is exposed in the top mold 106X) The surface of the layer 105 is deposited with an oxide, such as thermal oxidation, chemical vapor deposition (cvd), sputtering, etc., to form an interfacial oxide layer 107, which in one embodiment is SiO2Layers as shown in fig. 3.
Next, an etching process is used to etch away the interfacial oxide layer 107 on the upper surface of the top mold 106 ', so that the interfacial oxide layers 107 on both sides of the top mold 106 ' form sidewalls 107 ', as shown in fig. 4.
With side wall 107'And the top mold 106' is used as a mask, and the etching process is adopted to continuously etch silicon nitride (SiN)X) Layer 105 and interfacial oxide layer 104, forming silicon nitride (SiN) patterned in conformity with top mold 106X) A mold 105 ' and an interfacial oxidation mold 104 ', adjacent to the interfacial oxidation mold 104 ' exposing the type II Si layer 103, as shown in fig. 5.
Etching is continued by using the side walls 107 ' and the top mold 106 ' as masks, the type II Si layer 103 is etched, partial etching is performed on the Ge layer of the uppermost layer of the Si/SiGe superlattice structure portion, and then the top mold 105 ' is etched away, as shown in fig. 6.
One or more side walls 107' are etched by adopting an etching process, so that the number of top-layer channels can be regulated and controlled. Etching silicon nitride (SiN) by using the reserved side wall 107' as maskX) The mold 105 'and the interface oxidation mold 104' form silicon nitride (SiN)X) The plug 105 "and the interfacial oxidation plug 104" to expose the type II Si layer 103 between adjacent interfacial oxidation plugs 104 ", as shown in fig. 7 and 8.
The remaining spacers 107 are used as masks to continue etching the type II Si layer 103, forming a plurality of top vertical conduction channels 103 ″ in the type II Si layer 103. The vertical conduction channel 103 "Si crystal orientation is horizontal as shown in fig. 9. In one embodiment, the number of vertical conductive channels 103' is an odd number.
The first sidewalls 107', silicon nitride (SiN) are then etched awayX) The mandrel 105 "and the interfacial oxidation mandrel 104" and the etching of the stack of Si/SiGe superlattice structures continues to the substrate 101 layer so that the substrate 101 layer is partially etched. To this end, a plurality of periodically distributed fins are formed. A Shallow Trench Isolation (STI) 108 is disposed between two adjacent fins, and in one embodiment, the STI 108 is made of SiO2Which functions to space adjacent transistors as shown in fig. 10.
A sacrificial oxide layer 109 is then deposited on the surface of the fin, in one embodiment the sacrificial oxide layer 109 is SiO2. Dummy gates 110 are formed to be periodically distributed in a direction perpendicular to the previous fin line. The material used for the dummy gate 110 may be, for example, polysilicon (PolySi), as shown in the figureShown at 11.
The fin between the gates needs to be cleaned up and the space left clear for growing the source and drain in later steps. The SiGe material exposed at the surface is etched in by, for example, an isotropic etch, which includes an isotropic etch to uniformly etch in any direction. Such as isotropic, vapor phase etching. Such vapor phase etching may have a 100: 1 etch selectivity.
And performing epitaxial growth of a source/drain (S/D) between the cleaned grid electrode and the Si surface. If pFET, the source drain material is boron doped SiGe (SiGe: B), and if nFET, the source drain material is phosphorus doped SiC (SiC: P): firstly, epitaxially growing a source/drain of a lower-layer FET, then depositing an insulating medium to layer the upper FET and the lower FET, flattening the insulating medium, and then adopting an etching process to connect the source/drain of the lower-layer FET device to the BPR.
By etching process, the dummy gate and the sacrificial oxide layer 109 formed by the polysilicon (PolySi) are etched away, i.e. the dummy gate is removed, the channel is released, and the horizontal conduction channel 101 ″ is formed. The Si crystal orientation of the horizontal conduction channel 101 "is vertical as shown in fig. 12-13.
So far, a first stack part is formed on the lower layer of the substrate for a horizontal conductive channel FET, and a second stack part is formed on the upper layer for a vertical conductive channel FET; the first stack portion has at least one I-type channel structure 101 "; the second stack portion has at least one type II channel structure 103 ".
A wrap-around gate structure is then formed around each of the released channel materials. In one embodiment, the type I and type II wrap-around gate structures may be electrically connected such that they are complementary to each other; the I-shaped surrounding type grid structure is completely arranged around the I-shaped channel structure; and the II-type surrounding grid structure is completely arranged around the II-type channel structure;
an interface layer 1012 and a metal work function layer 1011 are deposited around the I-type and II-type channel structures, and the high-k dielectric layer may include a silicon oxide gate oxide. In one embodiment, a type I metal gate work function layer is deposited on the high-K dielectric layer outside the type I channel structure, and a type II metal gate work function layer is deposited on the high-K dielectric layer outside the type II channel structure.
The cleaned dummy gate spaces are then deposited with a conductive metal layer 1013. The conductive metal layer may be deposited with tungsten (W) or cobalt (Co).
In one embodiment, the I-type channel is an nFET channel, the II-type channel is a pFET channel, the I-type metal gate work function layer is an Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx layer or a composite layer of these, and the II-type metal gate work function layer is a TiN, TaN, TiNx, TaNx, TiNSi layer or a composite layer of these.
In one embodiment, the I-type channel is a pFET channel, the II-type channel is an nFET channel, the I-type metal gate work function layer is a TiN, TaN, TiNx, TaNx, TiNSi layer or a composite layer of several of them, and the II-type metal gate work function layer is an Al, TiAl, TiAlx, tiaxcx, TiCx, TaCx layer or a composite layer of several of them.
The thickness of the metal gate work function layer outside the I, II type FET stacked on top of the CEFT device is adjusted by the process of the embodiment, so that the threshold value of the I, II type FET is adjusted.
The CEFT device adjusts the threshold values of different N/PFET devices by adjusting the thicknesses of the I-type metal gate work function layer and the II-type metal gate work function layer.
According to an embodiment of the present invention, a CFET device structure is provided, an example structure of the CFET of the present invention is shown in fig. 14. As illustrated in fig. 14, the CFET device includes:
a substrate;
a first stack portion disposed on the substrate and having at least one I-type channel structure;
a second stack portion vertically stacked on the first stack portion, and having at least one type II channel structure;
a first surrounding gate structure disposed around the I-type channel structure;
a second surrounding gate structure disposed around the II-type channel structure;
the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part.
The first stack portion includes one or more I-type nfets and the second stack portion includes one or more pfets, or the first stack portion includes one or more nfets and the second stack portion includes one or more pfets.
The CEFT device structure described in the embodiment of the present invention may be prepared by the method described in the foregoing embodiment of the present invention, and based on the method described in the first embodiment of the present invention, a person skilled in the art can understand the specific structure and the deformation of the device, and thus details are not described here.
The invention also discloses a semiconductor device which comprises the CFET structure.
The technical scheme in the embodiment of the application at least has the following technical effects or advantages: according to the invention, Vertical integration of Vertical Nano-sheet and Horizontal Nano-sheet is realized by using a method of combining side wall masking and selective step etching, so that the purpose of simultaneously optimizing the crystal orientations of NMOS and PMOS channels is achieved, and the performance of NMOS and PMOS on a single wafer is simultaneously optimized. The device preparation process is compatible with the mainstream MOS device process. According to the invention, by the method of combining the side wall masking with the selective etching process, an additional photoetching process is not required to be introduced, and the flow is very simple; by the method of combining the side wall masking and the selective etching process, the formed top layer device and the bottom layer device have the channel self-alignment characteristic, and the control of the thickness and the width of a channel is greatly ensured; the formed Vertical Nano-sheet on Horizontal Nano-sheet structure can form channel structures with different crystal faces on the top layer and the bottom layer, can simultaneously optimize the mobility of electrons and holes, and achieves the effect of simultaneously optimizing NMOS and PMOS devices; the bottom layer Horizontal Nano-sheet can apply stress to the device by using a conventional source-drain epitaxial stress scheme, so that the performance of the device is improved; the driving capability and performance of the device can be adjusted by increasing the number of the nanosheets and adjusting the width of the nanosheets on the bottom layer of the Horizontal Nano-sheet; the top-layer Vertical Nano-sheet device can adjust the driving capability and performance of the top-layer device by adjusting the height of the Nano sheets and the number of the Nano sheets; under the condition of not increasing the area, the top-layer device can be provided with two nanosheets, the bottom-layer device is provided with one nanosheet, and in the structure of N on P, the performance of the top-layer NMOS device is greatly increased, so that NP balance is realized; the number of the nanosheets of the top-layer device can be regulated and controlled by adopting a conventional Fin Cut process.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (19)
1. A CFET structure, characterized by: the method comprises the following steps:
a substrate;
a first stack portion disposed on the substrate and having at least one I-type channel structure;
a second stack portion vertically stacked on the first stack portion, and having at least one type II channel structure;
a first surrounding gate structure disposed around the I-type channel structure;
a second surrounding gate structure disposed around the II-type channel structure;
the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part.
2. A CEFT structure as claimed in claim 1 wherein: the crystal plane direction of the I-type channel structure in the first stack part is a vertical direction, and the crystal plane direction of the II-type channel structure in the second stack part is a horizontal direction.
3. A CEFT structure as claimed in claim 1 or 2 wherein: the I-type channel is an nFET channel and the II-type channel is a pFET channel.
4. A CEFT structure as claimed in claim 1 or 2 wherein: the I-type channel is a pFET channel and the II-type channel is an nFET channel.
5. A CEFT structure as claimed in claim 1 or 2 wherein: the first surrounding type grid structure and the second surrounding type grid structure are electrically connected to form a complementary field effect transistor.
6. A CEFT structure as claimed in claim 1 or 2 wherein: the I-channel structure is formed of type I Si and the II-channel structure is formed of type II Si.
7. A CEFT structure as claimed in claim 1 or 2 wherein: the first surrounding type grid structure comprises an I-shaped metal grid work function layer; the second surrounding type grid structure comprises a II-type metal grid work function layer.
8. A CEFT structure as claimed in claim 7, in which: the I-type metal gate work function layer is a TiN, TaN, TiNx, TaNx, TiNSi layer or a composite layer of a plurality of layers.
9. A CEFT structure as claimed in claim 8, wherein: the II-type metal gate work function layer is an Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx layer or a composite layer of a plurality of layers.
10. A method of making a CFET device, comprising: the method comprises the following steps:
providing a substrate, forming a base fin structure on the substrate,
forming a first stack portion and a second stack portion on the base fin, the second stack portion being vertically stacked on the first stack portion; the first stack portion has at least one I-type channel structure; the second stack part is provided with at least one II-type channel structure; the crystal plane direction of the I-type channel structure in the first stack part is vertical to the crystal plane direction of the II-type channel structure in the second stack part;
forming a first surrounding type grid structure which is arranged around the I-shaped channel structure;
and forming a second surrounding type grid structure which is arranged around the II-type channel structure.
11. The method of claim 10, wherein: the crystal plane direction of the I-type channel structure in the first stack part is a vertical direction, and the crystal plane direction of the II-type channel structure in the second stack part is a horizontal direction.
12. The method according to claim 10 or 11, characterized in that: the I-type channel is an nFET channel and the II-type channel is a pFET channel.
13. The method according to claim 10 or 11, characterized in that: the I-type channel is a pFET channel and the II-type channel is an nFET channel.
14. The method according to claim 10 or 11, characterized in that: the first surrounding type grid structure and the second surrounding type grid structure are electrically connected to form a complementary field effect transistor.
15. The method according to claim 10 or 11, characterized in that: the I-channel structure is formed of type I Si and the II-channel structure is formed of type II Si.
16. The method according to claim 9 or 10, characterized in that: the first surrounding type grid structure comprises an I-shaped metal grid work function layer; the second surrounding type grid structure comprises a II-type metal grid work function layer.
17. The method of claim 16, wherein: the I-type metal gate work function layer is a TiN, TaN, TiNx, TaNx, TiNSi layer or a composite layer of a plurality of layers.
18. The method of claim 17, wherein: the II-type metal gate work function layer is an Al, TiAl, TiAlx, TiAlCx, TiCx, TaCx layer or a composite layer of a plurality of layers.
19. A semiconductor device, characterized in that it comprises a CFET structure according to any of claims 1-9.
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